Role Overview

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary ASIC Design Student to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, designing complex solutions that sit at the heart of our most ambitious connectivity projects.

As an ASIC Design Student, you won't just build chips—you will be part of a team defining the next generation of AI infrastructure main components. The complex digital blocks under your micro-architecture and implementation responsibilities will power the world's largest AI clusters. You will own the journey from high-level definition through RTL implementation and backend support, transforming complex logic challenges into elegant, high-performance hardware. If you thrive on solving unnamed challenges in deep-submicron processes and want to shape the digital design foundation for AI infrastructure connectivity, this is your opportunity.

Key Responsibilities

• Assist in the development of micro-architecture, RTL coding, and debugging for complex digital blocks
• Utilize industry-leading EDA tools (Lint, CDC, Synthesis) to ensure designs are robust and power-efficient
• Work closely with the verification team to run simulations, analyze results, and ensure design quality
• Interact with Architecture and Backend teams to understand the full chip development lifecycle
• Help leverage AI-based automation tools to optimize engineering workflows

Basic Qualifications

• Pursuing a Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical field
• Strong academic record with a focus on Digital Logic Design and VLSI
• Ability to work at least 2 days per week at our Haifa/Tel Aviv center
• Solid understanding of logic design principles and hardware description languages (Verilog or SystemVerilog)
• A "can-do" attitude with a passion for solving complex technical challenges
• Fluent in Hebrew and English with the ability to work effectively in a team environment

Preferred Qualifications

• Hands-on experience with FPGA projects or university-level tape-out projects
• Proficiency in Python, Perl, or Bash for automation
• Completed courses in Computer Architecture, Synthesis, or Static Timing Analysis (STA)
• Basic familiarity with high-speed protocols like PCIe or DDR

Role Overview

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Design Verification Student to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, designing complex solutions that sit at the heart of our most ambitious connectivity projects.

As a Design Verification Student, you will be at the forefront of quality, learning how to ensure that the chips powering the world's largest AI clusters are bug-free and robust.
This isn't just about running tests - it’s an opportunity to learn advanced verification methodologies (UVM/SystemVerilog) alongside world-class engineers. You will support the development of sophisticated testbenches and help verify high-performance digital blocks that sit at the heart of AI infrastructure.

Key Responsibilities

• Assist in building and maintaining System Verilog/UVM-based testbenches, including monitors, checkers, and functional coverage models
• Run simulations, analyze failures, and work with the design team to debug and resolve RTL issues
• Help define and implement functional coverage and assertions to ensure all "corner cases" of the design are tested
• Utilize and improve scripting (Python/Tcl) to streamline verification flows and result reporting
• Partner with Design Engineers to understand block specifications and ensure the verification plan matches the design intent

Basic Qualifications

• Pursuing a Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical field
• Ability to work at least 2 days a week at our Haifa/Tel Aviv center
• Strong understanding of Digital Logic and at least one programming language (C/C++ or Python)
• Basic familiarity with Verilog or SystemVerilog from academic projects or lab work
• A natural curiosity for "breaking things" and finding bugs, with a strong attention to detail
• Fluent in Hebrew and English with the ability to work effectively in a team environment

Preferred Qualifications

• Completed courses in VLSI, Digital Systems, or Computer Architecture
• Proficiency in Python, Perl, or Tcl
• Any prior exposure to UVM/OVM or constrained-random verification is a major plus
• Basic understanding of protocols like PCIe, Ethernet, or DDR

Role Overview

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Senior ASIC Design Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful product ownership in a new site, designing the digital blocks that sit at the heart of our most ambitious connectivity projects.

As a Senior ASIC Design Engineer, you won't just build chips—you will be part of a team defining the next generation of AI infrastructure main components. The complex digital blocks under your micro-architecture and implementation responsibilities will power the world's largest AI clusters. You will own the journey from high-level definition through RTL implementation and backend support, transforming complex logic challenges into elegant, high-performance hardware. If you thrive on solving challenging problems in deep-submicron processes and want to contribute to the digital design foundation for AI infrastructure connectivity, this is your opportunity.

Key Responsibilities

• Design Ownership & Implementation

  • Own the journey from high-level definition through micro-architecture, coding, and debug to backend implementation support
  • Tackle complex logic challenges and transform them into elegant, high-performance hardware solutions
  • Serve as the point of contact for your logic blocks, interacting with Architecture, Verification, and Backend teams

• Quality Assurance & Design Optimization

  • Utilize industry-leading EDA tools (Lint, CDC, Synthesis, Timing, Power) and in-house quality assurance tools to ensure designs are robust, scalable, and power-efficient
  • Apply design techniques to meet PPA (Power, Performance, Area) targets
  • Contribute to design quality through verification and validation activities

• Methodology Innovation & Collaboration

  • Participate in design methodology improvements and tool automation initiatives
  • Leverage AI assistance tools and contribute to in-house automation development to make engineering workflows faster and smarter
  • Collaborate effectively across teams to ensure seamless integration

Basic Qualifications

• Bachelor's degree in Electrical Engineering or related technical field
• 3+ years of experience in logic design at semiconductor companies
• Knowledge and experience in Verilog and/or SystemVerilog
• Excellent communication skills with ability to work effectively across teams
• Understanding of digital design principles and RTL coding best practices

Preferred Qualifications

• Master's degree in Electrical Engineering or related field
• Knowledge of DDR and PCIe protocols and implementation
• Understanding of power management techniques for low-power design
• Familiarity with Clock Domain Crossing, simulation, debugging, synthesis, and timing analysis
• Proficiency in scripting languages such as Python or Perl
• Experience with high-speed serial interface designs or connectivity protocols

Role Overview

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Front-End CAD Engineer to join our local engineering powerhouse from the ground up.

As a Front-End CAD Engineer, you will be the backbone of our chip design ecosystem. You won’t just be using tools; you’ll be architecting the methodologies, automation scripts, and design flows that enable our hardware teams to push the limits of silicon performance. Your work directly impacts the productivity of the design team and the time-to-market for our next-generation processors.

Key Responsibilities

• Develop, maintain, and optimize RTL generation tools, building automated IPs and SoC schemes
• Create robust applications using Python and Tcl to automate models build, regression and analysis tools and other assisting tools for all disciplines in front-end flows
• Evaluate and integrate Electronic Design Automation (EDA) tools from vendors like Cadence, Synopsys, and Mentor Graphics
• Define the methodologies of usage and integrate AI tools in this fast-growing field impacting all VLSI development flows

Basic Qualifications

• Bachelor’s degree in Electrical Engineering or a related technical field
• 5+ years of hands-on professional experience in relevant industries 
• Proven experience in Python and Tcl within a Linux/Unix environment
• Knowledge and experience in Verilog and/or System Verilog
• Very good communication skills

Preferred Experience

• Strong understanding of the VLSI design cycle, familiarity with clock domain crossing, simulation, debugging, synthesis and timing analysis
• Hands-on experience with industry-standard tools for lint, synthesis, simulation
• Experience with version control systems (Git) and compute cluster management (LSF/SGE)

Who we are looking for

As an Electrical engineering team leader, you will be a contributing member and leader of a new product development team, responsible for the design, simulation, analysis, testing, and integration of hardware.
You will provide technical leadership to a project team to achieve product performance, production, quality, cost, and schedule objectives.

What you will do

• Responsible for all team deliverables
• Responsible for team members mentoring “Hands-on”
  
  

Requirements

• Sc. in Electrical engineering. - Must
• At least 5 years of Experience in Analog and/or Power electronics designs (AC/DC, DC/DC topologies design, Analog circuits design, Operational Amplifiers circuits, Familiarity with modern power components, Noise and Signal integrity concerns. -Must.
• Minimum of 5 years of proven experience in a Board and PCBA design – Must
• Experience and familiarity with hardware design for FPGAs
• Microcontrollers DSP and SOM (Xilinx, ST, Intel SOM modules advantage)
• Experience in VHDL/Verilog at least 3 years
• Experience with interfaces/protocols – PCIe, DDR 3 or 4. - Must
• Familiarity with the common inter chip communication protocols:(I2C, SPI, UART/USART, QSPI). - Must