We are Datadog's in-house product experts. The technical solutions team enables Datadog's worldwide growth by educating potential clients and ensuring that existing customers are happy and successful. A Technical Account Manager (TAM) will continue to provide hands-on technical services to our largest customers by supporting, adopting and providing guidance over the comprehensive suite of products and features available at Datadog. A TAM is held in high regard as an expert and trusted advisor for how IT Operations translates to business value.

At Datadog, we place value in our office culture - the relationships and collaboration it builds and the creativity it brings to the table. We operate as a hybrid workplace to ensure our Datadogs can create a work-life harmony that best fits them.

What You’ll Do:

• Advise on technical support and product adoption for customers in line with pre-sales, post-sales and the renewal processes
• Analyze customer’s IT Operations environment on a regular basis and provide recommendations that will maximize Datadog’s value.
• Be the customer’s advocate by knowing their goals and use cases then suggesting process changes, product adoption, configuration and additional features to meet their requirements
• Participate and prepare for Monthly and Quarterly Business Reviews with customers
• Collaborate with Datadog’s product management, engineering and technical services teams to help identify new features and products
• Continuously evolve best practice to technical product adoption and customer success

Who You Are:

• Someone with a solid technical grounding and hands-on experience of IT Operations
• Confident in your hands on experience AWS, Azure or GCP
• Comfortable scripting languages like Python, Javascript, Ruby, Perl, Go, PHP, or Chef/Puppet etc.
• Skilled in using CI/CD tools e.g. Jenkins, Gitlab etc.
• Knowledgeable about Containerization tools e.g. Docker, Kubernetes or Rancher etc.
• Able to sit up to 4 hours, traveling to and from client sites 
• Able to travel via auto, train or air up to 30% of the time
• Previous experience working as a TAM supporting mid-market and/or Enterprise customers in the cloud space
• Experienced using Datadog and/or other cloud monitoring tools

Datadog values people from all walks of life. We understand not everyone will meet all the above qualifications on day one. That's okay. If you’re passionate about technology and want to grow your skills, we encourage you to apply.

Benefits and Growth:

• Best-in-breed onboarding
• Generous global benefits
• Intra-departmental mentor and buddy program for in-house networking
• New hire stock equity (RSUs) and employee stock purchase plan (ESPP)
• Continuous professional development, product training, and career pathing
• An inclusive company culture, able to join our Community Guilds and Inclusion Talks

Benefits and Growth listed above may vary based on the country of your employment and the nature of your employment with Datadog.

Role Overview

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Design Verification Student to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, designing complex solutions that sit at the heart of our most ambitious connectivity projects.

As a Design Verification Student, you will be at the forefront of quality, learning how to ensure that the chips powering the world's largest AI clusters are bug-free and robust.
This isn't just about running tests - it’s an opportunity to learn advanced verification methodologies (UVM/SystemVerilog) alongside world-class engineers. You will support the development of sophisticated testbenches and help verify high-performance digital blocks that sit at the heart of AI infrastructure.

Key Responsibilities

• Assist in building and maintaining System Verilog/UVM-based testbenches, including monitors, checkers, and functional coverage models
• Run simulations, analyze failures, and work with the design team to debug and resolve RTL issues
• Help define and implement functional coverage and assertions to ensure all "corner cases" of the design are tested
• Utilize and improve scripting (Python/Tcl) to streamline verification flows and result reporting
• Partner with Design Engineers to understand block specifications and ensure the verification plan matches the design intent

Basic Qualifications

• Pursuing a Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical field
• Ability to work at least 2 days a week at our Haifa/Tel Aviv center
• Strong understanding of Digital Logic and at least one programming language (C/C++ or Python)
• Basic familiarity with Verilog or SystemVerilog from academic projects or lab work
• A natural curiosity for "breaking things" and finding bugs, with a strong attention to detail
• Fluent in Hebrew and English with the ability to work effectively in a team environment

Preferred Qualifications

• Completed courses in VLSI, Digital Systems, or Computer Architecture
• Proficiency in Python, Perl, or Tcl
• Any prior exposure to UVM/OVM or constrained-random verification is a major plus
• Basic understanding of protocols like PCIe, Ethernet, or DDR

Role Overview

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Senior ASIC Design Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful product ownership in a new site, designing the digital blocks that sit at the heart of our most ambitious connectivity projects.

As a Senior ASIC Design Engineer, you won't just build chips—you will be part of a team defining the next generation of AI infrastructure main components. The complex digital blocks under your micro-architecture and implementation responsibilities will power the world's largest AI clusters. You will own the journey from high-level definition through RTL implementation and backend support, transforming complex logic challenges into elegant, high-performance hardware. If you thrive on solving challenging problems in deep-submicron processes and want to contribute to the digital design foundation for AI infrastructure connectivity, this is your opportunity.

Key Responsibilities

• Design Ownership & Implementation

  • Own the journey from high-level definition through micro-architecture, coding, and debug to backend implementation support
  • Tackle complex logic challenges and transform them into elegant, high-performance hardware solutions
  • Serve as the point of contact for your logic blocks, interacting with Architecture, Verification, and Backend teams

• Quality Assurance & Design Optimization

  • Utilize industry-leading EDA tools (Lint, CDC, Synthesis, Timing, Power) and in-house quality assurance tools to ensure designs are robust, scalable, and power-efficient
  • Apply design techniques to meet PPA (Power, Performance, Area) targets
  • Contribute to design quality through verification and validation activities

• Methodology Innovation & Collaboration

  • Participate in design methodology improvements and tool automation initiatives
  • Leverage AI assistance tools and contribute to in-house automation development to make engineering workflows faster and smarter
  • Collaborate effectively across teams to ensure seamless integration

Basic Qualifications

• Bachelor's degree in Electrical Engineering or related technical field
• 3+ years of experience in logic design at semiconductor companies
• Knowledge and experience in Verilog and/or SystemVerilog
• Excellent communication skills with ability to work effectively across teams
• Understanding of digital design principles and RTL coding best practices

Preferred Qualifications

• Master's degree in Electrical Engineering or related field
• Knowledge of DDR and PCIe protocols and implementation
• Understanding of power management techniques for low-power design
• Familiarity with Clock Domain Crossing, simulation, debugging, synthesis, and timing analysis
• Proficiency in scripting languages such as Python or Perl
• Experience with high-speed serial interface designs or connectivity protocols

Role Overview

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary ASIC Design Student to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, designing complex solutions that sit at the heart of our most ambitious connectivity projects.

As an ASIC Design Student, you won't just build chips—you will be part of a team defining the next generation of AI infrastructure main components. The complex digital blocks under your micro-architecture and implementation responsibilities will power the world's largest AI clusters. You will own the journey from high-level definition through RTL implementation and backend support, transforming complex logic challenges into elegant, high-performance hardware. If you thrive on solving unnamed challenges in deep-submicron processes and want to shape the digital design foundation for AI infrastructure connectivity, this is your opportunity.

Key Responsibilities

• Assist in the development of micro-architecture, RTL coding, and debugging for complex digital blocks
• Utilize industry-leading EDA tools (Lint, CDC, Synthesis) to ensure designs are robust and power-efficient
• Work closely with the verification team to run simulations, analyze results, and ensure design quality
• Interact with Architecture and Backend teams to understand the full chip development lifecycle
• Help leverage AI-based automation tools to optimize engineering workflows

Basic Qualifications

• Pursuing a Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical field
• Strong academic record with a focus on Digital Logic Design and VLSI
• Ability to work at least 2 days per week at our Haifa/Tel Aviv center
• Solid understanding of logic design principles and hardware description languages (Verilog or SystemVerilog)
• A "can-do" attitude with a passion for solving complex technical challenges
• Fluent in Hebrew and English with the ability to work effectively in a team environment

Preferred Qualifications

• Hands-on experience with FPGA projects or university-level tape-out projects
• Proficiency in Python, Perl, or Bash for automation
• Completed courses in Computer Architecture, Synthesis, or Static Timing Analysis (STA)
• Basic familiarity with high-speed protocols like PCIe or DDR

Role Overview

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Physical Design Engineer specializing in EMIR & Power Integrity to join our local engineering powerhouse from the ground up.

This is a unique opportunity to take on meaningful technical ownership in a new site, executing the backend power methodologies for chips that power the world's largest AI clusters. As a Physical Design Engineer, you will be a core technical contributor ensuring the power robustness and long-term reliability of our high-performance connectivity silicon.

You will execute the Electro-Migration and IR Drop (EMIR) analysis and sign-off from block level to full-chip, working closely at the intersection of Physical Design, Analog/Mixed-Signal design, and Package Engineering. You will be responsible for validating power grid architectures to ensure our products meet aggressive voltage drop and reliability targets in advanced FinFET process nodes, directly impacting the performance and yield of chips operating in the world’s most demanding AI and cloud environments.

Key Responsibilities

• Execute static and dynamic IR drop analysis, signal/power electromigration (EM) verification, and self-heat analysis from the block level through to full-chip sign-off
• Implement and maintain robust EMIR flows and methodologies using industry-standard tools (Ansys RedHawk-SC, Cadence Voltus, or equivalent)
• Work with Physical Design teams to implement optimal power grid structures, via pillars, and strap distributions to minimize voltage drop while maximizing routing resources
• Collaborate closely with Analog/SerDes designers to analyze current profiles and ensure robust power delivery to sensitive high-speed IP blocks
• Partner with Package Design engineers to perform Chip-Package-System (CPS) co-analysis, optimizing bump patterns and package routing for superior Power Integrity
• Perform root-cause analysis for voltage drop violations and EM risks, proposing and implementing layout fixes alongside the PD team
• Verify current density rules for ESD protection networks and ensure compliance with strict foundry reliability constraints
• Support silicon bring-up by correlating simulation results with actual silicon measurements and yield data

Basic Qualifications

• Bachelor's or Master's degree in Electrical Engineering or a related technical field
• 5+ years of hands-on experience in EMIR/Power Integrity analysis for high-performance SoCs or high-speed connectivity products
• Strong proficiency in industry-standard EMIR tools (Ansys RedHawk/RedHawk-SC, Totem, or Cadence Voltus)
• Deep understanding of EM/IR challenges in advanced FinFET nodes (7nm, 5nm, 3nm), including fin-heating, thermal coupling, and layout-dependent effects
• Solid understanding of Place & Route flows, power grid synthesis, extraction (RC), and standard cell architecture
• Proven ability to debug complex voltage drop issues, identify "weak spots" in the grid, and drive convergence on large, complex designs
• Proficiency in Python, Tcl, or Perl for flow automation and data parsing

Preferred Experience

• Experience with AI, networking, PCIe, CXL, or large-scale SerDes integration
• Background in Analog/Mixed-Signal EMIR analysis (using Totem or specialized analog flows)
• Experience performing Chip-Package-System (CPS) thermal and power co-simulation
• Familiarity with thermal analysis tools and their interaction with electrical performance
• Experience working with sign-off criteria and margins for high-volume production chips

Role Overview

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Static Timing Analysis (STA) Engineer to join our local engineering powerhouse from the ground up.

This is a unique opportunity to take on meaningful technical ownership in a new site, executing the sign-off methodology for chips that power the world's most advanced AI clusters. As an STA Engineer, you will be deeply involved in the STA activities from chip partition and time budgeting through to final sign-off. You will bridge the gap between Architecture, Design, DFT, and Physical Design to ensure our high-performance silicon meets the aggressive timing targets required for next-generation connectivity.

Key Responsibilities

• Execute the STA flow and sign-off methodologies, ensuring our products meet rigorous timing criteria for the most demanding data center environments
• Collaborate closely with Architecture, Design, DFT, and Backend teams, participating in timing reviews and working with block owners to navigate the path to sign-off convergence
• Develop, optimize, and manage complex SDC constraints, ensuring they are accurate and robust across multi-scenario environments
• Analyze and resolve challenges related to cross-chip clock distribution networks and apply sophisticated margining techniques to ensure robust silicon across all process corners
• Participate in design methodology improvements and tool automation, utilizing both industry-standard EDA tools and custom scripts to make our sign-off process faster and more efficient

Basic Qualifications

• B.Sc. in Electrical Engineering or Computer Engineering
• 5+ years of hands-on experience in Static Timing Analysis (STA) at semiconductor companies, specifically working on advanced process technologies. (Note: Adjust years of experience based on the exact level you are targeting)
• Deep expertise in multi-scenario STA, as well as timing and SDC constraint development and verification at the block and subsystem levels
• Solid understanding of advanced margining methodologies, including OCV, AOCV, and POCV, from synthesis through to final sign-off
• Solid knowledge of physical design flows (Synthesis, P&R, Physical Verification) and how they intersect with timing closure

Preferred Experience

• Experience developing and validating constraints using industry-standard tools like Timing Constraints Manager (Synopsys) or TimeVision (Ausdia)
• Proven track record of executing STA on complex Macro-level designs and supporting Full-Chip timing integration
• Strong background in scripting (Tcl, Python, Perl) and automation to enhance timing closure efficiency

Role Overview

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Senior DFT Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, ensuring the reliability and testability of chips that power the world's largest AI clusters.

As a Senior DFT Engineer at Astera Labs, you will be at the intersection of architecture, design, and production. You won't just run tools—you will be a foundational member of the team responsible for the entire lifecycle of our silicon's reliability. From defining initial DFT architecture to supporting post-silicon bring-up, your work ensures that the backbone of AI infrastructure connectivity is flawless and scalable. If you thrive on solving complex challenges in deep-submicron processes and want to establish world-class DFT methodologies, this is your opportunity.

Key Responsibilities

• DFT Architecture & Strategy

  • Own the DFT journey from high-level architecture definition and RTL design to backend implementation and post-production support
  • Develop comprehensive Design-for-Testability (DFT) strategies for next-generation connectivity platforms, ensuring chips meet the highest quality standards
  • Define DFT architectures including JTAG/iJTAG, MBIST, Scan, and ATPG methodologies

• Test Pattern Development & Optimization

  • Generate and optimize high-quality test and debug patterns for production
  • Perform Static Timing Analysis (STA) for DFT modes and conduct gate-level simulations to ensure robust performance
  • Drive test coverage and quality metrics to meet stringent manufacturing requirements

• Cross-Functional Collaboration & Methodology Innovation

  • Act as a multidisciplinary bridge, collaborating closely with Architecture, Verification, and Backend teams to ensure seamless integration and optimal QoR
  • Participate in developing and maintaining cutting-edge DFT implementation flows
  • Automate and improve methodologies using advanced scripting and tools

Basic Qualifications

• Bachelor's degree in Electrical Engineering or related technical field
• 3+ years of hands-on experience in DFT roles at semiconductor companies
• Deep expertise in DFT flows and architectures including JTAG/iJTAG, MBIST, Scan, and ATPG
• Proficiency with industry-standard EDA tools from Synopsys (TestMAX) or Mentor (Tessent)
• Strong understanding of logic design, verification, debug, and Static Timing Analysis (STA)
• Scripting proficiency in Tcl, Perl, Python, or Shell for automation and innovation

Preferred Qualifications

• Master's degree in Electrical Engineering or related field
• Knowledge of high-speed interface protocols (PCIe, Ethernet, CXL, UALink) and their specific test requirements
• Experience in chip bring-up and mass production activities
• Background in advanced process technologies (7nm and below)
• Excellent communication skills with ability to work effectively in global team environments