We are looking for a Staff Digital Design Engineer to help define, build, and optimize high-performance IP and SoC architectures for next-gen AI and compute workloads. This role is ideal for engineers who thrive at the intersection of microarchitecture, RTL implementation, and performance-aware design.

This role is hybrid, based out of Toronto, Ottawa, Boston, or Austin. 

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A digital design expert with a deep understanding of computer architecture and IP microarchitecture.
• Skilled in RTL development (Verilog/VHDL) and familiar with full ASIC flows.
• Comfortable optimizing for power, performance, and area (PPA) under aggressive design goals.
• A naturally collaborative and technical engineer — you thrive in spec definition, peer reviews, and team-wide planning.

What We Need

• Architecture and RTL implementation of Tenstorrent’s custom IP blocks and SoC components.
• Performance-aware design decisions for compute, interconnect, or memory-heavy blocks.
• Occasional contributions to validation using emulation, FPGA prototyping, or UVM flows.
• Strong synthesis and timing closure awareness to support backend teams.
• Prior experience in on-chip fabric and interconnect designs is an asset.

What You Will Learn

• How cutting-edge AI chips are built, from spec to silicon.
• What it takes to collaborate with teams designing novel processor and memory architectures.
• How to blend custom logic with standard SoC elements for power and scale.
• How cross-functional workflows come together across design, DV, physical, and firmware teams.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Our Tensix Team is building the next generation of high-performance AI compute systems. We’re looking for a Power Architect to drive architectural strategy, modeling, and design decisions that shape how power is understood and optimized across our products. This is a hands-on role with massive influence over how we build power-aware systems from the ground up.

This role is hybrid, based out of Toronto, ON or Austin, TX.

We welcome candidates at various experience levels. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• 10+ years experience with power estimation tools like PowerArtist, PtPX, RTL Architect, and PrimePower.
• Skilled in modeling and optimizing power at the architectural level, with deep knowledge of power-gating, voltage domains, and leakage control.
• Track record of influencing architectural and micro-architectural changes that meaningfully reduced design power.
• Proficient in Verilog HDL, Design Compiler, C/C++ and Python.
• Background in power-optimization of compute datapath  and/or interconnects.

What We Need

• Predict power consumption early in architecture and track it through RTL evolution.
• Propose architectural changes for power optimization across server and non-server markets.
• Build workloads that stress real-world use cases and guide thermal and power-delivery solutions.
• Correlate pre-silicon estimates to silicon measurements and drive power efficiency improvements.

What You Will Learn

• How AI workloads impact power at every layer of the stack — from circuit to software.
• Challenges in building accurate, CI-integrated power modeling infrastructure.
• Techniques for aligning design tradeoffs to the realities of AI model execution.
• How Tenstorrent approaches full-stack power optimization across chiplet-based systems.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Job Description:

As an Analog/Mixed-Signal IC Design Engineer, you will be part of a key team designing sophisticated advanced node CMOS products. Your responsibilities will include developing and verifying circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, and CDRs to meet performance targets. You will also work on analog and clocking blocks for connectivity applications, using industry-standard tools like Spectre and MATLAB. The company seeks a highly motivated designer for this role

Basic Qualifications:

• Strong academic and technical background in electrical engineering. A Master’s or PhD degree in EE is required, preferably from a top-tier university.
• 2+ years of experience supporting or developing complex analog IC designs.

Required Experience:

• Hands-on experience in designing high-speed mixed-signal circuits including ADC/DAC data converters, RX front-end, TX driver/serializer, low-jitter PLLs, TX/RX calibration, low-jitter CLK distribution are other high-speed analog circuits is a must
• Have a deep understanding of biasing, band-gaps, reference circuits, opamps, comparators and other analog circuits
• Solid track-record for implementation of analog circuits high-speed data transmission.
• Design and tapeout experience in advanced CMOS nodes (ex. 20nm or newer) is a must
• Solid fundamentals in detailed transistor-level design, feedback/stability analysis, and noise/jitter analysis.
• Knowledge of TIA design and drivers for optical applications is highly desirable
• Experience in RFIC design for wireless or wireline communication systems is highly desirable.
• Strong technical independent contributor with a proven ability to drive results.
• Excellent teamwork, presentation, and documentation skills.
• Ability to collaborate with global teams across multiple time zones and deliver under pressure with strict deadlines.
• Strong experience in lab chip bring-up and debugging efforts.

Preferred Experience:

• Relevant research publications and/or patents in analog or RF IC design.
• Familiarity in programming/scripting languages such as Python, Matlab, or C.
• Experience with PCB design.
• Familiarity with Verilog RTL or DSP design concepts.
• Knowledge of optical transceivers.
• Expertise in ESD protection techniques and IC packaging methodologies.

The base salary range is $150,000.00 USD – $200,000.00 USD.

The base salary range for this role in Canada is $110,000 CAD - $130,000 CAD

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.  

Job Description:

As an Analog/Mixed-Signal IC Design Engineer, you will be part of a key team designing sophisticated advanced node CMOS products. Your responsibilities will include developing and verifying circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, and CDRs to meet performance targets. You will also work on analog and clocking blocks for connectivity applications, using industry-standard tools like Spectre and MATLAB. The company seeks a highly motivated designer for this role

Basic Qualifications:

• Strong academic and technical background in electrical engineering. A Master’s or PhD degree in EE is required, preferably from a top-tier university.
• 8+ years of experience supporting or developing complex analog IC designs.

Required Experience:

• Hands-on experience in designing high-speed mixed-signal circuits including ADC/DAC data converters, RX front-end, TX driver/serializer, low-jitter PLLs, TX/RX calibration, low-jitter CLK distribution are other high-speed analog circuits is a must
• Have a deep understanding of biasing, band-gaps, reference circuits, opamps, comparators and other analog circuits
• Solid track-record for implementation of analog circuits high-speed data transmission.
• Design and tape out experience in advanced CMOS nodes (ex. 7nm, 5nm 3nmFinFET) is a must.
• Solid fundamentals in detailed transistor-level design, feedback/stability analysis, and noise/jitter analysis.
• Knowledge of TIA design and drivers for optical applications is highly desirable
• Experience in RFIC design for wireless or wireline communication systems is highly desirable.
• Strong technical independent contributor with a proven ability to drive results.
• Excellent teamwork, presentation, and documentation skills.
• Ability to collaborate with global teams across multiple time zones and deliver under pressure with strict deadlines.
• Strong experience in lab chip bring-up and debugging efforts.

Preferred Experience:

• Relevant research publications and/or patents in analog or RF IC design.
• Familiarity in programming/scripting languages such as Python, Matlab, or C.
• Experience with PCB design.
• Familiarity with Verilog RTL or DSP design concepts.
• Knowledge of optical transceivers.
• Expertise in ESD protection techniques and IC packaging methodologies.

 Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.

Job Description

We are seeking a Technical Lead Digital Design Engineer with deep expertise in high-performance PCIE controller and bridge design, micro-architecture, RTL implementation, and IP integration. The ideal candidate will play a critical role in the development of cutting-edge connectivity solutions.

Key Responsibilities:

• Design and implement high-performance digital solutions, including RTL development and synthesis.
• Collaborate with cross-functional teams on IP integration for Serdes and Controller IPS, processor and peripherals
• Own block-level and full-chip designs from architecture to GDS, focusing on designs at nodes ≤ 16nm.
• Ensure timing closure, assess verification completeness, CDC, lint etc.
• Utilize tools from Synopsys/Cadence for design and emulation.

Basic Qualifications:

• Bachelor’s in Electronics/Electrical engineering (Master's preferred).
• 5+ years of digital design experience, with 4+ years focused on PCIE controller, PCS or PHY implementation.
• Proven expertise in RTL development, synthesis, and timing closure.
• Experience with front-end design, gate-level simulations, and design verification.
• Strong work ethic, ability to handle multiple tasks, and a proactive, customer-focused attitude.

Required Expertise:

• Hands-on experience with PCIE Controller or Serdes/PHY IP.
• Hands-on pre-silicon and post-silicon design implementation.
• Hands-on experience  FW interaction and embedded design.
• Strong proficiency in System Verilog/Verilog and scripting (Python/Perl).
• Experience with block-level and full-chip design at advanced nodes (≤ 16nm).
• Top level integration and DFT knowledge.

Preferred Experience:

• PCIE SerDes controller or IP level experience.
• Understanding of PAD design, DFT, and floor planning.
• Experience with NIC, switch, or storage product development including embedded FW.
• Familiarity with working in design and verification workflows in a CI/CD environment.

The Role:
In this exciting role, you will be responsible for bring up and optimizations of Cerebras’s Wafer Scale Engine (WSE). Suitable candidate will have experience delivering end to end solutions working closely with teams across chip design, system performance, software development and productization.

Responsibilities:

• On Wafer Scale Engines, develop and debug flows that embed well tested and deployable optimizations in production processes to reduce time and costs 
• Work on refining AI Systems across H/W-S/W design constraints such as di/dt, V-F characterization space, current and temperature limits in relation to optimizations for performance.
• Develop/Enhance infrastructure to enable silicon for real world workload testing
• Develop self-checking metrics, as well as instrumentation for debug and coverage
• Work with the silicon architects/designers, performance engineers and software engineers to enhance performance of Wafer Scale Engines.
• Work across domains such as, Software, Design, Verification, Emulation & Validation to refine and optimize performance and process.
• Work with CI/CD tools, git repositories, github, git actions/Jenkins, merge and release flows to streamline test and release.

Skills & Qualifications:

• BS/BE/B.Tech or MS/M.Tech in EE, ECE, CS or equivalent work experience
• 7-10+ years of industry experience
• 3-5 years of experience in Pre-silicon & Post Silicon ASIC hardware
• Good understanding of computer architecture and networking
• Excellent Coding in languages such as Python/Verilog/System Verilog and C
• Proficient in hardware/software codesign and layered architectures.
• Excellent debugging, analytical, and problem-solving skills
• Proficient in large scale testing and automation using pytest and python
• Good presentation skills to refine diverse information and put forth optimization strategies and results.
• Good interpersonal skills, ability & desire to work as a standout colleague
• Proven track record of working cross-functionally learning fast and driving issues to closure 

Preferred:

• Previous work in AI-ML with 100+ CPU core & communication fabric-based design.
• Familiarity with in-line testing and diagnostics using CPU memory and execution with self-checking.
• Knowledge of chip defect profiles and mitigation strategies across the hardware and software stack
• Familiarity in creating test and s/w infrastructure at large scale
• Working across global time zones 

Location:
Bangalore, India

Toronto, Canada

Sunnyvale, California.

For Sunnyvale: The base salary range for this position is $175,000 to $275,000 annually.  Actual compensation may include bonus and equity, and will be determined based on factors such as experience, skills, and qualifications.

The Role:
In this exciting role, you will be responsible for bring up and optimizations of Cerebras’s Wafer Scale Engine (WSE). Suitable candidate will have experience delivering end to end solutions working closely with teams across chip design, system performance, software development and productization.

Responsibilities:

• On Wafer Scale Engines, develop and debug flows that embed well tested and deployable optimizations in production processes to reduce time and costs 
• Work on refining AI Systems across H/W-S/W design constraints such as di/dt, V-F characterization space, current and temperature limits in relation to optimizations for performance.
• Develop/Enhance infrastructure to enable silicon for real world workload testing
• Develop self-checking metrics, as well as instrumentation for debug and coverage
• Work with the silicon architects/designers, performance engineers and software engineers to enhance performance of Wafer Scale Engines.
• Work across domains such as, Software, Design, Verification, Emulation & Validation to refine and optimize performance and process.
• Work with CI/CD tools, git repositories, github, git actions/Jenkins, merge and release flows to streamline test and release.

Skills & Qualifications:

• BS/BE/B.Tech or MS/M.Tech in EE, ECE, CS or equivalent work experience
• 7-10+ years of industry experience
• 3-5 years of experience in Pre-silicon & Post Silicon ASIC hardware
• Good understanding of computer architecture and networking
• Excellent Coding in languages such as Python/Verilog/System Verilog and C
• Proficient in hardware/software codesign and layered architectures.
• Excellent debugging, analytical, and problem-solving skills
• Proficient in large scale testing and automation using pytest and python
• Good presentation skills to refine diverse information and put forth optimization strategies and results.
• Good interpersonal skills, ability & desire to work as a standout colleague
• Proven track record of working cross-functionally learning fast and driving issues to closure 

Preferred:

• Previous work in AI-ML with 100+ CPU core & communication fabric-based design.
• Familiarity with in-line testing and diagnostics using CPU memory and execution with self-checking.
• Knowledge of chip defect profiles and mitigation strategies across the hardware and software stack
• Familiarity in creating test and s/w infrastructure at large scale
• Working across global time zones 

Location:

Sunnyvale, California.

Bangalore, India

Toronto, Canada 

The base salary range for this position is $175,000 to $275,000 annually.  Actual compensation may include bonus and equity, and will be determined based on factors such as experience, skills, and qualifications.

Ethernovia Canada was established in Feb. 2020 with Senior Digital, Analog, and Software Engineers. Start remote with a hybrid remote/in-person flexibility in the future. Ideally you would be close enough to attend in-person meetings and work at least part time on site when the planned office in the greater Toronto/Markham area is opened. Fully remote applicants will also be considered. We have multiple international locations enabling us to pull in leading talent in various required disciplines so virtual communication is commonplace. 

Senior ASIC Design Verification Engineer

Summary:  

• As a Senior ASIC Design Verification Engineer, you will be responsible for all aspects of digital SoC verification.
• You will work the architects, designers, and SW engineers to plan and execute verification and validation of advanced automotive communication semiconductors and systems.
• You will contribute to a positive, trusting, and cohesive working environment based on integrity and strong work ethics.
• This position is located in: Canada - Remote

Key Qualifications:

• BS and/or MS in Electrical Engineering, Computer Science, or related field
• Minimum 10+ years of ASIC verification experience
• Strong understanding of ASIC verification fundamentals and industry standard methodologies
• Experience with Verilog/System Verilog, UVM, Python, TCL, C/C++
• Experience with the full verification flow, from spec to coverage analysis to gate level sim
• Debugging failures in simulation to root cause problems
• Self-motivated and able to work effectively both independently and in a team

Additional Success Factors:
Experience in any of the following areas:

• Networking (Ethernet MAC, PHY, Switching, TCP/IP, security, PCIe and other industry standard protocols)
• Video standards, protocols, processing
• Digital signal processing filters
• Third party IP (SerDes, controllers, processors, etc.)
• Modular and Reusable Testbench architecture
• Design for re-use of pre and post silicon tests and infrastructure
• Automation of testbench creation, tests, regression, or EDA tools
• Knowledge of SystemC and/or DPI

Personal Skills:

• Excellent communication/documentation skills.
• Attention to details.
• Collaboration across multidisciplinary and international teams.

What You Can Expect from Ethernovia:

• Technology depth and breadth expansion that can’t be found in a large company
• Opportunity to grow your career as the company grows
• Pre IPO stock options
• Cutting edge technology
• World class team
• Competitive base salary
• Flexible hours
• Medical, dental and vision insurance for employees

#LI-Remote