About the Company:

At SK Hynix Memory Solution, we're at the forefront of semiconductor innovation, developing advanced memory solutions that power everything from smartphones to data centers. As a global leader in DRAM and NAND flash technologies, we drive the evolution of advancing mobile technology, empowering cloud computing, and pioneering future technologies. Our cutting-edge memory technologies are essential in today's most advanced electronic devices and IT infrastructure, enabling enhanced performance and user experiences across the digital landscape.

We're looking for innovative minds to join our mission of shaping the future of technology. At SK Hynix Memory, you'll be part of a team that's pioneering breakthrough memory solutions while maintaining a strong commitment to sustainability. We're not just adapting to technological change – we're driving it, with significant investments in artificial intelligence, machine learning, and eco-friendly solutions and operational practices. As we continue to expand our market presence and push the boundaries of what's possible in semiconductor technology, we invite you to be part of our journey to creating the next generation of memory solutions that will define the future of computing.

About The Role

You will join the System on Chip (SoC) Design Team at SK hynix memory solutions America, a group dedicated to delivering best-in-class controllers for high-performance SSDs. This team spans the full design cycle—from micro-architecture and RTL design to timing closure and tapeout readiness—enabling next-generation enterprise and AI data center storage solutions.

Responsibilities

• RTL design (Verilog/SystemVerilog) for IP based on existing module or new specifications.
• Collaborate, create clear documentation and communication with Design Verification, Silicon Validation, and Firmware teams to ensure design quality.

Minimum Qualifications

• Education: Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field.
• Experience: 6+ years of hands-on experience in ASIC/SoC design.
• Proficiency in logic design and micro-architecture; RTL coding in Verilog and/or SystemVerilog language.
• Experience with Lint, CDC, synthesis, power analysis and DV coverage tool.

Preferred Qualifications

• Advanced Education: Master’s or PhD in Electrical Engineering with working experiences.
• Domain Knowledge: NAND Flash, memory controller, datapath design, NVMe, PCIe, UCIe, DDR, CPU subsystem, Network Interconnect, AMBA, error correction code.
• Proficiency in AI tool to generate synthesizable and functional RTL code.
• Knowledge of design verification approaches to enhance verification coverage.

REGARDING COMPENSATION:

SK hynix memory solutions America Inc. offers you the opportunity to apply your skills to exciting projects while working with innovative teams. Our compensation package is complimented by a generous benefits package including medical, dental, vision, life insurance and a company 401(k) match, as well as cafeteria, onsite gym and much more. If you are motivated by technical challenges, we offer a collaborative work environment that encourages career growth.

The salary offered to a selected candidate will be tailored based on several factors, including the location, job grade, relevant knowledge, skills, and experience. We also take into account the internal equity among our current team members to ensure fairness and competitiveness.

Role Overview

Astera Labs is seeking a Physical Design Engineering Manager to lead a team of physical design engineers at our Toronto site, driving the implementation of connectivity ASICs within our Signal Connectivity Group. This group is responsible for products that enable high-speed serial connectivity including PCIe retimers, Ethernet retimers, and signal conditioning solutions—deployed across the world's largest AI clusters and hyperscale data centers.

As an Physical Design Manager Engineering Manager, you will combine hands-on technical leadership with people management, owning physical design execution from RTL to GDSII while building and mentoring a high-performing team. You will drive floorplanning, place-and-route, timing closure, and sign-off for complex designs requiring deep understanding of high-speed physical layer interfaces and SerDes integration at TSMC advanced nodes. This role is fully on-site at our Toronto location.

Basic Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field; Master's preferred.
• 12+ years of experience in physical design implementation of complex SoCs at advanced nodes (7nm and below).
• 2+ years of experience leading teams or projects with demonstrated ability to mentor and develop engineers.
• Hands-on expertise across the physical design flow: synthesis, place-and-route, CTS, extraction, timing closure, EM-IR, DRC/LVS, and equivalence checking.
• Proficiency with Cadence Innovus and/or Synopsys Fusion Compiler/ICC2 and supporting toolchains.
• Strong scripting ability in Tcl, Python, and/or Perl.
• Professional attitude with the ability to prioritize a dynamic list of tasks, plan and prepare for customer meetings in advance, and work with minimal guidance.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind! 

Required Experience

• Build, lead, and mentor a physical design team, owning Physical Design execution and team development for Signal Connectivity Group products.
• Drive block and top-level physical design implementation from floorplan through tapeout for retimer and signal conditioning ASICs.
• Own floorplanning, macro placement, power grid design, clock tree synthesis, and place-and-route for complex blocks and full-chip designs.
• Drive timing closure at both block and full-chip levels, developing and maintaining timing constraints and signoff methodology.
• Ensure DRC/LVS/EM-IR closure and physical verification sign-off to foundry requirements.
• Integrate hard macros, high-speed SerDes, analog IP, and third-party IP blocks, ensuring seamless physical integration at block boundaries.
• Collaborate with RTL, DFT, STA, EMIR, and verification teams to drive design convergence from synthesis through sign-off.
• Work with IP vendors for both RTL and hard-macro integration, ensuring placement constraints and routing guidelines are met.
• Drive team execution, hiring, career development, and sprint planning for the Toronto PD team.
• Establish physical design best practices, flow improvements, and quality checks to scale execution across multiple concurrent programs.
• Coordinate with global PD teams (San Jose, Irvine, Bangalore) to ensure consistent methodology and design quality.
• Experience with Cadence and/or Synopsys physical design tools/flows.
• Familiarity and working knowledge of SystemVerilog/Verilog.

Preferred Experience

• Deep understanding of high-speed SerDes physical layer, including equalization, CDR, and signal integrity considerations impacting physical design.
• Experience with PCIe, Ethernet, or retimer/signal conditioning ASIC implementation.
• Knowledge of physical layer timing challenges specific to high-speed serial interfaces.
• Hands-on experience with UPF-based multi-voltage/multi-power-domain implementations.
• Familiarity with advanced packaging or multi-die integration and its impact on physical design.
• Experience with ECO methodologies and DFT-aware physical design.
• Knowledge of EMIR-aware implementation techniques and early-stage IR drop mitigation.
• Track record of building and scaling physical design teams through multiple tapeouts.
• Knowledge of agentic AI solutions for EDA automation.

Salary range is CAD $180,000 to $220,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives, and benefits.

About Akuna: 

Akuna Capital is an innovative trading firm with a strong focus on collaboration, cutting-edge technology, data driven solutions, and automation. We specialize in providing liquidity as an options market-maker – meaning we are committed to providing competitive quotes that we are willing to both buy and sell. To do this successfully, we design and implement our own low latency technologies, trading strategies, and mathematical models. 

Our Founding Partners first conceptualized Akuna in their hometown of Sydney. They opened the firm’s first office in 2011 in the heart of the derivatives industry and the options capital of the world – Chicago. Today, Akuna is proud to operate from additional offices in Sydney, Shanghai, London, and Singapore. 

What you’ll do as a Senior FPGA Engineer at Akuna: 

We are looking for Senior FPGA Engineers to accelerate various portions of our trading platform. Members of the Hardware Development team will work with cutting-edge FPGA technology and high-performance computing architectures – owning projects end-to-end and making Akuna’s systems faster and smarter. In this role, you will: 

• Own projects - driving project progression from inception, requirements, architecture, design entry, timing closure and verification
• Partner closely with the Low Latency, Trading and other teams to foster and develop ideas that performance 
• Develop and maintain RTL in Verilog/SystemVerilog
• Write and maintain verification environments
• Design optimization for timing closure
• Develop and maintain project documentation 

Qualities that make great candidates: 

• 10+ years of experience in FPGA or ASIC digital logic design – network traffic experience a strong plus
• Deep Verilog/SystemVerilog or VHDL skills
• Solid grasp of static timing analysis, synthesis, and place-and-route tools  
• Familiarity with algorithms, data structures, and verification/unit testing workflows
• Python and Bash scripting fluency
• Enthusiasm for collaboration with other FPGA team members as well as members from software and trading teams
• Open mindedness for novel development approaches and architectures
• Bachelor’s degree in Computer or Electrical Engineering, or related field; master’s degree a plus 
• The ability to react quickly and accurately to rapidly changing market conditions, including the ability to quickly and accurately respond and/or solve math and coding problems are essential functions of the role

In addition to technical skillsets, Akuna values the unique perspectives people can bring to the table to collaboratively solve complex problems and drive Akuna forward. We want everyone to feel empowered to apply. We welcome your application and encourage you to take the first steps toward your future with us!

In accordance with Illinois Equal Pay Act, the minimum base salary starts at $145,000. Exact compensation offered may vary based on many factors including, but not limited to, the candidate’s experience, qualifications, and skill set. This role is also eligible for a discretionary performance bonus as part of the total compensation package and includes a comprehensive benefits package that may encompass employer-paid medical, dental, vision, retirement contributions, paid time off, and other benefits. The minimum base salary herein was determined in good faith by Akuna Capital LLC.

As an Astera Labs Physical Design Engineer (Place & Route) to play a crucial role in the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. This is a generalist physical design role requiring broad expertise across floorplanning, place-and-route, timing closure, and physical sign-off. You will work closely with designers, verification engineering, and engineering operations to drive blocks from RTL to GDSII. This role is fully on-site and in-person.

Basic Qualifications:

• Strong academic and technical background in electrical engineering. A Bachelor's degree in EE / Computer Engineering is required, and a Master's degree is preferred.
• 3+ years of experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind!

Required Experience:

• Hands-on and thorough knowledge of synthesis, place and route, timing, extraction, EM-IR, formal verification (equivalence) and other backend tools and methodologies for technologies 7nm or less.
• Block level ownership from architecture to GDSII, driving multiple complex designs to production.
• Experience with Cadence and/or Synopsys physical design tools/flows.
• Familiarity and working knowledge of SystemVerilog/Verilog.
• Proven expertise in developing/maintaining timing constraints, timing signoff methodology, timing closure at the block or full-chip level.
• Experience in working with IP vendors for both RTL and hard-macro blocks.
• Good scripting skills in Tcl, Python, or Perl.

Nice to Have Experience Includes:

• Knowledge of design for test (DFT).
• Familiarity with ECO methodologies and tools.
• Knowledge of LVS/DRC closures.
• Experience with high-speed SERDES or Ethernet PHY design integration.
• Experience with clock tree synthesis optimization.
• Familiarity with PCIe, CXL, or Ethernet connectivity protocols.

Voyager is an innovative defense, national security, and space technology company committed to advancing and delivering transformative, mission-critical solutions. We tackle the most complex challenges to unlock new frontiers for human progress, fortify national security, and protect critical assets, leading in the race for technological and operational superiority from the ground to space. 

Forge the Future: Join Voyager Technologies 

The future belongs to those who build it. At Voyager Technologies, we’re building technologies that protect lives, expand frontiers, and prepare us for what’s next. And we’re doing that with people who are wired to solve, build, adapt, and lead. These roles are not for the faint of heart.  

You’ll help lay the foundation for humanity's future. Join a culture where innovation thrives, curiosity is rewarded, and impact is real. We’re a company of doers, thinkers, and builders, united by purpose and grounded in reality. 

If you want to put your skills to work where the stakes are real and the mission is bigger than any one person, forge the future with Voyager. 

Voyager’s Advanced Technologies Group is defining the future of the company and critical space and defense markets. The FPGA Engineer is a hands-on role responsible for the design, integration, and qualification of complex systems supporting these novel technology development efforts. The role emphasizes high-velocity design and technical leadership for in-space computing systems. The engineer provides technical direction and works closely with other engineering functions to ensure system architectures meet performance, safety, and mission assurance standards.

The position reports to the Vice President of Technology Development and is part of the Engineering department based in Long Beach, CA. This role can be hybrid.

In this role, the essential functions are:

• Designing and testing complex, high speed, FPGA (mostly Xilinx) designs implementing high-throughput algorithms.
• Designing and testing embedded applications using the Xilinx Zynq family.
• Developing architectures compatible with embedded Linux environments.
• Designing and supporting top-level system simulations.
• Translating system requirements into FPGA architectures.
• Implementing and documenting FPGA designs using HDL (VHDL, System Verilog, etc.).
• Supporting systems integration and Test Engineering to produce functional designs.
• Implementing and contributing to the architecture of current and next generation multi-megapixel camera systems, interfacing with the Camera Link and SpaceWire standards.
• Designing systems capable of handling Imager data and Image processing (Embedded Camera Development).
• Creating test plans to assure integrated performance meets specification.

If your experience aligns with our basic qualifications and you are inspired by our mission, we’d like to connect. If you don’t see the right role right now, Join Our Talent Community and stay connected as we continue to build what’s next. 

• Minimum BSEE.
• 5+ years of experience with firmware design, integration, & test (preferably with the Xilinx family)
• Capable of multi-tasking; working on multiple projects & supporting production activities
• Strong technical background; capable of coming up-to-speed quickly on new technologies.
• Good communication, with the ability to work both individually and collaboratively in a team environment.
• Strong documentation skills
• Great problem-solving skills a must.

The good faith base salary range for this role is $135,000-$185,000 at the time of this posting. Where you fall within the range depends on your experience, skills, and location. This range reflects base salary only and does not include benefits or bonus/incentive. This range may be adjusted in the future.

Voyager offers a highly competitive total compensation package designed to support the well-being, growth, and success of our employees. Employees benefit from a flexible and comprehensive rewards program that supports both professional and personal well-being.  

• Flexible Time Off (FTO), empowering employees to take the time they need to recharge and maintain a healthy work-life balance
• Comprehensive medical, dental, and vision coverage for employees and their families, with a significant portion of premiums covered by the company, and many benefits paid at 100% for employees
• Flexible, affordable gym memberships with 12,700+ options nationwide, including 24 Hour Fitness, EoS Fitness, Crunch Fitness, Anytime Fitness, Blink Fitness, Chuze Fitness, and more! No long-term contracts and FREE on-demand workout videos before you enroll
• 401(k) retirement plan with a company match of up to 4% to help you build long-term financial security
• Company wellness programs that support physical and mental well-being
• Additional voluntary benefits and employee support resources
• The opportunity to work alongside a highly talented team in an innovative, mission-driven environment

Voyager is an Equal Opportunity Employer. Employment decisions are made without regard to race, color, religion, national or ethnic origin, sex, sexual orientation, gender identity or expression, age, disability, protected veteran status, or other characteristics protected by law.  

Minority/Female/Disabled/Veteran 

To conform to U.S. Government export regulations, including the International Traffic in Arms Regulations (ITAR) (22 CFR Parts 120-130) and the Export Administration Regulations (EAR) (15 CFR Parts 730-774), applicants for this position must be a U.S. Person: a US Citizen, a lawful permanent resident of the U.S., or a protected individual as defined by 8 U.S.C. § 1324b(a)(3). Applicants must be eligible to obtain any required export authorizations from the U.S. Department of State or the U.S. Department of Commerce.

The statements contained in this job description are intended to describe the general content and requirements for performance of this job. It is not intended to be an exhaustive list of all job duties, responsibilities, and requirements. This job description is not an employment agreement or contract. Management has the exclusive right to alter the scope of work within the framework of this job description at any time without prior notice. 

What MatX Is Building

MatX builds custom AI accelerator silicon. The build system is the backbone: it wires together RTL, a stack of commercial EDA tools (simulation, synthesis, place-and-route, lint/CDC), and a Rust/Python software stack into one hermetic, reproducible pipeline. We run on Bazel with bzlmod, RBE, custom rules, and a small but tight set of platform-level abstractions.

You'll join a small group that owns the build graph, the toolchains, the rules that wrap each EDA tool, and the CI infrastructure that keeps thousands of targets green.

What You’ll Do Here

• New EDA tool integrations. Wrap a closed-source tool in a hermetic Bazel rule with proper providers, runfiles, and execution constraints. Add a new front-end stage to an existing toolchain; add a rule for test variants that share configuration; wire a third-party generator into our verilog graph as a first-class dep
• Bazel version migrations. Lead upgrades (8.x → 9.x) and the bzlmod/MODULE.bazel housekeeping that comes with them
• Hermeticity work. Hunt down the implicit assumptions: system Python, system gcc, leaked /usr/bin deps, host-state in tests. Replace them with hermetic toolchains and tracked inputs
• Refactors that delete code. Rewrite a fragmented family of test macros in terms of one shared rule. Remove a homegrown wrapper rule once upstream covers the case. Extract a common aspect helper used by three places that duplicated it. The good PRs net negative
• Build performance. Persistent workers for slow tools, RBE configs, action graph hygiene, cache-key debugging when something silently rebuilds
• CI infrastructure. GitHub Actions self-hosted runners on GCE COS, Buildbarn workers, monitoring, rolling upgrades
• PRs are small and frequent. Median is +50/-30. Big refactors arrive as a series of mechanical commits, each individually reviewable
• Reviews are real. We comment, ask questions, request changes. Reviews are how we share the build system across the team — not rubber-stamping
• Negative diffs are celebrated. "Remove unused X" and "Replace ad-hoc Y with Z" are first-class contributions
• You'll teach the rest of the team Bazel. Half the company writes RTL or Rust, not Starlark. Good rules let them stay in their domain. Good docstrings (and stardoc) keep them self-serve
• You'll work tightly with at least one of us. Most non-trivial changes are pair-designed before code. Fast feedback loops, whiteboard sessions, no async-only collaboration
• Lean on AI, but stay persnickety. We use Claude Code and similar tools heavily — for prototypes, refactors, scripts, even rule scaffolding. We also reject most of what they produce on the first pass. You'll steer the model hard toward your taste, push back on the easy answer, and review every line you commit as if you wrote it. Auto-generated PRs that pass tests but miss the point are not what we want

Who You Are

• Deep build-system fluency. Rules, providers (or equivalent), aspects, toolchains, platforms, configuration/select, transitions, query. You can read a build-system file — .bzl, Buck2 BUCK, Shake Rules.hs, whatever — and predict what its action graph will look like. Bazel-native is a plus; we'll trade six weeks of Starlark ramp for the right taste.
  We hire on build-system fluency, not Bazel-keyword-matching. If you've done equivalent work in Buck2, Shake/Hadrian, Pants, Nix, or a homegrown Blaze-shaped system, read the bullets as concepts — Bazel is what you'll write here, but the principles port. Be honest about ramp on Starlark and bzlmod.
• bzlmod / MODULE.bazel. Module extensions, lockfile management, vendoring third-party deps cleanly
• Remote execution. RBE, Buck2 RE, BuildBuddy, BuildBarn, your own — they all teach the same lessons. Cache-key debugging, Build without the Bytes, diagnosing "works locally, fails remote." If you've owned one end-to-end, the next one is a port
• Comfort in Rust / Python / shell / Starlark. You might read all four in any given week

Bonus Points If You Have

• Build graph is the source of truth. "If two things must stay in sync, make one depend on the other." Allergic to parallel lists in workflow YAML, Python arrays, and .bzl dicts that drift
• Don't parse what you can generate. If a tool has the structured data internally, have it write structured output. Parsing human-readable reports is a temporary bridge, not a design
• Split build from check. A rule that produces artifacts always succeeds; a separate _test target gates on quality. Empty dashboards because the build broke are unacceptable
• Let Bazel parallelize, not the orchestrator. One bazel build --keep_going over N matrix jobs that each warm up Bazel
• Encode execution constraints in the rule, not the invocation. No README accumulating per-tool --strategy=..., --remote_download_outputs=..., --sandbox_debug incantations. execution_requirements belongs on the action
• Compose at the boundary. Dev and prod differ only in where data comes from — share the components, swap the source. No parallel dev-only servers
• Smart targets over comprehensions. A direct rule call per file beats a list-comprehension factory plus three parallel side dicts
• Sort keys for determinism. The bytes of an emitted file are a function of semantic content, not iteration order
• Internal vs external API. Collapsing N files to 1 is a free improvement when you own both ends. It's a breaking change when someone else's scripts source those files by name
• Migrated a non-trivial codebase between major build-system versions or paradigms — WORKSPACE → bzlmod, Buck1 → Buck2, Make → Shake, or similar. Bonus if you led the bzlmod / MODULE.bazel housekeeping
• Written rules that wrap closed-source tools (EDA, ML, codegen) and made them hermetic and remote-executable — in Bazel, Buck2, Shake, or otherwise. The craft is the hermetic wrapper, not the syntax
• Owned a remote-execution deployment end-to-end — Bazel RBE, Buck2 RE, BuildBarn, BuildBuddy, in-house — including diagnosing cache poisoning, toolchain drift, or remote-vs-local divergence

Compensation

The US base salary for this full-time position is determined based on a variety of factors including role, experience, location, job related skills, and relevant education and training. Career length is only a guideline for compensation.

• Early Career - $120,000 - $250,000 + equity
• Mid Career - $175,000 - $362,500 + equity
• Senior Career - $250,000 - $475,000 + equity

What We Offer

• A Stake in our success A cash/equity mix that fits your needs, and option to do early exercise
• Health & Wellness Company subsidized Health, Dental, Vision, and Life insurance; Pre-tax Health Savings Accounts with generous company contribution (even if you don’t)
• Time To Recharge 4 weeks paid time off (accrued), 12 company holidays, and 3 weeks remote/flexible work per year
• Support to Parents Up to 12 weeks of paid parental leave, regardless of your path to parenthood
• Learning & Development $1,500 yearly towards your professional development e.g. conferences, courses, and other learning opportunities
• Team Connection Team Lunches, quarterly off-sites, and regular town halls
• Financial Wellbeing 401K and/or Roth IRA, with 5% company contribution, even if you don’t!
• Flexible Spending Accounts Pre-tax spend accounts for medical, dental/vision, dependent care, parking, and transit expenses
• Commute On Us For those commuting up to 1 hour, put your rideshare cost on our company card and reclaim the drive-time to get work done!
• MatX E[x]tras $50 per month to use on the perks you care about most 
• Remote Perks We work remotely Monday & Friday, supported by home-tech setup, and remote wifi expense reimbursement

As part of our dedication to the diversity of our team and our focus on creating an inviting and inclusive work experience, MatX is committed to a policy of Equal Employment Opportunity and will not discriminate against an applicant or employee on the basis of race, color, religion, creed, national origin or ancestry, sex, gender, gender identity, gender expression, sexual orientation, age, physical or mental disability, medical condition, marital/domestic partner status, military and veteran status, genetic information or any other legally recognized protected basis under federal, state or local laws, regulations or ordinances.

All candidates must be authorized to work in the United States and work from our offices in Mountain View Tuesdays-Thursdays.

This position requires access to information that is subject to U.S. export controls. This offer of employment is contingent upon the applicants capacity to perform job functions in compliance with U.S. export control laws without obtaining a license from U.S. export control authorities.

MatX does not accept unsolicited resumes from individual recruiters or third-party recruiting agencies in response to job postings. No fee will be paid to third parties who submit unsolicited candidates directly to our hiring managers or People team and any resumes submitted are deemed to be the property of MatX.

ABOUT THE TEAM 

Anduril AIRS provides high-performance cooled infrared imaging solutions, encompassing IDCAs, modules, and cameras. We achieve this through state-of-the-art technologies, advanced designs, and vertically integrated manufacturing processes. Our core strength lies in delivering customized, mission-critical imaging capabilities to system integrators and instrumentation manufacturers facing unique, challenging, and complex thermal imaging needs.

ABOUT THE JOB

The AIRS team is seeking a Senior Firmware Engineer to design a new product lines. In this role, you will work closely with an interdisciplinary technical team to define, complete the design and analysis, build prototypes leading to ground and flight testing, and mature the prototypes into products.

WHAT YOU’LL DO

• Lead FPGA architecture, standards, development and review processes
• FPGA Development: Designing, architecting, simulating, and integrating VHDL designs into FPGAs or Systems on Chip (SoC) for optimized performance, resource utilization, and power efficiency.
• Hardware/Software Integration: Collaborating with multidisciplinary teams (electrical engineers, software engineers, systems engineers) to ensure seamless integration of the firmware with the overall system, including processor bring-up and board support packages.
• Testing and Validation: Developing robust test benches in VHDL/Verilog and utilizing lab tools such as oscilloscopes and logic analyzers for rigorous testing and validation of designs against functional specifications and performance requirements.
• Optimization: Optimizing the algorithms for hardware acceleration, including MIPS optimization and efficient use of on-chip bus protocols like AXI or AXI-Stream. 

REQUIRED QUALIFICATIONS

• Education: A Bachelor's in Electrical Engineering, Computer Engineering, or a related technical field is typically required.
• Experience: 10+ years of experience developing HDL firmware for FPGA devices 
• Hardware Description Languages: Expertise in VHDL and/or Verilog/SystemVerilog is essential for RTL (Register Transfer Level) design.
• FPGA Tools: Experience with industry-standard FPGA design tools such as Xilinx Vivado or Intel Quartus.
• Debugging Skills: Strong hardware/software debugging skills using standard lab equipment.
• Version Control: Proficiency with version control systems (e.g., Git) for collaborative development.
• Eligible to obtain and maintain an active U.S. Secret security clearance

PREFERRED QUALIFICATIONS 

• Demonstrated experience designing with multi-gigabit SERDES, DDR memory busses, Ethernet MAC and PHY interfaces, FPGAs, and common communication busses like SPI and I2C
• Embedded software development experience with the use of timers, interrupts, hardware peripherals such as SPI controllers and ADCs
• Knowledge of embedded Linux development, including device trees, hardware drivers, bootloaders, and basic Unix/Linux tools
• Familiar with common programming languages like Python and MATLAB
• Familiarity with infrared image sensor technology

Qube Research & Technologies (QRT) is a global quantitative and systematic investment manager, operating in all liquid asset classes across the world. We are a technology and data driven group implementing a scientific approach to investing. Combining data, research, technology and trading expertise has shaped QRT’s collaborative mindset which enables us to solve the most complex challenges. QRT’s culture of innovation continuously drives our ambition to deliver high quality returns for our investors. 

• FPGA systems testing and verification strategies
• Setting testing and verification standards
• Implementing simulation and hardware testing for multiple exchanges

• A deep understanding of functional verification, code linting and hardware testing
• Solid understanding of layered reusable environments, scoreboards, functional coverage models, randomized stimulus, and self-checking harnesses using SystemVerilog, UVM or cocotb.
• Python and C++ programming in a Linux environment
• Familiarity with CI/CD pipelines (Jenkins, GitLab CI, Bamboo, etc)
• An ability to see through complexity to identify simple solutions
• Excellent problem-solving skills and the ability to work independently and as part of a team
• Strong understanding of networking concepts including TCP/IP, UDP/IP is desirable

About Epirus

Epirus is a high-growth technology company dedicated to overcoming the asymmetric challenges inherent to the future of national security. Epirus' flagship product, Leonidas, is a software-defined system built using intelligent power management techniques that allow power-hungry systems to do more with less.  

Job Summary: This is an exciting role in an innovative company. The ideal candidate for the position is someone who has experience developing high-performance real-time, autonomous software systems to rapidly develop next-generation products.  Employ your expertise by developing software systems that support functions such as autonomous target tracking, agile electronic beam-forming, and real-time hardware control.

Responsibilities: 

• Design and implement software of embedded devices and systems from requirements to production and deployment 
• Design, develop, code, test, and debug system software 
• Build real-time control software for a variety of projects 
• Analyze and enhance the efficiency, stability and scalability of system resources 
• Direct software QA and optimize I/O performance 
• Interface with hardware design and development 
• Assess third-party and open-source software 
• Lead teams to create minimum viable products from an idea 
• Derive software frameworks and architectures to accelerate development 
• Mentor peers to advance team velocity

Basic Qualifications:

• 5+ years of development in C and C++ 
• 3+ years working with embedded systems 
• Additional experience with one or more modern systems language(s): Python, Java, VHDL, Verilog, Go, Rust, etc. 
• Versed in multithreaded design (concurrency primitives, resource management, etc.) 
• Competent in computer science concepts (algorithms, data structures, object-oriented programming, etc.) 
• Strong foundations in mathematics and linear algebra 
• Adequate knowledge of reading schematics and data sheets for components 
• Bachelor’s degree in computer science or a similar discipline, Master’s degree preferred
• This is an on-site position; availability to work in our HQ in Torrance is required

Preferred Skills and Experience:

• 2+ years of experience with Xilinx FPGA and Embedded Cortex CPU architectures 
• Experience building software for real-time operating environments with specific latency requirements 
• Experience with Embedded Linux and/or software integration with FPGA firmware 
• Knowledge or experience with digital signal processing (DSP) or radio frequency (RF) technologies 
• User experience with DevOps Pipeline tools 
• Experience with Docker or Helm  
• Scrum Master Certification 
• Desire to mentor new hires 
• Exposure or interest in sensor fusion, machine learning, or AI

ITAR REQUIREMENTS: 

• To conform to U.S. Government space technology export regulations, including the International Traffic in Arms Regulations (ITAR) you must be a U.S. citizen, lawful permanent resident of the U.S., protected individual as defined by 8 U.S.C. 1324b(a)(3), or eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here.  

At Epirus, you’ll work with technical peers and great people—and get first crack at some of the defining technology challenges of our time. Here, “impossible” is just a challenge. We're a diverse, fast-growing team of change-makers fueling the future of energy with revolutionary solutions. Join us and rewrite the rules. 

Voyager is an innovative defense, national security and space technology company committed to advancing and delivering transformative, mission-critical solutions. We tackle the most complex challenges to unlock new frontiers for human progress, fortify national security, and protect critical assets to lead in the race for technological and operational superiority from ground to space. 

Forge the Future: Join Voyager Technologies 

The future belongs to those who build it. At Voyager Technologies, we’re building technologies that protect lives, expand frontiers and prepare us for what’s next. And we’re doing that with people who are wired to solve, build, adapt and lead. These roles are not for the faint of heart.  

You’ll help lay the foundation for humanity's future. Join a culture where innovation thrives, curiosity is rewarded, and impact is real. We’re a company of doers, thinkers and builders, united by purpose and grounded in reality. 

If you want to put your skills to work where the stakes are real and the mission is bigger than any one person, forge the future with Voyager. 

The FPGA Engineer for our Products line is responsible for assisting in the design of cutting-edge components for space and national security applications including Software Defined Radios, Digital Processing Systems, Space Rated Cameras, Star Trackers and Laser Communications.

The position reports to the VP of Product Design and is part of the Engineering department. This role is onsite and based in San Diego, CA. 

In this role, the essential functions are:

• Designing and testing complex, high speed, FPGA (mostly Xilinx) designs implementing high-throughput algorithms.
• Designing and testing embedded applications using the Xilinx Zynq family.
• Developing architectures compatible with embedded Linux environments.
• Designing and supporting top-level system simulations.
• Translating system requirements into FPGA architectures.
• Implementing and documenting FPGA designs using HDL (VHDL, System Verilog, etc.).
• Supporting systems integration and Test Engineering to produce functional designs.
• Implementing and contributing to the architecture of current and next generation multi-megapixel camera systems, interfacing with the Camera Link and SpaceWire standards.
• Designing systems capable of handling Imager data and Image processing (Embedded Camera Development).
• Creating test plans to assure integrated performance meets specification.

If your experience aligns with our basic qualifications and you are inspired by our mission, we’d like to connect. If you don’t see the right role right now, Join Our Talent Community and stay connected as we continue to build what’s next. 

• Bachelor’s degree in Electrical Engineering
• 5+ years of experience with firmware design, integration, & test (preferably with the Xilinx family)
• Experience with implementing and documenting FPGA designs using HDL (VHDL, System Verilog, etc.).
• Experience with lab equipment
• Experience drafting comprehensive technical documentation
• Capable of multi-tasking; working on multiple projects & supporting production activities
• Strong technical background; capable of coming up-to-speed quickly on new technologies.
• Good communication, with the ability to work both individually and collaboratively in a team environment.

The good faith base salary range for this role is $125,000 - $185,000 at the time of this posting. Where you fall within the range depends on your experience, skills, and location. This range reflects base salary only and does not include benefits or bonus/incentive. This range may be adjusted in the future.

Voyager offers a highly competitive total compensation package designed to support the well-being, growth, and success of our employees. Employees benefit from a flexible and comprehensive rewards program that supports both professional and personal well-being.  

• Unlimited Flexible Time Off (FTO), empowering employees to take the time they need to recharge and maintain a healthy work-life balance
• Comprehensive medical, dental, and vision coverage for employees and their families, with a significant portion of premiums covered by the company and many benefits paid at 100% for employees
• Flexible, affordable gym memberships with 12,700+ options nationwide including 24 Hour Fitness, EoS Fitness, Crunch Fitness, Anytime Fitness, Blink Fitness, Chuze Fitness and more! No long term contracts and FREE on-demand workout videos before you enroll
• 401(k) retirement plan with a company match of up to 4% to help you build long-term financial security
• Company wellness programs that support physical and mental well-being
• Additional voluntary benefits and employee support resources
• The opportunity to work alongside a highly talented team in an innovative, mission driven environment

Voyager is an Equal Opportunity Employer. Employment decisions are made without regard to race, color, religion, national or ethnic origin, sex, sexual orientation, gender identity or expression, age, disability, protected veteran status or other characteristics protected by law.  

To conform to U.S. Government export regulations, including the International Traffic in Arms Regulations (ITAR) (22 CFR Parts 120–130) and the Export Administration Regulations (EAR) (15 CFR Parts 730–774), applicants for this position must be a U.S. Person: a US Citizen, a lawful permanent resident of the U.S., or a protected individual as defined by 8 U.S.C. § 1324b(a)(3). Applicants must be eligible to obtain any required export authorizations from the U.S. Department of State or the U.S. Department of Commerce.

Minority/Female/Disabled/Veteran 

The statements contained in this job description are intended to describe the general content and requirements for performance of this job. It is not intended to be an exhaustive list of all job duties, responsibilities, and requirements. This job description is not an employment agreement or contract. Management has the exclusive right to alter the scope of work within the framework of this job description at any time without prior notice. 

ABOUT THE TEAM

Anduril's Space team is dedicated to expanding our AI-powered capabilities into the final frontier, enhancing Space Domain Awareness, Space Control, and Command and Control for U.S. military and allied partners. We're developing fully integrated hardware and software systems, including Lattice for Space Missions and modular payloads, to address growing threats in space and ensure our Guardians maintain a decisive advantage in this contested warfighting domain.

ABOUT THE JOB

We are looking for a Sr. FPGA/SoC Engineer to join our rapidly growing team in Costa Mesa, CA. In this role, you will be responsible for developing FPGA/SoC firmware and overseeing 3rd party development. You will work with internal and external design teams to develop products for use in orbit. This will require architecture, RTL generation and debug.

WHAT YOU’LL DO

• Rapidly develop, test, and implement FPGA designs using Xilinx SoC/FPGA.
• Integrate third-party vendors IP, as necessary.
• Work with third-party developers to ensure timely product success
• Perform digital circuit design, VHDL/Verilog coding, synthesis, place and route, timing closure, simulation, and verification. 
• Participate in entire design life cycle: from requirements and concept, through design and hand on testing/board bring up.
• Implement a variety of signal types such as high speed comms (ethernet, serial), signal processing (analog, digital).
• Ensure designs meet all relevant safety and performance standards, with traceability back to top-level system requirements, as necessary.
• Investigate and resolve bugs found during hand on testing (at HDL level and system level).

REQUIRED QUALIFICATIONS

• 5 years of experience preferred in FPGA/HDL hardware design. Experience with Xilinx SoC (Versal) is highly preferred.
• Familiarity with design software like Vivado (preferred), ModelSim, or Quartus.
• Proficient in VHDL and/or Verilog.
• Ability to work in a fast-paced, challenging environment.
• Excellent problem-solving and organizational skills.
• Strong communication and teamwork skills.
• Experience in SoC hardware bring-up, preferably on ARM-based systems.
• Eligible to obtain and maintain an active U.S. Secret security clearance. 

PREFERRED QUALIFICATIONS

• Working knowledge of designing for safety-critical functions.
• FPGA interfaces and high speed busses.
• Experience with systems on a Chip (SoC).
• Low-level firmware (C/C++) development for bring-up and test.
• Experience writing HDL for Space applications.

WHAT IS AIS?

Anduril Intelligence Systems (AIS) is focused on positioning Anduril as a lead provider of specialized engineering and products for Intelligence Community (IC) customers. We work within the IC to understand their requirements, shape their concepts of operation, and deliver exquisite capability across their problem set. We aim to develop and deploy critically needed capabilities that address our customers’ most pressing national security requirements.

ABOUT THE JOB

We are looking for a Staff FPGA Engineer to join our rapidly growing team in Reston, Virginia. You will be responsible for rapidly developing, testing, and implementing FPGA designs on Xilinx SoC/FPGA platforms. This requires strong skills in digital circuit design, VHDL/Verilog coding, and simulation. 

WHAT YOU’LL DO

• Integrate third-party vendors IP, as necessary.
• Participate in entire design life cycle: from requirements and concept, through design and hand on testing/board bring up.
• Implement a variety of signal types such as high speed comms (ethernet, serial), signal processing (analog, digital).
• Ensure designs meet all relevant safety and performance standards, with traceability back to top-level system requirements, as necessary.
• Investigate and resolve bugs found during hand on testing (at HDL level and system level).

REQUIRED QUALIFICATIONS

• Bachelors degree in electrical engineering, electronics engineering, computer engineering or related field
• 8+ years of professional experience in FPGA design and development. Experience with Xilinx SoC is highly preferred
• Familiarity with design software like Vivado (preferred), ModelSim, or Quartus
• Proficient in VHDL and/or Verilog
• Ability to work in a fast-paced, challenging environment
• Excellent problem-solving and organizational skills
• Strong communication and teamwork skills
• Experience in SoC hardware bring-up, preferably on ARM-based systems
• Currently possesses and is able to maintain an active U.S. Secret security clearance

PREFERRED QUALIFICATIONS

• Working knowledge of designing for safety-critical functions.
• FPGA interfaces and high speed busses.
• Experience with systems on a Chip (SoC).
• Low-level firmware (C/C++) development for bring-up and test.

WHAT IS AIS?

Anduril Intelligence Systems (AIS) is focused on positioning Anduril as a lead provider of specialized engineering and products for Intelligence Community (IC) customers. We work within the IC to understand their requirements, shape their concepts of operation, and deliver exquisite capability across their problem set. We aim to develop and deploy critically needed capabilities that address our customers’ most pressing national security requirements.

ABOUT THE JOB

We are looking for a Staff FPGA Engineer to join our rapidly growing team in Reston, Virginia. You will be responsible for rapidly developing, testing, and implementing FPGA designs on Xilinx SoC/FPGA platforms. This requires strong skills in digital circuit design, VHDL/Verilog coding, and simulation. 

WHAT YOU’LL DO

• Integrate third-party vendors IP, as necessary.
• Participate in entire design life cycle: from requirements and concept, through design and hand on testing/board bring up.
• Implement a variety of signal types such as high speed comms (ethernet, serial), signal processing (analog, digital).
• Ensure designs meet all relevant safety and performance standards, with traceability back to top-level system requirements, as necessary.
• Investigate and resolve bugs found during hand on testing (at HDL level and system level).

REQUIRED QUALIFICATIONS

• Bachelors degree in Electrical Engineering, Electronics Engineering, Computer Engineering or related field
• 12+ years of professional experience in FPGA design and development. Experience with Xilinx SoC is highly preferred
• Familiarity with design software like Vivado (preferred), ModelSim, or Quartus
• Proficient in VHDL and/or Verilog
• Experience in SoC hardware bring-up, preferably on ARM-based systems
• Ability to work in a fast-paced, challenging environment
• Excellent problem-solving and organizational skills
• Strong communication and teamwork skills
• Currently possesses and is able to maintain an active U.S. Secret security clearance

PREFERRED QUALIFICATIONS

• Working knowledge of designing for safety-critical functions
• FPGA interfaces and high speed busses
• Experience with systems on a Chip (SoC)
• Low-level firmware (C/C++) development for bring-up and test

PsiQuantum’s mission is to build the first useful quantum computers—machines capable of delivering the breakthroughs the field has long promised. Since our founding in 2016, our singular focus has been to build and deploy million-qubit, fault-tolerant quantum systems. 

Quantum computers harness the laws of quantum mechanics to solve problems that even the most advanced supercomputers or AI systems will never reach. Their impact will span energy, pharmaceuticals, finance, agriculture, transportation, materials, and other foundational industries. 

Our architecture and approach is based on silicon photonics. By leveraging the advanced semiconductor manufacturing industry—including partners like GlobalFoundries—we use the same high-volume processes that already produce billions of chips for telecom and consumer electronics. Photonics offers natural advantages for scale: photons don’t feel heat, are immune to electromagnetic interference, and integrate with existing cryogenic cooling and standard fiber-optic infrastructure. 

In 2024, PsiQuantum announced government-funded projects to support the build-out of our first utility-scale quantum computers in Brisbane, Australia, and Chicago, Illinois. These initiatives reflect a growing recognition that quantum computing will be strategically and economically defining—and that now is the time to scale. 

PsiQuantum also develops the algorithms and software needed to make these systems commercially valuable. Our application, software, and industry teams work directly with leading Fortune 500 companies—including Lockheed Martin, Mercedes-Benz, Boehringer Ingelheim, and Mitsubishi Chemical—to prepare quantum solutions for real-world impact. 

Quantum computing is not an extension of classical computing. It represents a fundamental shift—and a path to mastering challenges that cannot be solved any other way. The potential is enormous, and we have a clear path to make it real. 

Come join us. 

Job Summary:

The mission of PsiQuantum's Principal Hardware Design Engineer role is to support the Electronics team by owning hardware designs integral to the underlying system of the quantum computer. This engineer will collaborate in cross-functional teams of thermal, mechanical, firmware, optical engineers. The designs will meet the requirements of the overall system architecture and physical framework of the quantum computer.

Responsibilities:

• Define, Design and deliver production ready high-speed embedded hardware systems.
• Design, create schematics, and oversee PCB layout of analog and digital circuitry consisting of but not limited to high-speed transceivers, 10+ Gbps electrical and optical data links, FPGA's, microcontrollers, clock distribution, and power distribution.
• Ensure signal integrity and EMI suppression is accounted for in all designs.
• Design and create test set-ups for testing of electro-optic modules.
• Characterize, optimize, and debug analog, digital, and electro-optic circuitry using equipment such as mixed signal & sampling oscilloscopes, vector network analyzers, signal generators, multimeters, DC power supplies.
• Develop software to drive measurements.
• Analyze data and extract key performance parameters.
• Maintain detailed documentation of hardware designs, test results, and design changes.
• Software tools:
  • Orcad Schematic Capture and Allegro PCB Layout
  • C++, Python, RTL (VHDL or Verilog)
  • Keysight PathWave ADS
  • Microsoft Office

Experience/Qualifications:

• 7 years of experience with a Master Degree.
• 9-12 years of experience with a B.S. Degree.
• Results oriented.
• Delivers on commitments.
• Attention to detail.
• Data-driven in decision-making.
• Strong problem-solving skills.
• Proven team player with an ability to work effectively across departments, sites, time zones in direct and matrix team environments.
• Excellent verbal and written communication skills with an ability to communicate effectively to a variety of audiences ranging from senior leadership and technical experts to entry-level staff.

PsiQuantum provides equal employment opportunity for all applicants and employees. PsiQuantum does not unlawfully discriminate on the basis of race, color, religion, sex (including pregnancy, childbirth, or related medical conditions), gender identity, gender expression, national origin, ancestry, citizenship, age, physical or mental disability, military or veteran status, marital status, domestic partner status, sexual orientation, genetic information, or any other basis protected by applicable laws.

Note: PsiQuantum will only reach out to you using an official PsiQuantum email address and will never ask you for bank account information as part of the interview process. Please report any suspicious activity to recruiting@psiquantum.com.

We are not accepting unsolicited resumes from employment agencies.

What MatX Is Building

MatX designs hardware tailored for the world’s best AI models. Our hardware will make a given level of intelligence available 3-5 years sooner. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the world’s largest models. 

We are seeking an experienced System-on-Chip (SoC) Architect to lead the design of our next-generation AI-focused, server-class silicon.

What You'll Do Here

• Lead SoC architecture by translating Product Requirements Documents (PRDs) into SoC-level architectures in collaboration with subsystem architects and cross-functional teams
• Define SoC architecture including memory, systems, interconnects, clocking, power, IP requirements, and system integration
• Define system flows for power-up, boot, and recovery
• Own PPA feasibility and drive power, performance, and area trade-offs with implementation teams
• Own architectural specifications and documentation from definition through productization

Who You Are

• Industry experience in complex SoC architectures
• Knowledge of memory systems and interconnect fabrics, including industry standards
• Ability to define functional and PPA requirements from use cases
• Sound architectural judgment in driving trade-off decisions
• Excellent technical communication, documentation, and organizational skills
• Experience collaborating across hardware, software, and third-party IP teams
• Programming/scripting skills (verilog, bash, C/C++, python etc)

Compensation

The US base salary for this full-time position is determined based on a variety of factors including role, experience, location, job related skills, and relevant education and training. Career length is only a guideline for compensation.

• Early Career - $120,000 - $275,000 + equity
• Mid Career - $175,000 - $450,000 + equity
• Senior Career - $275,000 - $600,000 + equity

What We Offer

• A Stake in our success A cash/equity mix that fits your needs and option to do early exercise
• Health & Wellness Company subsidized Health, Dental, Vision, and Life insurance; Pre-tax Health Savings Accounts with generous company contribution (even if you don’t)
• Time To Recharge 4 weeks paid time off (accrued), 12 company holidays, and 3 weeks remote/flexible work per year
• Support to Parents Up to 12 weeks of paid parental leave, regardless of your path to parenthood
• Learning & Development $1,500 yearly towards your professional development e.g. conferences, courses, and other learning opportunities
• Team Connection Team Lunches, quarterly off-sites, and regular town halls
• Financial Wellbeing 401K and/or Roth IRA, with 5% company contribution, even if you don’t!
• Flexible Spending Accounts Pre-tax spend accounts for medical, dental/vision, dependent care, parking, and transit expenses
• Commute On Us For those commuting up to 1 hour, put your rideshare cost on our company card and reclaim the drive-time to get work done!
• MatX E[x]tras $50 per month to use on the perks you care about most 
• Remote Perks We work remotely Monday & Friday, supported by home-tech setup, and remote wifi expense reimbursement

As part of our dedication to the diversity of our team and our focus on creating an inviting and inclusive work experience, MatX is committed to a policy of Equal Employment Opportunity and will not discriminate against an applicant or employee on the basis of race, color, religion, creed, national origin or ancestry, sex, gender, gender identity, gender expression, sexual orientation, age, physical or mental disability, medical condition, marital/domestic partner status, military and veteran status, genetic information or any other legally recognized protected basis under federal, state or local laws, regulations or ordinances.

All candidates must be a

This position requires access to information that is subject to U.S. export controls. This offer of employment is contingent upon the applicants capacity to perform job functions in compliance with U.S. export control laws without obtaining a license from U.S. export control authorities.

MatX does not accept unsolicited resumes from individual recruiters or third-party recruiting agencies in response to job postings. No fee will be paid to third parties who submit unsolicited candidates directly to our hiring managers or People team and any resumes submitted are deemed to be the property of MatX.

What MatX Is Building

MatX designs hardware tailored for the world’s best AI models. Our hardware will make a given level of intelligence available 3-5 years sooner. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the world’s largest models. 

We are seeking an experienced System-on-Chip (SoC) Architect to lead the design of our next-generation AI-focused, server-class silicon.

What You'll Do Here

• Lead SoC architecture by translating Product Requirements Documents (PRDs) into SoC-level architectures in collaboration with subsystem architects and cross-functional teams
• Define SoC architecture including memory, systems, interconnects, clocking, power, IP requirements, and system integration
• Define system flows for power-up, boot, and recovery
• Own PPA feasibility and drive power, performance, and area trade-offs with implementation teams
• Own architectural specifications and documentation from definition through productization

Who You Are

• Industry experience in complex SoC architectures
• Knowledge of memory systems and interconnect fabrics, including industry standards
• Ability to define functional and PPA requirements from use cases
• Sound architectural judgment in driving trade-off decisions
• Excellent technical communication, documentation, and organizational skills
• Experience collaborating across hardware, software, and third-party IP teams
• Programming/scripting skills (verilog, bash, C/C++, python etc)
• This is a hybrid role that will require you to work from our Mountain View, CA office 3 days a week on Tuesday through Thursday

Compensation

The US base salary for this full-time position is determined based on a variety of factors including role, experience, location, job related skills, and relevant education and training. Career length is only a guideline for compensation.

• Early Career - $120,000 - $275,000 + equity
• Mid Career - $175,000 - $450,000 + equity
• Senior Career - $275,000 - $600,000 + equity

What We Offer

• A Stake in our success A cash/equity mix that fits your needs and option to do early exercise
• Health & Wellness Company subsidized Health, Dental, Vision, and Life insurance; Pre-tax Health Savings Accounts with generous company contribution (even if you don’t)
• Time To Recharge 4 weeks paid time off (accrued), 12 company holidays, and 3 weeks remote/flexible work per year
• Support to Parents Up to 12 weeks of paid parental leave, regardless of your path to parenthood
• Learning & Development $1,500 yearly towards your professional development e.g. conferences, courses, and other learning opportunities
• Team Connection Team Lunches, quarterly off-sites, and regular town halls
• Financial Wellbeing 401K and/or Roth IRA, with 5% company contribution, even if you don’t!
• Flexible Spending Accounts Pre-tax spend accounts for medical, dental/vision, dependent care, parking, and transit expenses
• Commute On Us For those commuting up to 1 hour, put your rideshare cost on our company card and reclaim the drive-time to get work done!
• MatX E[x]tras $50 per month to use on the perks you care about most 
• Remote Perks We work remotely Monday & Friday, supported by home-tech setup, and remote wifi expense reimbursement

As part of our dedication to the diversity of our team and our focus on creating an inviting and inclusive work experience, MatX is committed to a policy of Equal Employment Opportunity and will not discriminate against an applicant or employee on the basis of race, color, religion, creed, national origin or ancestry, sex, gender, gender identity, gender expression, sexual orientation, age, physical or mental disability, medical condition, marital/domestic partner status, military and veteran status, genetic information or any other legally recognized protected basis under federal, state or local laws, regulations or ordinances.

All candidates must be authorized to work in the United States and work from our offices in Mountain View Tuesdays-Thursdays.

This position requires access to information that is subject to U.S. export controls. This offer of employment is contingent upon the applicants capacity to perform job functions in compliance with U.S. export control laws without obtaining a license from U.S. export control authorities.

MatX does not accept unsolicited resumes from individual recruiters or third-party recruiting agencies in response to job postings. No fee will be paid to third parties who submit unsolicited candidates directly to our hiring managers or People team and any resumes submitted are deemed to be the property of MatX.

What You’ll Do

We are seeking an RTL engineer to develop high-fidelity, advanced IP-level power macromodels for AI computing memory component IPs. The role focuses on translating RTL/SystemC/C behavior into time-indexed, input-dependent power models.

Location: Daily onsite presence at our San Jose, CA office in alignment with our Flexible Work policy

Reports to: SVP, R&D (Power & Thermal Lab)

• Develop high-fidelity, advanced RTL- SystemC-, and C-based power macromodels for AI memory component IPs using analytical modeling, LUT, FSM, NN, and their hybrid.
• Extract activity-, value-, and state-dependent power features from C/SystemC/RTL simulations.
• Define power-relevant functional states (transaction/state-based abstraction).
• Support trace-driven power modeling, aligned with C/SystemC workload traces.
• Perform synthesis-assisted calibration using average and worst-case power anchors when available.
• Validate macromodel accuracy against reference RTL/gate-level results and real-silicon data when available.
• Collaborate with software engineers on feature semantics, timing alignment, and model interfaces.
• Contribute to scalable IP-wise composition for full-system power simulation.

What You Bring

• Bachelors degree 20+ years of experience or Masters degree 18+ years of experience.
• Strong RTL design, synthesis and analysis experience (Verilog/SystemVerilog/SystemC).
• Solid understanding of dynamic and leakage power mechanisms in CMOS and interconnects.
• Hands-on experience with logic synthesis and power analysis tools, including VCS, VC Formal, Design Compiler, PrimeTime-PX, StarRC, PowerArtist, Verdi, etc.
• Hands-on experience with power modeling in academia, including McPAT, CACTI, Wattch, etc. and industry tools such as Synopsys Platform Architect.
• Familiarity with SystemC or transaction-level modeling.
• Ability to abstract RTL behavior into compact analytical, table-based, FSM-based, and AL/ML models.
• Knowledge of power macromodeling, power estimation flows, or architectural power analysis.

Preferred Qualifications

• Experience with GPU, computer architecture, AI memory, memory controllers, PHYs, or high-speed I/O.
• Knowledge of cross-coupling capacitance, clock power modeling, and power and signal integrity.
• Exposure to low-power design and thermal management.
• Exposure to power macromodeling, power estimation flows, or architectural power analysis.

What You’ll Do

We are seeking an RTL engineer to develop high-fidelity, advanced IP-level power macromodels for AI computing memory component IPs. The role focuses on translating RTL/SystemC/C behavior into time-indexed, input-dependent power models.

Location: Daily onsite presence at our San Jose, CA office in alignment with our Flexible Work policy

Reports to: SVP, R&D (Power & Thermal Lab)

• Develop high-fidelity, advanced RTL- SystemC-, and C-based power macromodels for AI memory component IPs using analytical modeling, LUT, FSM, NN, and their hybrid.
• Extract activity-, value-, and state-dependent power features from C/SystemC/RTL simulations.
• Define power-relevant functional states (transaction/state-based abstraction).
• Support trace-driven power modeling, aligned with C/SystemC workload traces.
• Perform synthesis-assisted calibration using average and worst-case power anchors when available.
• Validate macromodel accuracy against reference RTL/gate-level results and real-silicon data when available.
• Collaborate with software engineers on feature semantics, timing alignment, and model interfaces.
• Contribute to scalable IP-wise composition for full-system power simulation.

What You Bring

• Bachelors degree 5+ years of experience or Masters degree 3+ years of experience.
• Strong RTL design, synthesis and analysis experience (Verilog/SystemVerilog/SystemC).
• Solid understanding of dynamic and leakage power mechanisms in CMOS and interconnects.
• Hands-on experience with logic synthesis and power analysis tools, including VCS, VC Formal, Design Compiler, PrimeTime-PX, StarRC, PowerArtist, Verdi, etc.
• Hands-on experience with power modeling in academia, including McPAT, CACTI, Wattch, etc. and industry tools such as Synopsys Platform Architect.
• Familiarity with SystemC or transaction-level modeling.
• Ability to abstract RTL behavior into compact analytical, table-based, FSM-based, and AL/ML models.
• Knowledge of power macromodeling, power estimation flows, or architectural power analysis.

Preferred Qualifications

• Experience with GPU, computer architecture, AI memory, memory controllers, PHYs, or high-speed I/O.
• Knowledge of cross-coupling capacitance, clock power modeling, and power and signal integrity.
• Exposure to low-power design and thermal management.
• Exposure to power macromodeling, power estimation flows, or architectural power analysis.

The AGI (Artificial General Intelligence) Computing Lab is dedicated to solving the complex system-level challenges posed by the growing demands of future AI/ML workloads. Our team is committed to designing and developing scalable platforms that can effectively handle the computational and memory requirements of these workloads while minimizing energy consumption and maximizing performance. To achieve this goal, we collaborate closely with both hardware and software engineers to identify and address the unique challenges posed by AI/ML workloads and to explore new computing abstractions that can provide a better balance between the hardware and software components of our systems. Additionally, we continuously conduct research and development in emerging technologies and trends across memory, computing, interconnect, and AI/ML, ensuring that our platforms are always equipped to handle the most demanding workloads of the future. By working together as a dedicated and passionate team, we aim to revolutionize the way AI/ML applications are deployed and executed, ultimately contributing to the advancement of AGI in an affordable and sustainable manner. Join us in our passion to shape the future of computing!

Location:  Daily onsite presence at our San Jose, CA office / U.S. headquarters in alignment with our Flexible Work policy.

What You’ll Do

• Develop the verification infrastructure and automation environment involved in build, simulation, regression and triages.
• Lead the verification for IP blocks of an AI accelerator by working with architects and RTL engineers.
• Create direct or random testbench, define verification scope and test plans for both functional and performance validation, close the verification quality metrics.
• Provide comprehensive documentation of verification strategy and ensure test environment is easy to use.
• Mentor junior engineers when necessary
• Work cross-functionally in debugging failures with design, compiler and simulation engineers

What You Bring

• Bachelor’s with 15+ years, or Master’s with 13+ years, or PhD's with 10+ years of industry experience.
• Strong background in SoC or IP verification and test bench development using UVM, System Verilog, C/C++ and scripting languages such as Perl/Python.
• Experience verifying at multiple levels of logic from scratch, starting from complex IP blocks to dies to SoCs to full system testing
• Understanding RTL and strong overall debugging skills
• Prior experience with computational logic, interconnect networks and/or memory system is desirable
• Strong background in microarchitecture and computer architecture preferably in the area of AI accelerators
• Knowledge of FPGA and emulation platforms preferred
• Strong analytical and problem-solving skills
• Excellent communication and interpersonal skills
• Ability to work independently and as part of a team
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.

#LI-VL1

The AGI (Artificial General Intelligence) Computing Lab is dedicated to solving the complex system-level challenges posed by the growing demands of future AI/ML workloads. Our team is committed to designing and developing scalable platforms that can effectively handle the computational and memory requirements of these workloads while minimizing energy consumption and maximizing performance. To achieve this goal, we collaborate closely with both hardware and software engineers to identify and address the unique challenges posed by AI/ML workloads and to explore new computing abstractions that can provide a better balance between the hardware and software components of our systems. Additionally, we continuously conduct research and development in emerging technologies and trends across memory, computing, interconnect, and AI/ML, ensuring that our platforms are always equipped to handle the most demanding workloads of the future. By working together as a dedicated and passionate team, we aim to revolutionize the way AI/ML applications are deployed and executed, ultimately contributing to the advancement of AGI in an affordable and sustainable manner. Join us in our passion to shape the future of computing!

We are looking for a Senior Engineer, RTL Memory Centric Computing.  This role is being offered under the AGICL lab as a part of DSRA. We are a research-driven systems lab working at the intersection of large language models, accelerator hardware, and high-performance software stacks. Our mission is to design, prototype, and optimize next-generation AI systems through tight hardware–software co-design.

Location:  Daily onsite presence at our San Jose, CA office / U.S. headquarters in alignment with our Flexible Work policy.

What You’ll Do

• Develop IP for memory centric computing systems using Verilog, System Verilog and HLS
• Optimize the IP for performance, power, and area by leveraging advanced design techniques such as pipelining, parallelism, and data compression.
• Collaborate with Verification engineers to design and develop test plans
• Make design decisions out of a large design trade-off space across performance, power, thermal, and cost.
• Troubleshoot and debug hardware issues and ensure the quality of the design through verification and validation.
• Stay up-to-date with the latest advancements in machine learning and hardware architecture and contribute to the development of new technologies.
• Communicate effectively with stakeholders, including users, partners, and management, to ensure that the systems are delivered on time and within budget
• Complete other responsibilities as assigned.

What You Bring

• Bachelor’s with 15+ years, or Master’s with 13+ years, or PhD's with 10+ years of industry experience.
• Strong background in microarchitecture and computer architecture
• 5+ years of experience in front-end design methodology involving RTL development for complex control and data path IPs
• Experience in designing Memory Controller, NOC, Interconnect IP
• Experience in Memory Centric computing IP and  SOC integration
• Experience in AI/ML workloads.
• Strong analytical and problem-solving skills
• Excellent communication and interpersonal skills
• Ability to work independently and as part of a team
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change

#LI-VL1

What You’ll Do

The DRAM Development Lab (DDL) is part of Samsung’s Memory Business Unit, the industry's technology and volume leader in DRAM, HBM and NAND Flash.  DDL’s vision is to solve key problems of Cloud & Data center by developing the new technology for memory and storage. The SoC Architecture team is involved in  SoC‑level designs for emerging memory/storage solutions and validates each design’s feasibility with hands‑on RTL implementation. We are an integral part of Samsung’s strong R&D focus & lab innovation engine. We work closely with development teams to bring feature innovation to product roadmaps.

This role offers the opportunity to shape next-generation SoC and subsystem architectures while staying deeply hands-on in RTL design, integration, and validation. It is ideal for engineers who want to turn advanced memory and storage concepts into real hardware and drive them all the way to silicon

Job ID: 42896

Location: Daily onsite presence at our Folsom office in alignment with our Flexible Work policy

• Collaborate with architecture, design, verification, and system teams to define and implement SoC features and subsystems
• Translate architectural requirements into microarchitecture, RTL design, and verification plans
• Design and develop RTL for SoC blocks and integration logic using SystemVerilog/Verilog
• Drive block- and SoC-level integration activities, including clocking, reset, power intent, interfaces, and configuration infrastructure
• Analyze performance, power, area, and timing tradeoffs to deliver efficient and scalable designs
• Support design verification by debugging issues found in simulation, emulation, formal analysis, and silicon validation
• Participate in pre‑silicon validation and post‑silicon bring‑up, including root‑cause analysis and issue resolution
• Contribute to technical documentation, block specification, test plans, and design reviews

What You Bring

• Bachelors in Electrical, Computer Science or related with 15+ years of experience or Masters in Electrical, Computer Science or related Science with 13+ years of Industry Experience or PhD in Electrical, Computer Science or related Science with 10+ years of Industry experience preferred.
• Strong technical background in SSD architecture and storage technologies, including controller architecture, NAND/flash behavior, data path design, and system performance consideration. 
• Familiarity with DRAM architecture and memory subsystem design, including memory hierarchy, bandwidth/latency tradeoffs, buffering, and traffic behaviors. 
• Experience with data integrity and protection mechanisms, such as ECC, parity, CRC, RAID, and end-to-end data protection schemes. 
• Experience contributing to complex hardware products from architecture definition through RTL implementation, verification, and silicon bring-up. 
• Proven ability to collaborate effectively across architecture, design, verification, firmware, and validation teams. 
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-SF1

The AGI (Artificial General Intelligence) Computing Lab is dedicated to solving the complex system-level challenges posed by the growing demands of future AI/ML workloads. Our team is committed to designing and developing scalable platforms that can effectively handle the computational and memory requirements of these workloads while minimizing energy consumption and maximizing performance. To achieve this goal, we collaborate closely with both hardware and software engineers to identify and address the unique challenges posed by AI/ML workloads and to explore new computing abstractions that can provide a better balance between the hardware and software components of our systems. Additionally, we continuously conduct research and development in emerging technologies and trends across memory, computing, interconnect, and AI/ML, ensuring that our platforms are always equipped to handle the most demanding workloads of the future. By working together as a dedicated and passionate team, we aim to revolutionize the way AI/ML applications are deployed and executed, ultimately contributing to the advancement of AGI in an affordable and sustainable manner. Join us in our passion to shape the future of computing!

Location:  Daily onsite presence at our San Jose, CA office / U.S. headquarters in alignment with our Flexible Work policy.

What You’ll Do

• Develop the verification infrastructure and automation environment involved in build, simulation, regression and triages.
• Lead the verification for IP blocks of an AI accelerator by working with architects and RTL engineers.
• Create direct or random testbench, define verification scope and test plans for both functional and performance validation, close the verification quality metrics.
• Provide comprehensive documentation of verification strategy and ensure test environment is easy to use.
• Mentor junior engineers when necessary
• Work cross-functionally in debugging failures with design, compiler and simulation engineers

What You Bring

• Bachelor’s with 10+ years, or Master’s with 8+ years, or PhD's with 5+ years of industry experience.
• Strong background in SoC or IP verification and test bench development using UVM, System Verilog, C/C++ and scripting languages such as Perl/Python.
• Experience verifying at multiple levels of logic from scratch, starting from complex IP blocks to dies to SoCs to full system testing
• Understanding RTL and strong overall debugging skills
• Prior experience with computational logic, interconnect networks and/or memory system is desirable
• Strong background in microarchitecture and computer architecture preferably in the area of AI accelerators
• Knowledge of FPGA and emulation platforms preferred
• Strong analytical and problem-solving skills
• Excellent communication and interpersonal skills
• Ability to work independently and as part of a team
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.

#LI-VL1

The AGI (Artificial General Intelligence) Computing Lab is dedicated to solving the complex system-level challenges posed by the growing demands of future AI/ML workloads. Our team is committed to designing and developing scalable platforms that can effectively handle the computational and memory requirements of these workloads while minimizing energy consumption and maximizing performance. To achieve this goal, we collaborate closely with both hardware and software engineers to identify and address the unique challenges posed by AI/ML workloads and to explore new computing abstractions that can provide a better balance between the hardware and software components of our systems. Additionally, we continuously conduct research and development in emerging technologies and trends across memory, computing, interconnect, and AI/ML, ensuring that our platforms are always equipped to handle the most demanding workloads of the future. By working together as a dedicated and passionate team, we aim to revolutionize the way AI/ML applications are deployed and executed, ultimately contributing to the advancement of AGI in an affordable and sustainable manner. Join us in our passion to shape the future of computing!

We are looking for a Senior Engineer, RTL Memory Centric Computing.  This role is being offered under the AGICL lab as a part of DSRA. We are a research-driven systems lab working at the intersection of large language models, accelerator hardware, and high-performance software stacks. Our mission is to design, prototype, and optimize next-generation AI systems through tight hardware–software co-design.

Location:  Daily onsite presence at our San Jose, CA office / U.S. headquarters in alignment with our Flexible Work policy.

What You’ll Do

• Develop IP for memory centric computing systems using Verilog, System Verilog and HLS
• Optimize the IP for performance, power, and area by leveraging advanced design techniques such as pipelining, parallelism, and data compression.
• Collaborate with Verification engineers to design and develop test plans
• Make design decisions out of a large design trade-off space across performance, power, thermal, and cost.
• Troubleshoot and debug hardware issues and ensure the quality of the design through verification and validation.
• Stay up-to-date with the latest advancements in machine learning and hardware architecture and contribute to the development of new technologies.
• Communicate effectively with stakeholders, including users, partners, and management, to ensure that the systems are delivered on time and within budget
• Complete other responsibilities as assigned.

What You Bring

• Bachelor’s with 10+ years, or Master’s with 8+ years, or PhD's with 5+ years of industry experience.
• Strong background in microarchitecture and computer architecture
• 5+ years of experience in front-end design methodology involving RTL development for complex control and data path IPs
• Experience in designing Memory Controller, NOC, Interconnect IP
• Experience in Memory Centric computing IP and  SOC integration
• Experience in AI/ML workloads.
• Strong analytical and problem-solving skills
• Excellent communication and interpersonal skills
• Ability to work independently and as part of a team
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change

#LI-VL1

The role is Design for Test (DFT) for high-performance designs going into industry leading AI/ML architectures. The person coming into this role will be involved in all implementation aspects from RTL to tapeout for various IPs on the chip. High level challenges include reducing test cost while attaining high coverage, and facilitating debug and yield learnings while minimizing design intrusions. The work is done collaboratively with a group of highly experienced engineers across various domains of the ASIC.

This role is hybrid, based out of Bangalore.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Responsibilities:

• Implementation of DFT features into RTL using verilog.
• Understanding of DFT Architectures and micro-architectures.
• ATPG and test coverage analysis using industry standard tools.
• JTAG, Scan Compression, and ASST implementation.
• Gate level simulation using Synopsys VCS and Verdi.
• Support silicon bring-up and debug.
• MBIST planning, implementation, and verification.
• Support Test Engineering on planning, patterns, and debug.
• Develop efficient DFx flows and methodology compatible with front end and physical design flows

Experience & Qualifications:

• BS/MS/PhD in EE/ECE/CE/CS with at least 5 years of industry experience in advanced DFx techniques.
• DFx experience implementing in finFET technologies.
• Experience with industry standard ATPG and DFx insertion CAD tools.
• Familiarity with SystemVerilog and UVM.
• Fluent in RTL coding for DFx logic including lock-up latches, clock gates, and scan anchors.
• Understanding of low-power design flows such as power gating, multi-Vt and voltage scaling.
• Good understanding of high-performance, low-power design fundamentals.
• Knowledge of fault models including Stuck-at, Transition, Gate-Exhaustive, Path Delay, IDDQ, and Cell Aware.
• Exposure to post-silicon testing and tester pattern debug are major assets.
• Experience with Fault Campaigns a plus.
• Strong problem solving and debug skills across various levels of design hierarchies.

Team Description:

The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-machine interface applications. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future. To accelerate our pathway to human ready brain-computer interfaces, you will have the opportunity to partner with our electrical, microfabrication, chip designers, neuro and mechanical engineers.

Job Responsibilities:

We are looking for Analog and Mixed-Signal IC Design Engineer Interns who are interested in architecting and implementing innovative solutions with high energy-efficiency and compact silicon footprint and who thrive with the autonomy to propose creative approaches to problems. 

Neuralink strives to be, as much as possible, a meritocratic environment: we require honest and transparent communication to ensure the best ideas win out, and we believe the best solutions emerge and the best teams are created when you assemble high-performing individuals with different skill sets and perspectives, and allow them to engage in rigorous and thoughtful inquiry. We want to work with exceptional people, and, to the extent that you excel, we want you to take on more responsibility and help all of us succeed. If this speaks to you, come join us.

The Analog and Mixed-Signal IC Design Engineer Intern will be responsible for analog and mixed-signal chip design, from circuit design to layout and verification. 

• Define and implement innovative and optimal analog and mixed signal circuit architectures and transistor-level circuit solutions to achieve a variety of challenging noise, mismatch, distortion, power consumption, and cost requirements
• Defines verification plan for a portion of IP or chip and runs complex simulations and analyses (e.g., power, performance, linearity, yield) on designs
• Designs, programs, and runs complex tests and reviews tests of other team members; ensures bugs and other issues are identified and appropriately analyzed

Key Qualifications:

• Minimum 1 years of experience in analog/mixed-signal integrated CMOS circuit design for a specific area (e.g., delta-sigma ADC, SAR ADC, DAC, VCO, PLL, DLL, Audio CODEC and Class D audio amplifier, high speed PHY & SERDES) with a successful track record of silicon validation
• Minimum 3 months experience of application of technical skills outside of the classroom (examples: laboratory, research, extracurricular project teams, open source contributions, volunteering, personal projects or prior internship/work experience)
• The ideal candidates are people who get excited about building things, are highly analytical, and enjoy tackling new problems regularly

Preferred Qualifications:

• Skills in scripting and automation for complex simulation scenarios
• Experience in lab testing of high-precision analog and mixed-signal ICs
• Functional modeling experience and logic verification with Verilog AMS and SystemVerilog
• Experience in design and layout with advanced CMOS FinFET technologies
• Experience with design for high-volume production

Team Description:

The Brain Interfaces SoC Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-machine interface applications. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future.

Job Description and Responsibilities:

The engineer will be responsible for analog and mixed-signal chip design, from circuit design to layout and verification. Other responsibilities include:

• Design analog circuit building blocks and subsystems in transistor-level to achieve a variety of challenging noise, mismatch, distortion, power consumption, and cost requirements while satisfying top-level specifications
• Works with layout teams to oversee block-level layout of multiple blocks
• Planning and execution of analog verification plan for portion of IP or chip and runs complex simulations and analyses (e.g., power, performance, linearity, yield) on designs
• Designs, programs, and runs complex tests and reviews tests of junior team members; ensures bugs and other issues are identified and appropriately analyzed
• Consults with internal or external users and third-party vendors to guide implementation and ensure alignment with their needs and goals

Required Qualifications:

• Bachelor of Science degree and additional experience in a related technical field for at least 5 years after receiving the BS degree
• Minimum 5 years of experience in analog/mixed-signal integrated CMOS circuit design for a specific area (e.g., delta-sigma ADC, SAR ADC, DAC, VCO, PLL, DLL, Audio CODEC and Class D audio amplifier, high speed PHY & SERDES) with a successful track record of silicon validation
• The ideal candidates are people who get excited about building things, are highly analytical, and enjoy tackling new problems regularly

Preferred Qualifications:

• Masters or PhD in electrical engineering, physics, or other related fields
• Experience with design for high-volume production
• Experience in lab testing of high-precision analog and mixed-signal ICs
• Functional modeling experience and logic verification with Verilog AMS and SystemVerilog
• Experience in design and layout with advanced CMOS FinFET technologies
• Skills in scripting and automation for complex simulation scenarios

Job Summary

We are seeking a talented Signal Processing Engineer to design, develop, and optimize advanced digital signal processing (DSP) algorithms for on-chip and embedded implementation. In this role, you will create efficient, hardware-friendly algorithms that run directly on custom SoCs, enabling real-time processing with constraints on power, latency, area, and throughput. You will collaborate closely with the SoC, Firmware, and Machine Learning teams to translate high-level signal processing needs into production-ready solutions.

Key Responsibilities

• Design and develop signal processing algorithms for sensing neural activity in the cortex (e.g. spike detection), monitoring cortical electrode health, and more.
• Design and develop numerical algorithms, such as custom data compression to increase radio throughput.
• Develop fixed-point or quantized versions of algorithms optimized for constrained hardware.
• Implement and verify algorithms in high-level languages and transition them to hardware-friendly representations.
• Perform algorithm-to-architecture mapping: analyze trade-offs between accuracy, latency, power, and resource utilization on the SoCs.
• Collaborate with the digital design team to define micro-architectures for custom on-chip processing pipelines, including dataflow, pipelining, and parallelization.

Required Qualifications

• Education: BS, MS or PhD in Electrical Engineering, Computer Engineering, Signal Processing, or a related field.
• Experience: 3+ years in digital signal processing algorithm development or real-world products, with a focus on embedded or hardware-constrained implementations.
• Fluent in signal processing fundamentals (both analog and digital) and strong numerical capabilities.
• Familiarity with fixed-point arithmetic, quantization effects, and numerical precision trade-offs.
• Proficiency in Python and C for algorithm prototyping and simulation.

Preferred Qualifications

• Hands-on experience with Verilog/VHDL, or transitioning algorithms to RTL.
• Experience with dedicated DSP cores or accelerators.
• Track record of optimizing for power/area/latency in resource-constrained environments.

Base Salary Range:

 $121,000 - $230,500

About Graphcore

At Graphcore, we’re building the future of AI compute.

We’re a team of semiconductor, software and AI experts, with deep experience in creating the complete AI compute stack - from silicon and software to infrastructure at datacenter scale.

As part of the SoftBank Group, backed by significant long-term investment, we are delivering key technology into the fast-growing SoftBank AI ecosystem. To meet the vast and exciting AI opportunity, Graphcore is expanding its teams around the world.

We are bringing together the brightest minds to solve the toughest problems, in a place where everyone has the opportunity to make an impact on the company, our products and the future of artificial intelligence.

The Person 

Graphcore’s experienced, skilled, and motivated engineering team is heavily involved in shaping the future of AI. A successful candidate will exhibit exceptional knowledge in Design for Testability (DFT) and will have a strong technical background and experience in DFT methodologies, complemented by a robust, self-motivated work ethic. The ideal candidate should also have a focus on quality and demonstrate a good understanding of the importance of production test on the success of a product. Some hands-on experience in one or more of the following areas is essential: RTL design, simulations and debugging, synthesis, STA.  

The Role: 

We are expanding and looking for an experienced DFT engineers to join the Silicon team. As a part of our team, you will have the opportunity to work on next-generation AI designs targeted for data centers applications. 

Responsibilities: 

• Keep up with the latest industry trends in DFT domain and help adopt the latest DFT techniques and methodologies 

• Work closely with design, verification, physical design and product engineering teams to integrate DFT requirements into the overall design process 

• Define and implement DFT architecture and features for next-generation AI designs and support their verification effort 

• Develop efficient DFT flows and methodology compatible with silicon design flows 

• Work with 3rd party IPs to integrate the provided design into the DFT infrastructure 

• Generate structural test vectors, analyze and improve test coverage 

• Work with the product and test engineering teams to ensure successful silicon bring-up and help identify any silicon failures to enhance yield learning and improvement 

Requirements: 

• Very good understanding of DFT components like JTAG (IEEE 1149.x), IJTAG (IEEE P1687), Core Test (IEEE P1500), SSN (Streaming Scan Network), Test Compression, OCC etc. 

• Experience on developing DFT specifications and driving the implementation of the DFT features 

• Experience in MBIST and BISR implementation and verification is desired 

• Solid understanding of design verification methodologies for validating the DFT features using simulation in pre-silicon designs 

• Exposure to STA constraints development and analysis for DFT modes and SDF simulations would be a plus 

• Experience in Scan based testing and industry standard ATPG tools 

• Knowledge of ATPG pattern verification and gate-level simulation flows using Synopsys VCS and Verdi or other EDA tools 

• Very good knowledge of Digital Integrated Circuits and Systems 

• Hands-on experience with Verilog RTL coding and familiarity with System Verilog   

• Strong scripting and debugging skills using programming languages like Python, TCL, Perl, Shell etc. 

• Exposure to silicon bring-up, post-silicon testing and tester pattern debugging 

• Strong problem-solving skills across various levels of design hierarchies 

• Great team working and communication skills 

Academic Credentials 

• Bachelors or Masters or PhD in Computer engineering/Electrical engineering/Electronics Engineering

Benefits: 

In addition to a competitive salary, Graphcore offers flexible working, a generous annual leave policy, private medical insurance and health cash plan, a dental plan, pension (matched up to 5%), life assurance and income protection. We have a generous parental leave policy and an employee assistance programme (which includes health, mental wellbeing, and bereavement support). We offer a range of healthy food and snacks at our central Bristol office and have our own barista bar! We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments  

We welcome people of different backgrounds and experiences and are committed to building an inclusive work environment that makes Graphcore a great home for everyone. We are an equal opportunity employer and want to build a work environment where everyone is happy, productive and respectful so they can do their best work. If you have a disability or additional need that requires accommodation, just let us know. 

About Graphcore

At Graphcore, we’re building the future of AI compute.We’re a team of semiconductor, software and AI experts, with deep experience in creating the complete AI compute stack - from silicon and software to infrastructure at datacenter scale.As part of the SoftBank Group, backed by significant long-term investment, we are delivering key technology into the fast-growing SoftBank AI ecosystem.To meet the vast and exciting AI opportunity, Graphcore is expanding its teams around the world.We are bringing together the brightest minds to solve the toughest problems, in a place where everyone has the opportunity to make an impact on the company, our products and the future of artificial intelligence.

Job Summary  

Our team is at the forefront of the artificial intelligence revolution, enabling innovators from all industries and sectors to expand human potential with technology. The availability of specialised artificial intelligence compute will be a decisive factor in AI’s rate of progress. Graphcore allows innovators to go further, faster. What we do really makes a difference. Reporting to the Director of Silicon Architecture, the SoC Architects are responsible for the design, specification, modelling and integration of sub-systems within complex, high performance and highly integrated silicon devices at the forefront of AI acceleration technology. The role involves close collaboration with other groups, including architecture, silicon design, verification, hardware and software teams.  

The Team

The Silicon Architecture Team sits within the COO group. The SoC architects are responsible for the architectural specification, integration, modelling, validation and evaluation of numerous critical sub-systems, including high-speed interfaces for our upcoming AI acceleration platforms. 

Responsibilities and Duties 

• Defines team infrastructure and processes  

• Distilling product requirements and their effects on SoC/platform design trade-offs 

• Collaborating with processor, SoC and system architects to determine optimal solutions 

• When required, providing technical knowledge silicon design, verification, and hardware engineers to ensure implementation correctness  

• Good experience potential hard and soft third-party IP and liaising with third party IP vendors 

• Design and specification of performant SoC sub-systems and their associated integrations 

• Manages queries for the silicon bring-up, characterisation and evaluation activities as required 

• Drives delivery and planning of technical objectives 

• Advise in planning for infrastructure and processes  

• Silicon Architecture Team representation within cross-functional working groups 

• Mentors' senior technical engineers  

Candidate Profile  

Essential: 

• Degree in Electronic Engineering, Computer Science or related subject 

• Experience in the technical specification of complex silicon SoC devices 

• Strong software development experience 

• Solid understanding of complex computer/SoC architecture 

• Excellent communication skills 

• Strong experience in writing and developing technical specifications 

• In depth knowledge of RTL development and verification processes 

• Be a self-starter, able to motivate and support team members  

• Ability to work across teams and programming languages 

Desirable 

• Architecture modelling experience in Python/C++/Rust 

• Experience of machine learning or massively parallel computing systems 

• Verilog 

• Knowledge of one or more of DDR, PCIe, Ethernet, on-chip networks 

Benefits
In addition to a competitive salary, annual leave policy, medical and dental health plans, a gym card and employee pension (matched up to 4%). We review our benefits on a yearly basis to ensure we offer a valuable and rewarding benefits programme to our employees.  We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments.

About Graphcore

At Graphcore, we’re building the future of AI compute.

We’re a team of semiconductor, software and AI experts, with deep experience in creating the complete AI compute stack - from silicon and software to infrastructure at datacenter scale.

As part of the SoftBank Group, backed by significant long-term investment, we are delivering key technology into the fast-growing SoftBank AI ecosystem.

To meet the vast and exciting AI opportunity, Graphcore is expanding its teams around the world.

We are bringing together the brightest minds to solve the toughest problems, in a place where everyone has the opportunity to make an impact on the company, our products and the future of artificial intelligence.

The Team:

The verification team sits within the Silicon design team and is responsible for ensuring that the RTL created by the logical design team and used by the physical design team matches the architecture specification for Graphcore silicon. The silicon verification engineer is responsible for verification activities within Graphcore, helping the team meet the company objectives for quality silicon delivery.

Responsibilities

• Verification planning, specification and closure of functional coverage
• Providing feedback to architects
• Test generation and failure diagnosis/triage
• Contributing to shared verification infrastructure
• Ensuring good communication between sites

Essential skills:
• Verification experience in relevant industry
• Proven leadership and planning skills
• Highly motivated, a self starter, and a team player
• Ability to work across teams and programming languages to find root causes of deep and complex issues
• Experience of the verification process applied in CPU and/or ASIC environments
• System Verilog, Python, C++, Linux

Desirable skills:
• UVM
• SVA
• Assembly languages
• LLVM, GCC
• DVCS e.g. Git
• SGE or other DRMS
• XML and XPath/XSLT
• Web programming – HTML/DOM, Javascript, SQL  

Benefits: 

In addition to a competitive salary, Graphcore offers flexible working, a generous annual leave policy, private medical insurance and health cash plan, a dental plan, pension (matched up to 5%), life assurance and income protection. We have a generous parental leave policy and an employee assistance programme (which includes health, mental wellbeing, and bereavement support). We offer a range of healthy food and snacks at our central Bristol office and have our own barista bar! We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments  

We welcome people of different backgrounds and experiences and are committed to building an inclusive work environment that makes Graphcore a great home for everyone. We are an equal opportunity employer and want to build a work environment where everyone is happy, productive and respectful so they can do their best work. If you have a disability or additional need that requires accommodation, just let us know. 

Silicon Verification Engineer

Multiple roles across different levels

Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. 

As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Bengaluru which will play a central role in Graphcore's work building the future of AI computing.  

The verification team sits within the Silicon design team and is responsible for ensuring that the RTL created by the logical design team and used by the physical design team matches the architecture specification for Graphcore silicon. The silicon verification engineer is responsible for verification activities within Graphcore, helping the team meet the company objectives for quality silicon delivery.

Responsibilities

• Verification planning, specification and closure of functional coverage
• Providing feedback to architects
• Test generation and failure diagnosis/triage
• Contributing to shared verification infrastructure
• Ensuring good communication between sites

Essential skills:
• Verification experience in relevant industry
• Proven leadership and planning skills
• Highly motivated, a self starter, and a team player
• Ability to work across teams and programming languages to find root causes of deep and complex issues
• Experience of the verification process applied in CPU and/or ASIC environments
• System Verilog, Python, C++, Linux

Desirable skills:
• UVM
• SVA
• Assembly languages
• LLVM, GCC
• DVCS e.g. Git
• SGE or other DRMS
• XML and XPath/XSLT
• Web programming – HTML/DOM, Javascript, SQL  

Benefits:

In addition to a competitive salary, Graphcore offers a competitive benefits package. We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments. 

About Graphcore

At Graphcore, we’re building the future of AI compute.We’re a team of semiconductor, software and AI experts, with deep experience in creating the complete AI compute stack - from silicon and software to infrastructure at datacenter scale.As part of the SoftBank Group, backed by significant long-term investment, we are delivering key technology into the fast-growing SoftBank AI ecosystem.To meet the vast and exciting AI opportunity, Graphcore is expanding its teams around the world.We are bringing together the brightest minds to solve the toughest problems, in a place where everyone has the opportunity to make an impact on the company, our products and the future of artificial intelligence.

Job Summary  

Our team is at the forefront of the artificial intelligence revolution, enabling innovators from all industries and sectors to expand human potential with technology. The availability of specialised artificial intelligence compute will be a decisive factor in AI’s rate of progress. Graphcore allows innovators to go further, faster. What we do really makes a difference. Reporting to the Director of Silicon Architecture, the SoC Architects are responsible for the design, specification, modelling and integration of sub-systems within complex, high performance and highly integrated silicon devices at the forefront of AI acceleration technology. 

The role involves close collaboration with other groups, including architecture, silicon design, verification, hardware and software teams.  

The Team 

The Silicon Architecture Team sits within the COO group. The SoC architects are responsible for the architectural specification, integration, modelling, validation and evaluation of numerous critical sub-systems, including high-speed interfaces for our upcoming AI acceleration platforms. 

Responsibilities and Duties 

• Distilling product requirements and their effects on SoC/platform design trade-offs 

• Collaborating with processor, SoC and system architects to determine optimal solutions 

• Understanding of how to collaborate with silicon design, verification, and hardware engineers to demonstrate awareness and options for implementation correctness 

• Evaluating potential hard and soft third-party IP and liaising with third party IP vendors 

• Design and specification of performant SoC sub-systems and their associated integrations 

• Contribute to the silicon bring-up, characterisation and evaluation activities as required 

• Silicon Architecture Team representation within cross-functional working groups 

• Implement improvements to infrastructure and processes 

• Assist with complex debugging activities 

• Mentors Engineers with technical queries 

Candidate Profile  

Essential: 

• Degree in Electronic Engineering, Computer Science or related subject 

• Solid understanding of computer/SoC architecture 

• Excellent communication skills 

• Good experience in the writing of technical specifications 

• Knowledge of RTL development and verification processes 

• Be highly motivated, a self-starter, and a team player 
• Ability to work across teams and programming languages 

Desirable 

• Experience in the technical specification of complex silicon SoC devices 

• Experience of machine learning or massively parallel computing systems 

• Verilog 

• Low-level software experience, embedded C 
  
  
• Knowledge of one or more of DDR, PCIe, Ethernet, on-chip networks

Benefits
In addition to a competitive salary, annual leave policy, medical and dental health plans, a gym card and employee pension (matched up to 4%). We review our benefits on a yearly basis to ensure we offer a valuable and rewarding benefits programme to our employees.  We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments.

About Graphcore

At Graphcore, we’re building the future of AI compute.

We’re a team of semiconductor, software and AI experts, with deep experience in creating the complete AI compute stack - from silicon and software to infrastructure at datacenter scale.

As part of the SoftBank Group, backed by significant long-term investment, we are delivering key technology into the fast-growing SoftBank AI ecosystem.

To meet the vast and exciting AI opportunity, Graphcore is expanding its teams around the world.

We are bringing together the brightest minds to solve the toughest problems, in a place where everyone has the opportunity to make an impact on the company, our products and the future of artificial intelligence.

The Team:

The verification team sits within the Silicon design team and is responsible for ensuring that the RTL created by the logical design team and used by the physical design team matches the architecture specification for Graphcore silicon. The silicon verification engineer is responsible for verification activities within Graphcore, helping the team meet the company objectives for quality silicon delivery.

Responsibilities

• Verification planning, specification and closure of functional coverage
• Providing feedback to architects
• Test generation and failure diagnosis/triage
• Contributing to shared verification infrastructure
• Ensuring good communication between sites

Essential skills:
• Verification experience in relevant industry
• Proven leadership and planning skills
• Highly motivated, a self starter, and a team player
• Ability to work across teams and programming languages to find root causes of deep and complex issues
• Experience of the verification process applied in CPU and/or ASIC environments
• System Verilog, Python, C++, Linux

Desirable skills:
• UVM
• SVA
• Assembly languages
• LLVM, GCC
• DVCS e.g. Git
• SGE or other DRMS
• XML and XPath/XSLT
• Web programming – HTML/DOM, Javascript, SQL  

Benefits: 

In addition to a competitive salary, Graphcore offers flexible working, a generous annual leave policy, private medical insurance and health cash plan, a dental plan, pension (matched up to 5%), life assurance and income protection. We have a generous parental leave policy and an employee assistance programme (which includes health, mental wellbeing, and bereavement support). We offer a range of healthy food and snacks at our central Bristol office and have our own barista bar! We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments  

We welcome people of different backgrounds and experiences and are committed to building an inclusive work environment that makes Graphcore a great home for everyone. We are an equal opportunity employer and want to build a work environment where everyone is happy, productive and respectful so they can do their best work. If you have a disability or additional need that requires accommodation, just let us know. 

About Graphcore

At Graphcore, we’re building the future of AI compute.

We’re a team of semiconductor, software and AI experts, with deep experience in creating the complete AI compute stack - from silicon and software to infrastructure at datacenter scale.

As part of the SoftBank Group, backed by significant long-term investment, we are delivering key technology into the fast-growing SoftBank AI ecosystem.

To meet the vast and exciting AI opportunity, Graphcore is expanding its teams around the world.

We are bringing together the brightest minds to solve the toughest problems, in a place where everyone has the opportunity to make an impact on the company, our products and the future of artificial intelligence.

The Team:

The verification team sits within the Silicon design team and is responsible for ensuring that the RTL created by the logical design team and used by the physical design team matches the architecture specification for Graphcore silicon. The Silicon Verification Lead is responsible for verification activities within Graphcore, helping the team meet the company objectives for quality silicon delivery.

Responsibilities

• Verification planning, specification and closure of functional coverage
• Providing feedback to architects
• Test generation and failure diagnosis/triage
• Contributing to shared verification infrastructure
• Ensuring good communication between sites

Essential skills:
• Verification experience in relevant industry
• Proven leadership and planning skills
• Highly motivated, a self starter, and a team player
• Ability to work across teams and programming languages to find root causes of deep and complex issues
• Experience of the verification process applied in CPU and/or ASIC environments
• System Verilog, Python, C++, Linux

Desirable skills:
• UVM
• SVA
• Assembly languages
• LLVM, GCC
• DVCS e.g. Git
• SGE or other DRMS
• XML and XPath/XSLT
• Web programming – HTML/DOM, Javascript, SQL  

Benefits: 

In addition to a competitive salary, Graphcore offers flexible working, a generous annual leave policy, private medical insurance and health cash plan, a dental plan, pension (matched up to 5%), life assurance and income protection. We have a generous parental leave policy and an employee assistance programme (which includes health, mental wellbeing, and bereavement support). We offer a range of healthy food and snacks at our central Bristol office and have our own barista bar! We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments  

We welcome people of different backgrounds and experiences and are committed to building an inclusive work environment that makes Graphcore a great home for everyone. We are an equal opportunity employer and want to build a work environment where everyone is happy, productive and respectful so they can do their best work. If you have a disability or additional need that requires accommodation, just let us know. 

About Graphcore

At Graphcore, we’re building the future of AI compute.We’re a team of semiconductor, software and AI experts, with deep experience in creating the complete AI compute stack - from silicon and software to infrastructure at datacenter scale.As part of the SoftBank Group, backed by significant long-term investment, we are delivering key technology into the fast-growing SoftBank AI ecosystem.To meet the vast and exciting AI opportunity, Graphcore is expanding its teams around the world.We are bringing together the brightest minds to solve the toughest problems, in a place where everyone has the opportunity to make an impact on the company, our products and the future of artificial intelligence.

Job Summary 

Our team is at the forefront of the artificial intelligence revolution, enabling innovators from all industries and sectors to expand human potential with technology. The availability of specialised artificial intelligence compute will be a decisive factor in AI’s rate of progress. Graphcore allows innovators to go further, faster. What we do really makes a difference. Reporting to the Director of Silicon Architecture, the SoC Architects are responsible for the design, specification, modelling and integration of sub-systems within complex, high performance and highly integrated silicon devices at the forefront of AI acceleration technology. 

The role involves close collaboration with other groups, including architecture, silicon design, verification, hardware and software teams.  

The Team 

The Silicon Architecture Team sits within the COO group. The SoC architects are responsible for the architectural specification, integration, modelling, validation and evaluation of numerous critical sub-systems, including high-speed interfaces for our upcoming AI acceleration platforms. 

Responsibilities and Duties 

• Distilling product requirements and their effects on SoC/platform design trade-offs
• Collaborating with processor, SoC and system architects to determine optimal solutions
• Collaborating with silicon design, verification, and hardware engineers to ensure implementation correctness
• Evaluating potential hard and soft third-party IP and liaising with third party IP vendors
• Design and specification of performant SoC sub-systems and their associated integrations
• Contribute to the silicon bring-up, characterisation and evaluation activities as required
• Silicon Architecture Team representation within cross-functional working groups
• Implement discussed infrastructure and processes improvements agreed with team 
• Assist with debugging activities
• Mentoring junior engineers 

Candidate Profile  

Essential: 

• Degree in Electronic Engineering, Computer Science or related subject 

• Solid understanding of computer/SoC architecture 

• Excellent communication skills 

• Experienced in the writing of technical specifications 

• Knowledge of RTL development and verification processes 

• Be highly motivated, a self-starter, and a team player 

• Ability to work across teams and programming languages
   

Desirable 

• Experience in the technical specification of silicon SoC devices 

• Experience of machine learning or massively parallel computing systems 

• Verilog 

• Low-level software experience, embedded C 

• Knowledge of one or more of DDR, PCIe, Ethernet, on-chip networks 

Benefits
In addition to a competitive salary, annual leave policy, medical and dental health plans, a gym card and employee pension (matched up to 4%). We review our benefits on a yearly basis to ensure we offer a valuable and rewarding benefits programme to our employees.  We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments.

Silicon Verification Engineer

Multiple roles across different levels

Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. 

As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Bengaluru which will play a central role in Graphcore's work building the future of AI computing.  

The verification team sits within the Silicon design team and is responsible for ensuring that the RTL created by the logical design team and used by the physical design team matches the architecture specification for Graphcore silicon. The silicon verification engineer is responsible for verification activities within Graphcore, helping the team meet the company objectives for quality silicon delivery.

Responsibilities

• Verification planning, specification and closure of functional coverage
• Providing feedback to architects
• Test generation and failure diagnosis/triage
• Contributing to shared verification infrastructure
• Ensuring good communication between sites

Essential skills:

•8 to 12 Years of experience
•Verification experience in relevant industry
• Proven leadership and planning skills
• Highly motivated, a self starter, and a team player
• Ability to work across teams and programming languages to find root causes of deep and complex issues
• Experience of the verification process applied in CPU and/or ASIC environments
• System Verilog, Python, C++, Linux

Desirable skills:
• UVM
• SVA
• Assembly languages
• LLVM, GCC
• DVCS e.g. Git
• SGE or other DRMS
• XML and XPath/XSLT
• Web programming – HTML/DOM, Javascript, SQL  

Benefits:

In addition to a competitive salary, Graphcore offers a competitive benefits package. We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments. 

About Graphcore

At Graphcore, we’re building the future of AI compute.We’re a team of semiconductor, software and AI experts, with deep experience in creating the complete AI compute stack - from silicon and software to infrastructure at datacenter scale.As part of the SoftBank Group, backed by significant long-term investment, we are delivering key technology into the fast-growing SoftBank AI ecosystem.To meet the vast and exciting AI opportunity, Graphcore is expanding its teams around the world.We are bringing together the brightest minds to solve the toughest problems, in a place where everyone has the opportunity to make an impact on the company, our products and the future of artificial intelligence.

Job Summary  

Our team is at the forefront of the artificial intelligence revolution, enabling innovators from all industries and sectors to expand human potential with technology. The availability of specialised artificial intelligence compute will be a decisive factor in AI’s rate of progress. Graphcore allows innovators to go further, faster. What we do really makes a difference. Reporting to the Director of Silicon Architecture, the SoC Architects are responsible for the design, specification, modelling and integration of sub-systems within complex, high performance and highly integrated silicon devices at the forefront of AI acceleration technology. The role involves close collaboration with other groups, including architecture, silicon design, verification, hardware and software teams.  

The Team 

The Silicon Architecture Team sits within the COO group. The SoC architects are responsible for the architectural specification, integration, modelling, validation and evaluation of numerous critical sub-systems, including high-speed interfaces for our upcoming AI acceleration platforms. 

Responsibilities and Duties 

• Distilling product requirements and their effects on SoC/platform design trade-offs 

• Collaborating with processor, SoC and system architects to determine optimal solutions 

• When required, guiding silicon design, verification, and hardware engineers to ensure implementation correctness  

• Evaluating potential hard and soft third-party IP and liaising with third party IP vendors 

• Design and specification of performant SoC sub-systems and their associated integrations 

• Manages queries for the silicon bring-up, characterisation and evaluation activities as required 

• Drives delivery of technical objectives 

• Advise on planning for infrastructure and processes 

• Silicon Architecture Team representation within cross-functional working groups  

• Mentors' technical engineers  

Candidate Profile  

Essential: 

• Degree in Electronic Engineering, Computer Science or related subject 

• Experience in the technical specification of complex silicon SoC devices 

• Strong software development experience 

• Solid understanding of complex computer/SoC architecture 

• Excellent communication skills 

• Strong experience in the writing of technical specifications 

• Knowledge of RTL development and verification processes 

• Be highly motivated, a self-starter, and a team player 

• Ability to work across teams and programming languages 

Desirable 

• Architecture modelling experience in Python/C++/Rust 

• Experience of machine learning or massively parallel computing systems 

• Verilog 

• Knowledge of one or more of DDR, PCIe, Ethernet, on-chip networks 

Benefits
In addition to a competitive salary, annual leave policy, medical and dental health plans, a gym card and employee pension (matched up to 4%). We review our benefits on a yearly basis to ensure we offer a valuable and rewarding benefits programme to our employees.  We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments.

As an Astera Labs Physical Design Engineer (Place & Route) to play a crucial role in the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. This is a generalist physical design role requiring broad expertise across floorplanning, place-and-route, timing closure, and physical sign-off. You will work closely with designers, verification engineering, and engineering operations to drive blocks from RTL to GDSII. This role is fully on-site and in-person.

Basic Qualifications:

• Strong academic and technical background in electrical engineering. A Bachelor's degree in EE / Computer Engineering is required, and a Master's degree is preferred.
• 8+ years of experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind!

Required Experience:

• Hands-on and thorough knowledge of synthesis, place and route, timing, extraction, EM-IR, formal verification (equivalence) and other backend tools and methodologies for technologies 7nm or less.
• Block level ownership from architecture to GDSII, driving multiple complex designs to production.
• Experience with Cadence and/or Synopsys physical design tools/flows.
• Familiarity and working knowledge of SystemVerilog/Verilog.
• Proven expertise in developing/maintaining timing constraints, timing signoff methodology, timing closure at the block or full-chip level.
• Experience in working with IP vendors for both RTL and hard-macro blocks.
• Good scripting skills in Tcl, Python, or Perl.

Nice to Have Experience Includes:

• Knowledge of design for test (DFT).
• Familiarity with ECO methodologies and tools.
• Knowledge of LVS/DRC closures.
• Experience with high-speed SERDES or Ethernet PHY design integration.
• Experience with clock tree synthesis optimization.
• Familiarity with PCIe, CXL, or Ethernet connectivity protocols.

THE ROLE

The Everpure Engineering Team builds the industry’s most innovative, high-performance, and highly available portfolio of products that are designed for the most demanding mission critical applications.  While we deliver a hardware storage array, over 90% of our engineering staff are software engineers. Our customers are the most important part of our business and they love FlashArray for its simplicity of management, the constant flow of new and exciting upgrades, and ability to live on the cutting edge of technology while never taking downtime, ever. These new innovations enable our customers to leverage the agility of the public cloud for both traditional IT and cloud-native applications.

WHAT YOU'LL DO

• Responsibilities include plan, lead, implement, debug HW design and qualification projects.
• Help debug testbeds and HW related escalation both internal and external
• Participation in all phases of the product development cycle including design, documentation, eDVT, FA and support for custom HW design
• Define, implement and automate HW validation and qualification tests
• Strong understanding of X86 architecture and proven design track record
• Solid understanding of Major Bus technology SAS/SATA, PCIe, UPI, Serial Busses (I2c, I3c, SPI, SVID, etc.)
• Solid understanding and ability to analyse high speed signals and comfortable with High Speed Oscilloscopes, bus analyzers (getting trace capture and perform analysis)
• Analysis and review of device and system-level power regulators, PWM selection & design, cooling and electrical (SI) functionality
• Improve design and qualification processes to enhance efficiency, consistency, and product robustness
• Setting up and running stress tests including industry standard tools : PTU, Mprime, Iometer, LinPack, etc.
• Qualification of CPU subsystems including DDR4/5 memory, PCIe cards (Fiber Channel, ISCSI, SAS, etc.), PCH chipsets, BMC, LOM, and peripherals
• Work cross-functionally with engineering, operations, Mfg. Test, and support to introduce new storage subsystems into production
• Perform failure and root cause analysis activities in support of system hardening efforts and customer escalations
• Provide guidance and mentoring to other team members

WHAT YOU BRING

• 8+ years in x86 and storage related HW development and qualification
• B.S. Electrical or Computer Engineering (M.S. is a plus)
• Experience working at enterprise data storage system companies or server companies preferred
• Strong knowledge of hardware design, x86 architectures and interfaces. Ability to qualify x86 hardware at the electrical, SI, protocol and functional levels
• Strong knowledge of selecting x86 subcomponents, NVMe drives, Power supplies ( AC & DC), and discrete power circuits
• Experience planning, implementing and automating HW qualification processes
• Strong experience with scripting languages (i.e. Python, BASH, etc) and test development
• Understand Verilog and CPLD design background
• Work with diagnostics engineers by providing direction and reviewing test plans to ensure proper coverage
• Detail oriented, analytical, process savvy, and customer focused yet flexible and adaptable to business needs
• Highly self-motivated with the ability to work autonomously in a fast-paced, technical development environment
• Experience working in and leading cross-functional teams
• High level of teamwork and collaboration skills
• Ability to operate in a fast-paced changing business environment
• Strong verbal and written communication skills
• We are primarily an in-office environment and therefore, you will be expected to work from the Santa Clara, CA office in compliance with Everpure’s policies, unless you are on PTO, or work travel, or other approved leave.

#LI-ONSITE

DRW is a diversified trading firm with over 3 decades of experience bringing sophisticated technology and exceptional people together to operate in markets around the world. We value autonomy and the ability to quickly pivot to capture opportunities, so we operate using our own capital and trading at our own risk.

Headquartered in Chicago with offices throughout the U.S., Canada, Europe, and Asia, we trade a variety of asset classes including Fixed Income, ETFs, Equities, FX, Commodities and Energy across all major global markets. We have also leveraged our expertise and technology to expand into three non-traditional strategies: real estate, venture capital and cryptoassets.

We operate with respect, curiosity and open minds. The people who thrive here share our belief that it’s not just what we do that matters–it's how we do it. DRW is a place of high expectations, integrity, innovation and a willingness to challenge consensus.

We are currently seeking a FPGA Engineer to join one of our trading teams. While DRW has been leveraging FPGA technology for a number of years, you will have the opportunity to build an FPGA application from scratch for an existing team. We’re seeking a candidate that has a strong understanding of software and hardware interaction. This person will participate in the full development lifecycle, including system and block level testing, of low latency high throughput FPGA design.

This role is for the Chicago office only.

Responsibilities: 

• Architect and implement new FPGA applications (synthesis, place & route, static timing analysis, documentation) from the ground up
• Research and evaluate a variety of cutting-edge FPGA hardware and technologies
• Propose creative solutions to overcome FPGA/hardware limitations
• Liaise directly with software and other design teams
• Conduct lab debugging and characterization of new hardware

Candidate Requirements: 

• Bachelor’s degree or higher, Computer/Electrical Engineering with 3+ years of experience within the field; (Master’s degree or higher also counts for experience)
• Solid Hardware Engineering experience, especially with FPGA
• Highly autonomous with a can-do attitude able to lead an FPGA based project from system requirements to production
• Strong capacity to quickly evaluate FPGA based project feasibility based on hardware limitation
• Strong skills in RTL logic design (Verilog) and verification; 2+ years of experience writing Verilog
• Experience in FPGA design flow including synthesis, place & route , static timing analysis is required
• Experience with the design of system-on-chip (SOC) architectures, memory & processor subsystems, networking, and peripheral interconnect is required
• Knowledge of the TCP/IP stack
• Strong working knowledge of either XILINX or ALTERA FPGA design flow
• Experience with functional verification utilizing high-level methodologies (e.g. System Verilog) is a plus.
• Excellent research and data gathering skills

The annual base salary range for this position is $150,000 to $250,000 depending on the candidate’s experience, qualifications, and relevant skill set. The position is also eligible for an annual discretionary bonus. In addition, DRW offers a comprehensive suite of employee benefits including group medical, pharmacy, dental and vision insurance, 401k (with discretionary employer match), short and long-term disability, life and AD&D insurance, health savings accounts, and flexible spending accounts.

For more information about DRW's processing activities and our use of job applicants' data, please view our Privacy Notice at https://drw.com/privacy-notice.

California residents, please review the California Privacy Notice for information about certain legal rights at https://drw.com/california-privacy-notice.

#LI-BL1

Position Overview 

We are seeking a Senior FPGA Verification Engineer with 4–8 years of experience to design, develop, and execute comprehensive verification strategies for complex FPGA designs. This role requires strong hands-on expertise in System Verilog and UVM, testbench architecture, and cross-functional collaboration with design and system teams. 

 Key Responsibilities: 

• Develop and maintain System Verilog/UVM-based verification environments for FPGA block-level and top-level designs  
• Create and execute verification plans, directed and constrained-random test scenarios, assertions, and functional coverage  
• Perform simulation-based verification of FPGA designs using industry-standard simulators  
• Drive debug and root-cause analysis of functional issues and work closely with FPGA RTL designers
• Integrate and maintain VIPs, scoreboards, checkers, and reference models  
• Support FPGA bring-up, validation, and debug activities on FPGA platforms and evaluation boards  
• Review FPGA RTL, verification code, and test plans to ensure quality and completeness  
• Mentor junior engineers and contribute to FPGA verification best practices
• Support regression runs, coverage closure, and release signoff 

Qualifications 

Education:  

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field 

Experience: 

4–8 years of hands-on experience in functional verification 

Preferred Qualifications:  

• Familiarity with cadence tools like Xcelium 
• Familiarity with Xilinx Vivado 
• Experience with hardware/software co-verification  
• Knowledge of high-speed interfaces (AXI, AXIStream, DDR, SPI)  

Soft Skills: 

• Strong analytical and debugging skills  
• Ability to work effectively in cross-functional teams  
• Excellent written and verbal communication skills  
• Self-driven with the ability to own verification tasks end-to-end  
• High attention to detail and commitment to quality 

Technology Stack: 

• Languages: System Verilog, Verilog, VHDL (working knowledge)  
• Verification Methodology: UVM  
• Simulation Tools: Xcelium, Questa, VCS  
• FPGA Tools: Xilinx Vivado  
• Debug Tools: SimVision  
• Scripting: Python, Tcl, Shell  
• Version Control: Git   

Physical Requirements 

• Ability to work in a standard office environment  
• Ability to use a computer for extended periods  
• Occasional lab work for FPGA bring-up and debug 

This job description may not be inclusive to the duties and responsibilities listed. Additional tasks may be assigned to the employee from time to time or the scope of the job may change as needed by business demands. 

Essential Duties & Responsibilities

• Collaborate with Solutions Architects and Algorithm Engineers to develop and optimize C++ applications for real-time operational mission data processing signal chains.
• Work with remote sensing data providers (e.g. EO/IR, hyper-spectral, etc.) to characterize data and tune signal processing chains to optimize for specific data/targets.
• Contribute to the development of a robust, repeatable, and adaptable signal processing architecture.
• Engineer solutions for low Size, Weight, and Power (SWaP) deployments such as Versal ACAP devices.
• Ensure all solutions are thoroughly designed, documented, and tested.
• Use and contribute to CI/CD pipelines to encode quality within the Software Development Life Cycle.
• Collaborate with team members and leads to achieve project milestones.
• Adhere to applicable corporate and DoD processes & standards to ensure quality, compliance, and security.

Required Skills & Experience 

• Secret clearance (ability to obtain Secret clearance, i.e. U.S. Citizenship required)
• 8+ years’ experience in high performance C++ applications software engineering within Linux environments
• Bachelor's degree in Computer Science, Computer Engineering, or a related field with equivalent experience
• Knowledge of embedded systems and hardware acceleration concepts
• Ability to document and communicate software designs
• Familiarity with version control systems such as Git
• Excellent problem-solving skills and attention to detail
• Ability to work independently and as part of a team
• Strong communication and collaboration skills
• A passion for learning and staying current with industry trends

Desired Skills & Experience 

• Experience with Xilinx/AMD Versal ACAP platforms or similar (highly desired)
• Experience with Vitis Unified Software Platform and Vivado Design Suite
• Familiarity with FPGA design and hardware description languages (VHDL/Verilog)
• Experience translating complex algorithms into production software solutions
• Experience with DoD/DoW projects
• Current US Secret security clearance
• Strong Continuous integration/Continuous delivery techniques (CI/CD)
• Experience in other programming languages such as Python, Java, or JavaScript
• Experience in AI assisted software development tools and techniques

Application Deadline:  July 13, 2026

#CJPost

#LI-onsite

The Role 

We are seeking a Mixed-Signal Behavioral Modeling Engineer to own the creation of behavioral modeling and drive mixed-signal verification methodology from the ground up. You will be part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the largest, most powerful, rapidly designed and rapidly manufactured satellites ever deployed in space. Your work will directly influence top-level integration and silicon tapeout success. This is a high-impact, technical role with significant ownership across modeling, methodology, verification, and cross-functional alignment with RF, analog, and digital teams.  

Responsibilities 

• Develop high-level behavioral models for analog and mixed-signal IP (ADCs, DACs, PLLs, LDOs, RF front-end blocks, biasing, amplifiers, etc.). 
• Create abstracted models using Verilog, Verilog-AMS, or SystemVerilog. 
• Develop regression infrastructure and mixed-signal testbenches enabling co-simulation (digital + analog). 
• Integrate AMS models into digital verification environments (UVM-based). 
• Define and build the mixed-signal verification methodology for top-level SoC and subsystem verification. 
• Support architectural exploration through early-phase modeling and system-level simulations.  
• Collaborate with analog/RF designers to capture real-world analog behaviors and map them into accurate behavioral abstractions. 
• Work with digital and verification teams to ensure seamless integration of AMS models. 
• Provide modeling and verification insights during architectural reviews, PDR/CDR, and silicon bring-up. 
• Act as technical leader and subject-matter expert.  

Required Qualifications  

• M.S. or Ph.D. in Electrical Engineering, Computer Engineering, or related field. 
• 2+ years of experience in analog/mixed-signal modeling and/or AMS verification. 
• Hands-on experience with SystemVerilog, Verilog-AMS, wreal/RNM, or equivalent modeling languages. 
• Strong understanding of analog/mixed-signal circuits (PLLs, LDOs, ADC/DACs, RF/IF paths, clocking, amplifiers). 
• Experience with mixed-signal co-simulation environments (Cadence AMS Designer, Synopsys VCS AMS, or similar). 

Preferred Qualifications  

• Experience building AMS verification methodologies from scratch. 
• Familiarity with UVM-based verification and digital design flows. 
• Knowledge of signal processing theory, RF system modeling, or communication systems. 
• Experience with MATLAB/Simulink, Python modeling, or SystemC AMS for high-level architectural modeling. 
• Experience working in cross-functional, geographically distributed teams.  

Compensation and Benefits:

• Base salary range for this role is $130,000 – $180,000 + equity in the company
• Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
• Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks

The Role 

We are seeking a Senior Mixed-Signal Behavioral Modeling Engineer to own the creation of behavioral modeling and drive mixed-signal verification methodology from the ground up. You will be part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the largest, most powerful, rapidly designed and rapidly manufactured satellites ever deployed in space. Your work will directly influence top-level integration and silicon tapeout success. This is a high-impact, technical role with significant ownership across modeling, methodology, verification, and cross-functional alignment with RF, analog, and digital teams.   

Responsibilities 

• Develop high-level behavioral models for analog and mixed-signal IP (ADCs, DACs, PLLs, LDOs, RF front-end blocks, biasing, amplifiers, etc.). 
• Create abstracted models using Verilog, Verilog-AMS, or SystemVerilog. 
• Develop regression infrastructure and mixed-signal testbenches enabling co-simulation (digital + analog). 
• Integrate AMS models into digital verification environments (UVM-based). 
• Define and build the mixed-signal verification methodology for top-level SoC and subsystem verification. 
• Support architectural exploration through early-phase modeling and system-level simulations.  
• Collaborate with analog/RF designers to capture real-world analog behaviors and map them into accurate behavioral abstractions. 
• Work with digital and verification teams to ensure seamless integration of AMS models. 
• Provide modeling and verification insights during architectural reviews, PDR/CDR, and silicon bring-up. 
• Act as technical leader and subject-matter expert.  

Required Qualifications  

• M.S. or Ph.D. in Electrical Engineering, Computer Engineering, or related field. 
• 5+ years of experience in analog/mixed-signal modeling and/or AMS verification. 
• Hands-on experience with SystemVerilog, Verilog-AMS, wreal/RNM, or equivalent modeling languages. 
• Strong understanding of analog/mixed-signal circuits (PLLs, LDOs, ADC/DACs, RF/IF paths, clocking, amplifiers). 
• Experience with mixed-signal co-simulation environments (Cadence AMS Designer, Synopsys VCS AMS, or similar). 

Preferred Qualifications  

• Experience building AMS verification methodologies from scratch. 
• Familiarity with UVM-based verification and digital design flows. 
• Knowledge of signal processing theory, RF system modeling, or communication systems. 
• Experience with MATLAB/Simulink, Python modeling, or SystemC AMS for high-level architectural modeling. 
• Experience working in cross-functional, geographically distributed teams.  

Compensation and Benefits:

• Base salary range for this role is $160,000 – $230,000 + equity in the company
• Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
• Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks

ABOUT THE TEAM

The Electronic Warfare (EW) team is responsible for developing high-reliability radios, embedded processing, and power systems for software defined radio platforms. Working across hardware, software, and mission autonomy, the team delivers EW-critical electronics, PCB assemblies, and FPGA-based processing architectures that enable Anduril's next-generation autonomous electronic warfare platforms to operate in complex and contested environments. EW Electrical Engineers drive end-to-end development, from system architecture and circuit design to verification, integration, and test, ensuring scalable, mission-ready solutions that meet the performance, reliability, and survivability demands of the U.S. Military and modern EW warfare.

ABOUT THE JOB

We are looking for a Senior FPGA Engineer to join our rapidly growing team in Costa Mesa, CA. In this role, you will be responsible for the end-to-end design and verification of projects on the Xilinx SOC/FPGA platforms and helping to establish robust design processes. This will require expertise in SystemVerilog, FPGA, and Xilinx. If you are someone who has supported rapid software defined radio development, then this role is for you.

WHAT YOU'LL DO

• Work with software, and electrical, engineers to bring up state of the art boards for software defined radios.
• Integrate, and test, VHDL DSP Modules into larger system.
• Design custom, and optimized, HDL for software defined radios.
• Develop drivers for custom RF component boards (PLLs, mixed signal front ends, etc)

REQUIRED QUALIFICATIONS

• Strong experience with DSP implementation for embedded devices and/or software defined radios.
• Experience leading a team of FPGA engineers in the development of new custom PCB's and custom FPGA modules
• Experience with bring-up of high speed digital interfaces (PCIE,JESD,etc).
• HDL design experience using VHDL or Verilog.
• Experience with Linux development environment and tools (e.g. Git, gcc, etc)
• Eligible to obtain and maintain an active U.S. Secret security clearance

PREFERRED QUALIFICATIONS

• Experience with embedded Linux driver development.
• Experience with Linux development environment and tools (e.g. Git, gcc, etc)
• Exposure to Wireless comms or Radar systems
• Experience with RF test equipment (Spec An, Sig Gens, Oscilloscope, etc)
• Experience with Xilinx AI Engines or NVDIA CUDA

ABOUT THE TEAM

Anduril’s Electronic Warfare (EW) team is seeking experienced generalist embedded software engineers to build out the software ecosystem supporting a next-generation electronic warfare platform. As an Embedded software engineer, you’ll develop high-performance implementations of numerical algorithms, collaborate with digital systems engineers to enable maximum-performance interfaces between next-gen RF hardware and software, work with DSP and RFML engineers to rapidly deploy bleeding-edge capabilities to our customers, and collaborate with the wider software organization to deliver seamless integration of electronic warfare products with the Anduril Lattice system-of-systems suite. You will apply state-of-the-art software construction techniques to ensure the timely delivery of correct mission-critical code.

WHAT YOU'LL DO

• Work with digital systems engineers and systems programmers to develop high-performance hardware/software interfaces.
• Develop and maintain infrastructure and tools that enable DSP and RFML engineers to rapidly deploy algorithms and models to our assets.
• Develop high-performance implementations of numerical algorithms for generating, manipulating, and visualizing RF data.
• Develop correct, high-reliability software for controlling our electronic warfare assets, seamlessly integrated with the Anduril Lattice ecosystem.
• Utilize infrastructure providing deterministic builds and configuration management for deployment, guaranteeing software traceability and minimizing the maintenance burden of our products.

REQUIRED QUALIFICATIONS

• 7+ years professional experience in software engineering
• Experience (professional or in the setting of an open source community) working with typed functional programming languages (Haskell or Rust)
• Experience with software-defined digital radio systems
• Eligible to obtain and maintain an active U.S. Top Secret SCI security clearance

PREFERRED QUALIFICATIONS

• Experience with MATLAB, especially C code generation.
• Experience with Linux kernel module development
• Experience with FPGA development (Verilog, VHDL, etc.), especially Xilinx devices and tools.
• Experience with graphics programming (OpenGL, DirectX, Vulkan, etc.)
• Experience with Nix/NixOS