We are looking for a talented engineer to join our CPU design team to define and implement CPU system RTL. You’ll work to combine multiple cores, multiple clusters of cores, fabrics and subsystem components together, collaborating with DV, PD, architecture and performance teams to deliver a functional, timing, and power-converged design.

This role is hybrid, based out of Bengaluru, India.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• An experienced micro-architect who thrives in building CPU systems (multiple cores, multiple clusters of cores and subsystem components) from scratch.
• Skilled in RTL coding (Verilog/VHDL) and familiar with industry-standard tools for simulation, synthesis, and power analysis.
• Proficient in debugging RTL/logic across multiple design hierarchies and pre/post-silicon environments.
• Background in microarchitecture definition, design specification, and performance-driven trade-off analysis.

What We Need

• 10+ years of industry experience with strong CPU systems RTL and microarchitecture background.
• Collaborate closely with DV, PD, architecture and performance engineers to meet functional, timing, and power goals.
• Use innovative techniques to optimize power, performance, and area while driving RTL experiments and evaluating results.
• Partner with validation and test teams to ensure robust pre-silicon and post-silicon execution.
• Enhance RTL design environment, tools, and methodologies to improve development efficiency.

What You Will Learn

• End-to-end exposure to CPU design from microarchitecture through timing and power convergence.
• How to design and optimize a custom RISC-V CPU system from first principles.
• Integration of open-source and industry-standard tools to improve RTL flows and results.
• Work in a deeply technical, highly collaborative team solving cutting-edge CPU design challenges.

Role Overview

We are seeking a Senior Staff DFT Engineer to join a rapidly growing DFT design team focused on next-generation AI accelerator SoCs. In this role, you will define, architect, and implement current and future DFT/DFX solutions, supporting advanced SoC designs that leverage innovative memory-centric compute and heterogeneous chiplet architectures.

This is a highly hands-on role requiring both deep technical execution and high-level planning, working across design, verification, product, and test teams to ensure robust manufacturability and silicon bring-up.

Location:

Hybrid, working onsite at our Bengaluru, Karnataka, headquarters 3-5 days per week.

Key Responsibilities

• Drive DFT partitioning strategies for ATPG, including hierarchical and scalable approaches.

• Implement ATPG compression and serialization, and perform RTL scan insertion with associated design rule fixes.

• Own Memory BIST (MBIST) solutions, including memory repair and in-system test (IST), from implementation through verification and silicon debug.

• Support boundary scan and define DFT mode constraints for IPs, providing timing feedback to STA teams.

• Generate and integrate DFT RTL, ensuring quality through RTL-level checks (e.g., linting and DFT rule verification).

• Apply and support IEEE 1149.1, IEEE 1500, and IEEE 1687 standards.

• Execute and verify ATPG (SAF, TDF) and MBIST using unit-delay and min/max timing simulations.

• Perform detailed ATPG coverage analysis and drive coverage closure.

• Collaborate with product and test engineering teams to deliver manufacturing test patterns for ATE.

• Develop diagnostic tools and flows for ATPG, MBIST, and silicon bring-up on ATE.

• Work hands-on with industry-standard DFT tools, contributing from low-level implementation through architectural planning.

Minimum Qualifications

• BE/ME (or equivalent) in Electrical Engineering, Computer Engineering, Computer Science, or a related field.

• 7+ years of experience in DFT, including scan test and MBIST.

• Proficiency with HDLs such as Verilog, SystemVerilog, or VHDL.

• Experience with scripting or programming languages (e.g., Python, Perl, TCL, C).

• Strong ability to collaborate effectively in cross-functional and diverse teams.

• Experience producing clear, detailed technical documentation.