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Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.
We are looking for a talented engineer to join our CPU design team to define and implement CPU system RTL. You’ll work to combine multiple cores, multiple clusters of cores, fabrics and subsystem components together, collaborating with DV, PD, architecture and performance teams to deliver a functional, timing, and power-converged design.
This role is hybrid, based out of Bengaluru, India.
We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.
What You Will Learn
This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.
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Role Overview
We are seeking a Senior Staff DFT Engineer to join a rapidly growing DFT design team focused on next-generation AI accelerator SoCs. In this role, you will define, architect, and implement current and future DFT/DFX solutions, supporting advanced SoC designs that leverage innovative memory-centric compute and heterogeneous chiplet architectures.
This is a highly hands-on role requiring both deep technical execution and high-level planning, working across design, verification, product, and test teams to ensure robust manufacturability and silicon bring-up.
Location:
Hybrid, working onsite at our Bengaluru, Karnataka, headquarters 3-5 days per week.
Drive DFT partitioning strategies for ATPG, including hierarchical and scalable approaches.
Implement ATPG compression and serialization, and perform RTL scan insertion with associated design rule fixes.
Own Memory BIST (MBIST) solutions, including memory repair and in-system test (IST), from implementation through verification and silicon debug.
Support boundary scan and define DFT mode constraints for IPs, providing timing feedback to STA teams.
Generate and integrate DFT RTL, ensuring quality through RTL-level checks (e.g., linting and DFT rule verification).
Apply and support IEEE 1149.1, IEEE 1500, and IEEE 1687 standards.
Execute and verify ATPG (SAF, TDF) and MBIST using unit-delay and min/max timing simulations.
Perform detailed ATPG coverage analysis and drive coverage closure.
Collaborate with product and test engineering teams to deliver manufacturing test patterns for ATE.
Develop diagnostic tools and flows for ATPG, MBIST, and silicon bring-up on ATE.
Work hands-on with industry-standard DFT tools, contributing from low-level implementation through architectural planning.
BE/ME (or equivalent) in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
7+ years of experience in DFT, including scan test and MBIST.
Proficiency with HDLs such as Verilog, SystemVerilog, or VHDL.
Experience with scripting or programming languages (e.g., Python, Perl, TCL, C).
Strong ability to collaborate effectively in cross-functional and diverse teams.
Experience producing clear, detailed technical documentation.
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