Who We Are:

Inversion builds advanced reentry systems to deliver next-generation capabilities from space.
 
Our mission is to make Earth radically more accessible by turning Low-Earth Orbit into an on-demand logistics domain. We see space not as a destination, but as a platform — one that unlocks unprecedented speed and global reach.
 
Our spacecraft are designed to deliver payloads anywhere on Earth in under an hour, operating through extreme reentry conditions and landing with high precision. These systems open the door to new ways of testing, delivering, and operating at hypersonic speeds.
 
Inherently dual-use, our technology is built to meet urgent national security needs while laying the groundwork for future commercial applications. Backed by leading investors including Y Combinator, Spark Capital, and Lockheed Martin Ventures, and working with partners such as the U.S. Space Force and NASA, Inversion is pushing the boundaries of what’s possible in space-based defense and logistics.

What You'll Do:

As a Senior FPGA Engineer, you will lead the design, implementation, integration, and verification of FPGA-based architectures supporting Inversion’s next-generation re-entry vehicles. You will work within the Avionics team to develop high-performance digital systems for RF, communications, telemetry, and real-time signal processing applications across both flight and ground hardware.

This role is ideal for an experienced engineer who can translate system requirements and signal processing concepts into robust FPGA implementations, while driving hardware bring-up, verification, and end-to-end integration across multidisciplinary teams. You will help develop critical hardware and systems for cutting-edge maneuverable reentry vehicles - advancing one of the most capable reentry vehicle platforms ever developed.

You will be a key member of the Avionics team, reporting directly to the Director of Engineering, Avionics. Our engineers are responsible for the complete lifecycle of the hardware they create, including design, development, integration, verification, and troubleshooting.

Essential Duties and Responsibilities:

• Design, implement, and verify FPGA-based processing architectures for RF, DSP, telemetry, and real-time embedded applications.
• Translate signal processing, communications, and control algorithms into efficient FPGA implementations.
• Develop interfaces between FPGAs, ADCs/DACs, processors, RF front ends, memories, and other digital subsystems.
• Own FPGA development flow including architecture definition, RTL design, simulation, synthesis, place-and-route, timing closure, and hardware validation.
• Optimize FPGA designs for latency, throughput, resource utilization, power, and reliability.
• Develop reusable IP, testbenches, and verification infrastructure to support current and future platform development.
• Support board bring-up, integration, debug, and troubleshooting in laboratory and field test environments.
• Partner closely with DSP, RF, software, embedded, and electrical engineers to ensure end-to-end system performance.
• Support hardware/software co-design and system-level integration across flight and ground systems.
• Document architecture, design decisions, verification results, and integration procedures.

Required Qualifications:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Physics, or a related technical field.
• Typically 5+ years of professional experience in FPGA design and development for high-speed digital, communications, or signal processing systems.
• Ability to obtain and maintain a U.S. security clearance up to Top Secret.
• Strong experience with VHDL, Verilog, and/or SystemVerilog.
• Familiarity with Xilinx, AMD, Intel/Altera, or equivalent FPGA toolchains and development environments.
• Experience developing FPGA-based architectures for high-speed, real-time signal processing systems.
• Experience with digital communications and common interface protocols.
• Strong understanding of high-speed digital interfaces such as JESD204, PCIe, Ethernet, SPI, UART, and related protocols.
• Experience with simulation, synthesis, timing analysis, timing closure, resource optimization, and hardware debugging.
• Familiarity with MATLAB/Simulink, Python, C, or C++ for algorithm handoff, modeling, verification, or automation.
• Understanding of hardware/software integration and board bring-up.
• Hands-on experience with lab equipment such as logic analyzers, oscilloscopes, and spectrum analyzers.
• Ability to communicate technical architecture and design tradeoffs clearly across multidisciplinary teams.

Desired Qualifications:

• Experience with RF, telemetry, SDR, or communications systems.
• Experience implementing digital downconversion/upconversion, filtering, channelization, packetization, synchronization, or other DSP functions in FPGA fabric.
• Familiarity with processor/FPGA co-design and embedded Linux or bare-metal control interfaces.
• Experience with high-speed ADC/DAC interfaces and board-level integration in mixed-signal systems.
• Familiarity with verification methodologies, constrained-random simulation, hardware-in-the-loop testing, or automated regression infrastructure.
• Experience supporting qualification, environmental test, and deployment of hardware in aerospace, defense, or other high-reliability applications.
• Experience in startup environments or small, highly collaborative engineering teams.

Additionally: Staff-Level Consideration – We are also open to considering exceptional candidates for a Staff FPGA Engineer level. Staff-level candidates should possess all of the qualifications listed above, in addition to 8+ years of professional experience with demonstrated technical leadership in FPGA architecture, implementation, and system integration. The Staff-level compensation range is $161,000 - $221,000.

Our office headquarters is located in Playa Vista, CA. This position requires in office presence.

_{The California annual base salary for this role is currently $137,000 - $193,000.  Pay Grades are determined by role, level, location, and alignment with market data.  Individual pay will be determined on a case-by-case basis and may vary based on the following considerations: interviews and an assessment of several factors that are unique to each candidate, job-related skills, relevant education and experience, certifications, abilities of the candidate and internal equity.}