About this Senior Hardware Validation Engineer (IC5) role at Centific
About Centific
Centific is a frontier AI data foundry that curates diverse, high-quality data, using our purpose-built technology platforms to empower the Magnificent Seven and our enterprise clients with safe, scalable AI deployment. Our team includes more than 150 PhDs and data scientists, along with more than 4,000 AI practitioners and engineers. We harness the power of an integrated solution ecosystem—comprising industry-leading partnerships and 1.8 million vertical domain experts in more than 230 markets—to create contextual, multilingual, pre-trained datasets; fine-tuned, industry-specific LLMs; and RAG pipelines supported by vector databases. Our zero-distance innovation™ solutions for GenAI can reduce GenAI costs by up to 80% and bring solutions to market 50% faster.
Our mission is to bridge the gap between AI creators and industry leaders by bringing best practices in GenAI to unicorn innovators and enterprise customers. We aim to help these organizations unlock significant business value by deploying GenAI at scale, helping to ensure they stay at the forefront of technological advancement and maintain a competitive edge in their respective markets.
About Job
Responsibilities
● Own electrical and system verification for assigned subsystems: develop high-level test
plans, define test priorities and coverage, and set entry/exit criteria per build (Proto, EVT, DVT, PVT, MP).
● Take operational and technical ownership of verification activities at CM and vendor labs
ensure adherence to measurement techniques, setup integrity, and quality of documentation.
● Execute and oversee bring-up, characterization, and debug of prototype hardware across power, signal integrity, memory/storage, sensors, thermal, and system coexistence domains.
● Drive failures to root cause and classify them as product, test, environment, config, or
handling issues; file high-quality bugs with repro steps, build/config IDs, artifacts, and gate impact.
● Capture complete metadata for every test run (unit SNs, OS build, FW version, tool build, chamber ID, ambient conditions) and maintain traceability to requirements.
● Serve as the communication bridge between engineers in the US and verification teams in-region; represent verification status in daily triage, bug syncs, and build readiness reviews.
● Partner with EE design, FW, thermal, mechanical, and TPM counterparts to close verification gaps and influence design for testability.
● Improve verification capability over time — test procedures, reporting, and automation of
repetitive measurements.
● Mentor junior and contingent worker verification engineers in region.
● Domestic and regional travel as needed (up to ~30%).
