Job Summary

We are seeking a CAD Engineer specializing in Digital Verification to build, enhance, and support scalable verification infrastructure, methodologies, and EDA automation flows for ASIC/SoC development.

The role focuses on enabling verification teams with robust regression systems, automation frameworks, and advanced methodologies (UVM, coverage, Continuous Integration flows) to improve productivity, debug efficiency, and time-to-tapeout.

Digital Verification CAD Support & Methodology Enablement

• Act as the primary support interface for Design & Verification (DV) teams to troubleshoot issues in simulation, regression, coverage, and debug flows
• Collaborate with DV teams to identify bottlenecks and provide practical solutions or workarounds
• Support adoption of modern verification techniques (coverage-driven, formal, emulation) through guidance and issue resolution
• Deploy, integrate, and maintain CAD tools, scripts, and environments supporting digital verification flows
• Provide day-to-day support for EDA tools (VCS, Xcelium, Verdi, vManager, etc.) and resolve tool/flow-related issues
• Work closely with EDA vendors (Cadence, Synopsys, Siemens) to track, debug, and escalate tool issues, and support tool evaluations and rollouts
• Support and maintain regression and CI/CD systems, ensuring stable execution and timely issue resolution
• Monitor and optimize infrastructure usage (compute farms, LSF environments) to ensure efficient job execution and resource utilization
• Analyze DV flow issues and performance bottlenecks, and provide improvements or recommendations for optimization
• Partner with DV, RTL design, and system teams to resolve cross-functional issues impacting verification flows
• Provide methodology guidance, user support, and training to verification engineers on tools and flows
• Maintain and contribute to documentation, best practices, and support guidelines for verification flows

Required Qualifications

• Bachelor’s / master’s degree in Electronics Engineering
• 8–12 years of experience in Digital Verification / CAD / Engineering Support-related roles
• Strong understanding of digital verification flow (simulation, regression, coverage, debug)
• Hands-on experience with System Verilog and UVM (for debugging/support perspective)
• Proficiency in scripting/programming (Python, Tcl, Perl, or similar)
• Experience in Linux-based environments
• Experience with EDA tools (VCS, Xcelium, Verdi, vManager, etc.)
• Exposure to regression environments, CI/CD systems, and compute farm usage
• Familiarity with AI/ML-based DV tools (e.g., Cadence Verisium AI) is a plus
• Basic understanding of SoC/ASIC architecture and RTL design concepts

Required Interpersonal Skills

• Strong communication skills with the ability to interact effectively across teams
• Proven ability to collaborate with design, verification, IT and infrastructure teams
• Experience working in multi-cultural global environments and coordinating with globally distributed teams

Nice-to-Have

• Exposure to AI-assisted verification workflows / LLM-based tools and AI Agents development.
• Experience with cloud-based or distributed regression environments
• Interest in automating repetitive support workflows across DV flows using scripting or AI-based approaches
• Experience as CAD Application Engineer in EDA vendor company

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