As a Sr. Staff/Staff Digital Design Engineer, you will be working with a team of design engineers to develop novel SoC products for connectivity and communication. You will also be a key contributor to product definition and resulting detailed device performance and functional requirements specifications. In addition to delivering high quality digital solutions, the team supports other disciplines with work product such as Verilog stimulus files, test benches for device bring up/characterization, test vectors for product manufacturing.

Key Responsibilities

• Contribute to SoC architecture development for high-performance low-power IoT devices
• Employ skills in SystemVerilog, Python, Tcl, UPF to bring designs from concept through architecture to silicon and, finally, high-volume production
• Work cross-functionally with Systems/RF/software/firmware/verification/validation/operations teams
• Support schedule and resource planning to deliver products to market on time
• Help to define digital/system design and implementation methodologies and test strategies and flows

Job Requirements

• Theoretical and practical knowledge of SoC architectures employing embedded processors
• Familiarity with common bus architectures like AXI/AHB/APB/OBI
• Deep RTL design knowledge (SystemVerilog)
• Experience with multi-clock and multi-power domain systems and strategies to control and minimize power consumption
• Understanding of timing constraints, static timing analysis and timing closure
• Experience with Arm TrustZone, device lifecycle states, Secure Boot, and PSA Certified Level 2+ security.
• MS/PhD EE/CS preferred 

Desirable Skills

• You have an engineering mindset, and you believe that communication is key to growing a team stronger
• Able to work effectively with incomplete or changing requirements