Job Details:

Job Description:

Altera is seeking an experienced Physical Design Manager to lead a high-performing team responsible for delivering production-quality physical implementation for advanced semiconductor designs. This role combines technical leadership, people management, cross-functional execution, and ownership of predictable, high-quality tapeout results.

The ideal candidate brings deep expertise across the physical design flow, a strong track record managing complex SoC or ASIC programs, and the ability to build an inclusive, accountable engineering culture.

What you will do

• Lead, mentor, and grow a team of physical design engineers in Bangalore.
• Own physical implementation planning and execution from netlist through signoff and tapeout.
• Drive floorplanning, power planning, placement, clock-tree synthesis, routing, optimization, extraction, timing closure, physical verification, and signoff activities.
• Establish technical direction, project priorities, execution plans, and quality standards for the team.
• Partner closely with RTL design, microarchitecture, DFT, STA, CAD, verification, packaging, and product engineering teams.
• Identify physical design risks early and lead mitigation plans across schedule, power, performance, area, and manufacturability.
• Review and improve design methodologies, automation, flows, tools, and engineering practices.
• Ensure effective use of metrics, reviews, documentation, and lessons learned to improve predictability and execution quality.
• Contribute to staffing plans, capability development, performance management, and succession planning.
• Communicate technical status, trade-offs, risks, and recommendations clearly to engineering leadership.

Qualifications:

• Bachelor’s or master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.
• 12+ years of experience in ASIC or SoC physical design, with significant experience leading teams or major project areas.
• Strong hands-on understanding of the complete physical design flow from synthesis handoff through signoff.
• Experience with floorplanning, power distribution, placement, CTS, routing, timing closure, signal integrity, IR drop, electromigration, physical verification, and design-for-manufacturability considerations.
• Demonstrated experience delivering complex designs to tapeout in advanced process technologies.
• Strong knowledge of timing constraints, multi-voltage or low-power design, ECO implementation, and signoff methodologies.
• Experience collaborating across geographically distributed, cross-functional engineering teams.
• Strong problem-solving, planning, prioritization, communication, and people-leadership skills.

Preferred qualifications

• Experience with high-performance, high-volume, networking, compute, FPGA, or other complex SoC designs.
• Experience managing multiple projects, blocks, or design programs concurrently.
• Familiarity with industry-standard implementation and signoff tools, including tools from leading EDA vendors.
• Experience developing automation using Tcl, Python, Perl, or similar scripting languages.
• Experience defining physical design methodologies, flows, dashboards, and productivity improvements.
• Track record of hiring, developing, and retaining strong engineering teams.
• Knowledge of advanced-node challenges such as congestion, variability, multicorner-multimode closure, and restrictive design rules.

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