We are looking for a Senior Mixed-Signal/Analog/IO Circuit Design Engineer – someone who is excited to join a growing group of diverse individuals responsible for handling challenge high-speed memory interface designs.

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can pursue, and that matter to the world. This is our life’s work, to amplify human creativity and intelligence.

What you'll be doing:

• Mixed-Signal/Analog circuit design for High Speed Memory I/O Interfaces
• Solve challenge of circuit designs in deep submicron CMOS FinFET processes
• Take designs through productization and be involved in all stages of development
• Work with multi-functional teams to optimize the designs

What we need to see:

• Advanced High-Speed Design Expertise: 5+ years of proven experience in high-speed memory (LPDDR, DDR, GDDR, HBM) or SerDes design, underpinned by a BSEE or MSEE and a deep understanding of system-level timing budgets and specifications.
• FinFET Circuit Mastery: In-depth technical command of deep submicron CMOS FinFET processes, with the ability to navigate complex circuit design challenges and implementation nuances.
• Reliability & Physical Integrity: Comprehensive knowledge of device reliability, ESD, and Latch-Up requirements, including the ability to supervise layout development to ensure strict adherence to these critical rules.
• Full-Flow Tool Proficiency: Expert-level command of Cadence custom design environments and industry-standard simulators (Hspice, XA, FineSim, Spectre), with a working knowledge of Verilog, Nanotime, or Matlab.
• Silicon-to-System Perspective: Ability to bridge the gap between die and system, offering insights into package substrate design, board-level constraints, and Power Delivery Network (PDN) analysis.
• Collaborative Leadership: A proactive teammate with strong interpersonal skills, capable of mentoring junior engineers and performing hands-on validation using high-end lab test and measurement equipment.

We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation.