At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

This position involves:

• Interfacing with customers regarding digital reference flow requirements, including
  • Synthesis
  • Floorplanning
  • Clock tree synthesis
  • Power planning
  • Place and route
  • Timing closure
  • Sign-off
• Capturing reference flow requirements, scoping effort on reference flow development
• Creating baseline flows to be used by customers as starting point for digital implementation
• Using baseline flow to implement test cases for process certification and validation
• Using implementation testcases for Tempus and Voltus sign-off
• Creating documentation explaining the theory and use behind reference flow steps and commands
• PPA optimization

Position requires:

• Bachelor’s degree with at least 12-15 years of design/EDA experience or Master’s degree with at least 10 years of experience. Master’s degree preferred.
• Strong knowledge in Digital Design Flows, Static Timing Analysis and EMIR is required
• Prior experience with ASIC digital implementation flows and EDA tools is required; Experience with advanced FinFet nodes (7nm and below) required.  Experience with GAA technologies (2nm and below) preferred.
• Good programming knowledge in Unix, Shell scripting, perl and importantly TCL
• Strong customer-facing communication and problem-solving skills
• Strong personal drive for continuous learning and expanding professional skill sets
• Excellent verbal and written communication skills

Familiar with EDA tool operation, setup and debug:

• Digital: Genus, Innovus, Tempus, Voltus, etc

We’re doing work that matters. Help us solve what others can’t.