The Hardware team at Hudson River Trading (HRT) creates high performance compute engines using FPGA and ASIC technologies to drive low latency trading decisions on global markets. We build custom solutions across the spectrum of speed and smarts: from bespoke circuits to world-class machine learning accelerators. 

FPGAs and ASICs are critical pieces of our technology stack. We are looking for talented hardware developers to architect and design complex systems on a highly collaborative global team. In this role, you'll identify efficient ways to perform on-the-fly transformations of market data and implement models with complex data structures in RTL. You’ll work with FPGA, ASIC, or both technologies as a member of our integrated team. No previous financial  experience is necessary!

Responsibilities

• Contribute to a highly collaborative team, working closely with others to deliver hardware solutions
• Describe and communicate hardware designs at a high level (the interface), low level (step-by-step algorithm/circuit), or anywhere in between
• Analyze and fix problems quickly
• Continuously learn, tinker, and explore new technologies to deepen your hardware expertise
• Challenge your teammates and raise the bar for the work the team produces

Qualifications

• Currently pursuing a Bachelor's, Masters, or PhD in Computer Science, Computer Engineering, Electrical Engineering, or a related discipline, with eligibility for full-time employment in 2027
• Proficiency in SystemVerilog
• Deep knowledge of FPGA internals and/or ASIC 
• Excellent digital logic design, optimization, debugging and problem solving skills
• Thorough understanding of computer architecture and vendor tool suites
• Familiarity with C++ and/or Python 
• Comfortable working in a Linux environment
• Previous internship experience in digital logic design
• Expertise in networking protocols, CPU design, physical design, or machine learning accelerators is a big plus

Hardware Design and Verification at HRT

HRT hires for both design and verification roles. There is often overlap in skills, and both teams work together very closely. Design engineers typically have training in computer architecture and digital logic design, and they are primarily focused on creating hardware in SystemVerilog. Verification engineers typically have training in both digital logic and software engineering, and are primarily focused on building complex modeling and testing environments in Python and C++. If you are interested, you can view our Design Verification (DV) Engineer - 2027 Grads posting here.

We do not allow multiple applications. Please apply to the ONE role you are most interested in and we will consider you for all open positions when reviewing your application.

The estimated base salary range for this position is 300,000 USD per year (or local equivalent). The base pay offered may vary depending on multiple individualized factors, including location, job-related knowledge, skills, and experience. This role will also be eligible for discretionary performance-based bonuses and a competitive benefits package.