Über diese FPGA IP Design and Verification Engineer Stelle bei Altera
Job Details:
Job Description:
Performs functional logic verification of an FPGA to ensure design will meet specification requirements. Develops FPGA verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications. Executes verification plans and defines and runs system simulation models to verify the FPGA design, analyze power and timing, and uncover bugs. Replicates, root causes, and debugs issues in the pre-silicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates with FPGA architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features. May also collaborate with systems and software engineers to support integration testing of the FPGA. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology. Documents, reviews, and executes the verification strategy plan on different methodologies/techniques (e.g., gate-level-simulation strategy, power patterns/aware simulations) used to enable feature coverage as per the microarchitecture specifications.
Qualifications:
7+ years of experience in Semiconductor IP Design verification.
Familiarity with HDL languages (VHDL, Verilog, SystemVerilog).
Experience or knowledge in scripting languages such as Tcl, Perl, or Python.
Prior experience or exposure to FPGA tools (Quartus or Vivado) would be advantageous.
Strong willingness to learn new skills and technologies.
Ability to work collaboratively within a team environment.
Good communication skills and ability to clearly present project details and outcomes.
