Tenstorrent is looking  for a STA methodology engineer who owns timing across advanced-node, high-performance, low-power designs, bringing deep expertise with PrimeTime, noise/crosstalk/OCV analysis, and strong scripting skills. They will lead the development and optimization of end-to-end STA methodologies and flows, drive data- and ML-assisted timing automation, and partner closely with logic, physical design, DFT, and EDA vendors to solve complex timing challenges across multiple IPs and products. 

This role is hybrid, based out of Santa Clara, CA, Austin, TX, or Fort Collins, CO.

We welcome candidates at various experience levels. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting

Who you are

• An experienced Static Timing Analysis (STA) / timing methodology engineer with a BS/M in Electrical or Computer Engineering (or equivalent experience) 5+ years in industry, focused on high-performance and low-power designs at advanced technology nodes. As well as a deep knowledge of STA tools and techniques, including noise, crosstalk, and OCV analysis.
• You are fluent with PrimeTime and related signoff tools (e.g., PT-SI, PTPX, PT-ECO) and have extensive hands-on experience driving signoff correlation, advanced static timing analysis, and signoff closure.
• You are strong at debugging timing constraints, resolving timing correlation issues, and developing effective timing closure strategies.
• You write robust, production-quality scripts in Tcl, Python, and/or Perl and are comfortable building and maintaining CAD utilities and flow components.

What we need

• A senior methodology owner to lead cross-functional efforts to solve complex timing challenges across multiple IPs, projects, and technology nodes. Experience developing and enhancing STA methodologies across the full RTL-to-GDS flow, including: Early timing estimation and timing feasibility checks. Timing optimization techniques in synthesis and place-and-route. Timing signoff methodologies and criteria. Post-route timing ECO strategies and execution.
• A technical leader to architect, optimize, and maintain production STA flows using industry-standard EDA tools, continuously improving PPA (Power, Performance, Area) and runtime efficiency.
• A methodology engineer who can explore and deploy data-driven and ML-assisted techniques to: Improve STA automation. Predict and prioritize timing risk. Guide optimization strategies across blocks and full-chip. Design, implement, and maintain scalable CAD utilities and STA flow components that improve PPA, robustness, and team productivity.
• A methodology owner who continuously refines workflows and introduces new technologies to ensure robust, PPA-optimized timing solutions across all product lines.

What you will learn

• How to scale STA methodologies across a diverse portfolio of IP and SoC programs, balancing aggressive performance targets with strict power and area constraints.
• Best practices for integrating data-driven and ML-assisted approaches into timing flows to improve automation, predictability, and decision-making.
• How to influence tool roadmaps by partnering closely with leading EDA vendors on advanced-node timing, noise, and variability challenges.
• How to operate within and help shape a rapidly evolving startup design environment, including tradeoffs between quick solutions and long-term methodology investments.
• Deeper cross-functional insight into how logic design, physical design, and DFT interact with STA methodology, and how to build flows that serve all of these stakeholders effectively.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This position requires access to technology that requires a U.S. export license for persons whose most recent country of citizenship or permanent residence is a U.S. EAR Country Groups D:1, E1, or E2 country. 

Tenstorrent is seeking an Physical Design Engineer to lead  cross-functional efforts to solve complex physical design challenges and develop end-to-end RTL-to-GDS methodologies across advanced nodes, with a strong focus on PPA and runtime improvements. The engineer will architect, integrate, and deploy AI/ML-driven solutions into production physical design flows, creating custom CAD tools and partnering with internal teams and EDA vendors to drive next-generation, ML-enabled capabilities. 

This role is hybrid, based out of Santa Clara, CA or Austin, TX or Fort Collins, CO.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who you are

• BS in Electrical or Computer Engineering (or equivalent experience) with 5+ years in Physical Design CAD methodology at advanced nodes.
• Proven track record improving PPA and/or runtime on high-performance, low-power taped-out designs.
• Hands-on with industry-standard EDA tools (e.g., Fusion Compiler) across synthesis, P&R, STA, signoff, and hierarchical flows.
• Strong Python/Tcl and data skills, with interest or experience in ML frameworks (PyTorch, TensorFlow), and the ability to drive complex projects independently.

What we need

• Lead and contribute to cross-functional efforts solving complex physical design challenges across IPs, projects, and advanced technology nodes.
• Develop and enhance RTL-to-GDS methodologies, including floorplanning, synthesis, P&R, STA, signoff, and assembly.
• Architect and deploy AI/ML-driven solutions in production flows to improve engineering efficiency, turnaround time, and QoR.
• Optimize EDA tools and custom CAD flows using data-driven and ML-based techniques, in close collaboration with verification, extraction, timing, DFT, and EDA vendors.

What you will learn

• How to scale AI/ML-driven methodologies across diverse products and advanced technology nodes in real production flows.
• New ways to blend classical EDA algorithms with modern ML techniques to push PPA and runtime limits.
• Best practices for deploying, validating, and monitoring ML models in production CAD environments.
• How to influence next-generation ML-enabled EDA tools and collaborate deeply with cross-functional teams (PV, extraction, timing, DFT).

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This position requires access to technology that requires a U.S. export license for persons whose most recent country of citizenship or permanent residence is a U.S. EAR Country Groups D:1, E1, or E2 country. 

Tenstorrent is seeking an exceptional Senior-level Physical Design Engineer to drive top-level implementation of our complex AI and CPU System-on-Chip designs. You'll orchestrate cross-disciplinary collaboration, implementing sophisticated floorplans, power grids, and clock networks while ensuring design closure at the chip level. If you excel at managing the complexity of full-chip physical design and want to deliver next-generation AI hardware, we need your expertise.

This role is hybrid, based out of Santa Clara, CA or Austin, TX or Fort Collins, CO.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A seasoned physical design engineer who thrives on complex, full-chip implementation challenges.
• Expert at collaborating across disciplines, working effectively with architecture, RTL, and packaging teams.
• Passionate about optimizing chip-level implementations for power, performance, and area.
• Detail-oriented professional who drives design closure while maintaining quality and meeting aggressive schedules.

What We Need

• 8+ years of top-level SOC physical design experience on complex, multi-million gate designs.
• Deep expertise in hierarchical floorplanning, fabric implementation, power grid design, and global clock distribution.
• Proven track record with bump planning, RDL implementation, and multi-voltage domain designs.
• Mastery of timing closure, EM/IR analysis, and physical verification at the chip level.

What You Will Learn

• How to implement cutting-edge AI accelerators and high-performance CPUs at the SOC level.
• Advanced techniques for chiplet integration and next-generation packaging co-design.
• Strategies for optimizing massive designs with complex power domains and clock architectures.
• Methods for driving successful chip-level closure through effective cross-functional collaboration.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This position requires access to technology that requires a U.S. export license for persons whose most recent country of citizenship or permanent residence is a U.S. EAR Country Groups D:1, E1, or E2 country. 

Tenstorrent is seeking a SoC Physical Design Verification Engineer to drive full-chip signoff and ensure manufacturable, high-quality silicon across advanced technology nodes. You’ll lead physical verification closure (DRC, LVS, ERC, etc.), debug issues using standard industry PV tools, and collaborate across RTL, PD, CAD, and packaging teams to achieve successful tapeouts. If you thrive in a fast-paced environment and enjoy solving complex challenges in cutting-edge silicon, we’d love to hear from you.

This role is hybrid, based out of Santa Clara, CA or Austin, TX or Fort Collins, CO.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A seasoned engineer with a strong background in CPU/IP/SoC physical verification and tapeout closure.
• A hands-on problem solver who excels at debugging and driving signoff through complex verification flows.
• A collaborative team player who works effectively across RTL, PD, CAD, and foundry interfaces.
• A mentor and technical leader passionate about building efficient, manufacturable silicon.
  
  

What We Need

• BS/MS in Electrical/Electronics Engineering (or related) with 7–14 years of hands-on CPU/IP/SoC physical verification experience.
• Proven expertise in DRC, LVS, ERC, PERC, Antenna, and DFM verification using industry-standard tools and flows (Calibre, ICV, Pegasus, FC, Innovus, etc.).
• Strong background in ESD planning, padring integration, bump/RDL strategies, and reliability analysis (IR drop, EM), with solid understanding of advanced nodes (7nm, 5nm, 3nm) and FinFET design challenges.
• Scripting proficiency in Python and TCL for automation and flow optimization.

What You Will Learn

• Advanced physical verification methodologies and flow optimization for next-generation SoCs.
• Integration and verification strategies for full-chip signoff across advanced process technologies.
• Cross-functional collaboration across design, CAD, and foundry teams to ensure flawless tapeouts.
• Leadership and mentoring opportunities in building scalable PV methodologies and automation.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This position requires access to technology that requires a U.S. export license for persons whose most recent country of citizenship or permanent residence is a U.S. EAR Country Groups D:1, E1, or E2 country. 

Tenstorrent is seeking talented Physical Design Engineers to implement high-performance blocks for our industry-leading CPU and AI/ML architectures. You'll own the complete implementation flow from synthesis to tapeout, working alongside world-class engineers to push the boundaries of performance, power, and area. If you're passionate about crafting silicon that powers the future of AI computing and thrive on solving complex design challenges, we want you on our team.

This role is hybrid, based out of Austin, TX, Santa Clara, CA or Fort Collins, CO. 

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A hands-on engineer with deep expertise in SOC/ASIC physical design and a track record of successful tapeouts.
• Passionate about optimizing PPA through innovative implementation techniques and close RTL collaboration.
• Strong problem solver who excels at debugging complex issues across design hierarchies.
• Collaborative team player who thrives in fast-paced, technically challenging environments.

We’re looking for a Timing Engineer to join our silicon team. In this role, you’ll drive static timing analysis and closure for complex, high-performance designs. You’ll collaborate closely with logic, DFT, and physical design teams to debug constraints, optimize paths, and ensure our chips meet performance targets across corners and modes.

This role is hybrid, based out of Austin, TX, Fort Collins, CO, or Santa Clara, CA.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Experienced in STA and passionate about enabling silicon to meet aggressive performance goals.
• Analytical and detail-oriented, with a strong understanding of timing paths, constraints, and optimization strategies.
• A collaborative team player who works well across logic, DFT, and physical design boundaries.
• Resourceful and self-driven, capable of developing scripts and methodologies that improve timing closure workflows.

What We Need

• 7+ years of industry experience and a proven record of successful tapeouts.
• Deep knowledge of STA tools and techniques, including noise, crosstalk, and OCV analysis.
• Proficiency in writing and debugging SDC constraints, creating ECOs, and developing closure strategies.
• Strong scripting skills in Python, Perl, and TCL to support automation and flow development.
• Familiarity with SPICE modeling and worst-case corner analysis.

What You Will Learn

• How to close timing on Tenstorrent’s high-performance RISC-V CPUs and AI SoCs.
• Advanced STA methodologies tailored to modern sub-micron process technologies.
• How to collaborate with world-class engineers across RTL, DFT, and physical design teams.
• How to influence chip performance through timing methodology innovation and automation.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is seeking talented Physical Design Engineers to implement high-performance partitions for an industry-leading AI SOC. You'll own the complete implementation flow from synthesis to tapeout, working alongside world-class engineers to push the boundaries of performance, power, and area. If you're passionate about crafting silicon that powers the future of AI computing and thrive on solving complex design challenges, we want you on our team.

This role is hybrid, based out of Austin,TX or Santa Clara, CA or Fort Collins, CO.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who you are

• Experienced with synthesis and place-and-route flows, especially using Synopsys Design Compiler / Fusion Compiler and IC Compiler II.
• Comfortable in a small, cross-functional physical design team, owning a block or subsystem and partnering on tapeout milestones with clear communication and accountability.
• Ideally bring extra depth in areas such as UPF/multi-voltage power domains, SoC interface IP integration (e.g. I3C, UART), signoff breadth (DRC/LVS, EM/IR, LEC/Formality), multi-clock/CDC-aware implementation, PLL/DLL integration, and DFT-aware physical implementation (OCC/MBIST).

What we need

• Execute synthesis, PNR, and STA for assigned partitions of a complex AI SoC.
• Help close EM/IR, ensure UPF power intent is consistent with implementation, and drive LEC and physical verification signoff for your partitions in coordination with methodology owners.
• Work closely with architects, RTL designers, and DFT engineers to resolve implementation and signoff issues across your blocks.

What you will learn

• How to implement and close AI SoC partitions end-to-end, including power intent, timing, and physical signoff in a modern Synopsys-based flow.
• Deeper expertise across signoff domains: EM/IR, DRC/LVS, logical equivalence (LEC/Formality), and CDC-aware implementation on meaningful production blocks.
• Practical integration of analog/mixed-signal macros (PLL/DLL), DFT features (OCC/MBIST), and SoC interface IP within advanced physical design flows and collaborative tapeout environments.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This position requires access to technology that requires a U.S. export license for persons whose most recent country of citizenship or permanent residence is a U.S. EAR Country Groups D:1, E1, or E2 country.