Role Overview 

Astera Labs is seeking a dynamic HR Director to lead our EMEA human resources team, overseeing operations across our Israel Design Centers in Haifa and Tel Aviv, as well as our R&D center in Aachen, Germany. This is a critical leadership role that will shape the people strategy for our rapidly expanding EMEA presence as we continue to scale our world-class engineering teams building the connectivity solutions powering the AI revolution. 

As HR Director, you will operate as a true business leader who happens to specialize in people strategy—not a support function, but a driver of business outcomes. You will partner with EMEA site leadership to accelerate product development timelines, improve engineering productivity, and build the organizational capabilities required to win in the AI infrastructure market. Equally critical, you will serve as the connective tissue between EMEA and our global corporate teams, ensuring seamless alignment on programs, policies, and priorities while representing EMEA needs in global discussions. This role demands a commercially-minded leader who connects every HR initiative to measurable business impact, whether that's reducing time-to-hire for critical roles, improving retention of top performers, or building leadership bench strength to support our expansion. You will build and scale a high-performing HR team while partnering closely with our global HR function to deliver results. 

Key Responsibilities 

Business Partnership & Strategic Impact 

• Drive EMEA people strategy that directly accelerates business outcomes including product delivery, engineering velocity, and market expansion 

• Operate as a member of the EMEA leadership team, contributing to business decisions beyond traditional HR scope 

• Translate business challenges into people solutions—identify where talent, organizational design, or capability gaps are limiting growth and take action 

• Establish and track HR metrics tied to business performance, holding the function accountable for measurable results 

Global Alignment & Collaboration 

• Partner closely with global corporate teams including HR, Finance, Legal, and IT to ensure EMEA alignment on company-wide initiatives and programs 

• Serve as the primary HR liaison between EMEA sites and headquarters, advocating for regional needs while maintaining global consistency 

• Collaborate on the design and rollout of global HR programs, adapting implementation for local markets while preserving intent 

• Build strong cross-functional relationships across geographies to enable effective decision-making and execution 

Talent Strategy & Competitive Advantage 

• Build a world-class semiconductor talent pipeline that gives Astera Labs a competitive edge in EMEA markets 

• Partner with engineering leadership to forecast talent needs and proactively address skill gaps before they impact delivery 

• Design compensation and retention strategies that protect critical talent and reduce regrettable attrition 

• Drive workforce planning that aligns headcount investments with product roadmap priorities 

Team Building & Scaling 

• Build, develop, and lead a high-performing HR team across Israel and Germany oriented around delivering business results 

• Effectively manage and develop remote teams across international borders, fostering collaboration and accountability across multiple sites 

• Drive scalable HR processes and infrastructure to support rapid growth without sacrificing speed or quality 

• Create clear accountability and performance expectations within the HR function 

HR Operations & Compliance 

• Ensure execution excellence in HR operations including employee relations, compensation, benefits, and performance management across EMEA 

• Maintain compliance with local labor laws and regulations in Israel and Germany 

• Continuously improve operational efficiency to free up capacity for strategic priorities 

Culture & Performance 

• Champion a high-performance culture that attracts ambitious talent and drives accountability 

• Implement initiatives that improve employee engagement and productivity, not engagement for its own sake 

• Foster an environment where top performers thrive and underperformance is addressed swiftly 

Basic Qualifications 

• Bachelor's degree in Human Resources, Business Administration, or related field 

• 10+ years of progressive HR experience with significant time in HR leadership roles 

• 3+ years of experience managing and developing HR teams 

• Demonstrated ability to manage remote teams across international borders and multiple time zones 

• Experience in the semiconductor or high-tech hardware industry 

• Strong knowledge of Israel labor law and HR practices; familiarity with German employment regulations 

• Proven track record of scaling HR functions in high-growth environments 

• Demonstrated business acumen with a history of tying HR initiatives to measurable business outcomes 

Preferred Qualifications 

• Master's degree in Human Resources, MBA, or related advanced degree 

• Experience supporting engineering-heavy organizations in fast-paced, product-driven companies 

• Multi-country HR management experience across EMEA 

• Experience partnering with US-headquartered companies and navigating global/regional dynamics 

• Hebrew language fluency; German language skills a plus 

• Experience with M&A integration or establishing new site operations 

• HR certification (SHRM-SCP, CIPD, or equivalent) 

Role Overview

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Design Verification Student to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, designing complex solutions that sit at the heart of our most ambitious connectivity projects.

As a Design Verification Student, you will be at the forefront of quality, learning how to ensure that the chips powering the world's largest AI clusters are bug-free and robust.
This isn't just about running tests - it’s an opportunity to learn advanced verification methodologies (UVM/SystemVerilog) alongside world-class engineers. You will support the development of sophisticated testbenches and help verify high-performance digital blocks that sit at the heart of AI infrastructure.

Key Responsibilities

• Assist in building and maintaining System Verilog/UVM-based testbenches, including monitors, checkers, and functional coverage models
• Run simulations, analyze failures, and work with the design team to debug and resolve RTL issues
• Help define and implement functional coverage and assertions to ensure all "corner cases" of the design are tested
• Utilize and improve scripting (Python/Tcl) to streamline verification flows and result reporting
• Partner with Design Engineers to understand block specifications and ensure the verification plan matches the design intent

Basic Qualifications

• Pursuing a Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical field
• Ability to work at least 2 days a week at our Haifa/Tel Aviv center
• Strong understanding of Digital Logic and at least one programming language (C/C++ or Python)
• Basic familiarity with Verilog or SystemVerilog from academic projects or lab work
• A natural curiosity for "breaking things" and finding bugs, with a strong attention to detail
• Fluent in Hebrew and English with the ability to work effectively in a team environment

Preferred Qualifications

• Completed courses in VLSI, Digital Systems, or Computer Architecture
• Proficiency in Python, Perl, or Tcl
• Any prior exposure to UVM/OVM or constrained-random verification is a major plus
• Basic understanding of protocols like PCIe, Ethernet, or DDR

Role Overview

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary ASIC Design Student to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, designing complex solutions that sit at the heart of our most ambitious connectivity projects.

As an ASIC Design Student, you won't just build chips—you will be part of a team defining the next generation of AI infrastructure main components. The complex digital blocks under your micro-architecture and implementation responsibilities will power the world's largest AI clusters. You will own the journey from high-level definition through RTL implementation and backend support, transforming complex logic challenges into elegant, high-performance hardware. If you thrive on solving unnamed challenges in deep-submicron processes and want to shape the digital design foundation for AI infrastructure connectivity, this is your opportunity.

Key Responsibilities

• Assist in the development of micro-architecture, RTL coding, and debugging for complex digital blocks
• Utilize industry-leading EDA tools (Lint, CDC, Synthesis) to ensure designs are robust and power-efficient
• Work closely with the verification team to run simulations, analyze results, and ensure design quality
• Interact with Architecture and Backend teams to understand the full chip development lifecycle
• Help leverage AI-based automation tools to optimize engineering workflows

Basic Qualifications

• Pursuing a Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical field
• Strong academic record with a focus on Digital Logic Design and VLSI
• Ability to work at least 2 days per week at our Haifa/Tel Aviv center
• Solid understanding of logic design principles and hardware description languages (Verilog or SystemVerilog)
• A "can-do" attitude with a passion for solving complex technical challenges
• Fluent in Hebrew and English with the ability to work effectively in a team environment

Preferred Qualifications

• Hands-on experience with FPGA projects or university-level tape-out projects
• Proficiency in Python, Perl, or Bash for automation
• Completed courses in Computer Architecture, Synthesis, or Static Timing Analysis (STA)
• Basic familiarity with high-speed protocols like PCIe or DDR

Role Overview

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Physical Design Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the backend execution and methodologies for chips that power the world's largest AI clusters.

As a Physical Design Engineer, you will be a key architect of our silicon's physical reality. You won't just execute a flow—you will help establish our local execution culture and technical standards, owning the transformation of complex logic into high-performance silicon. You will drive the physical implementation journey from synthesis through signoff, ensuring our connectivity solutions meet the extreme performance, power, and area targets required for next-generation AI infrastructure. If you thrive on solving complex challenges in deep-submicron processes and want to shape the backend methodology for AI infrastructure connectivity, this is your opportunity.

Key Responsibilities

• Physical Implementation & Execution

  • Be part of the founding Backend team in Israel, playing a critical role in establishing local execution culture and technical standards
  • Take full responsibility for physical implementation journey including Synthesis, Floorplanning, Place & Route, and Clock-Tree Synthesis (CTS)
  • Own macro-level implementation with deep hands-on experience in floorplanning and complex routing

• Signoff & Design Integrity

  • Drive final stages of design integrity, owning Timing signoff (STA), Physical Verification (DRC/LVS), and Reliability analysis (EMIR)
  • Ensure first-pass silicon success through rigorous signoff flows and analysis
  • Apply Logic Equivalence Checking (LEC) and other verification techniques to guarantee design correctness

• Methodology Development & Cross-Functional Collaboration

  • Participate in defining and refining Backend methodologies with autonomy to improve workflows and tool automation
  • Work closely with Architecture, Design, and DFT teams to navigate challenges of advanced process nodes and high-speed connectivity
  • Leverage scripting and automation to make engineering environment faster and more robust

Basic Qualifications

• Bachelor's degree in Electrical Engineering or related technical field
• 3+ years of hands-on experience in Physical Design at semiconductor companies
• Proven expertise in the full RTL2GDS flow with deep hands-on experience in macro-level implementation, floorplanning, and complex routing
• Experience working with advanced process technologies (7nm and below)
• Solid experience with signoff tools and flows including STA, Logic Equivalence Checking (LEC), DRC, and EMIR analysis
• Proficiency in TCL or Python scripting to drive EDA tool flows and automate repetitive tasks

Preferred Qualifications

• Experience with full-chip level implementation and integration
• Knowledge of Power and Noise analysis (SI/PI) to optimize high-performance silicon
• Familiarity with Design-for-Test (DFT) requirements and their impact on physical layout
• Experience with industry-standard EDA tools (Synopsys Fusion Compiler/ICC2, Cadence Innovus)
• Background in high-speed interface designs or connectivity protocols