Job Details:

Job Description:

Altera is seeking a Manager, Static Timing Analysis (STA) to lead a team responsible for timing closure and signoff of advanced FPGA designs! This role will play a critical part in ensuring high-performance, power-efficient silicon by driving timing methodology, analysis, and optimization across complex designs.

The ideal candidate brings deep STA expertise, strong leadership experience, and a proven ability to collaborate across design, physical implementation, and architecture teams.

Key Responsibilities

• Team Leadership:
  Build, manage, and mentor a high-performing STA team; drive technical excellence and career development.

• Timing Closure & Signoff:
  Own end-to-end STA for FPGA designs, including constraint development, timing analysis, and timing signoff.

• Methodology Development:
  Define and implement robust STA methodologies, flows, and best practices to improve timing convergence and design quality.

• Cross-Functional Collaboration:
  Partner with RTL design, synthesis, physical design (P&R), and architecture teams to identify and resolve timing issues.

• Performance Optimization:
  Drive improvements in performance, power, and area (PPA) through timing-driven design and optimization techniques.

• Tool & Flow Expertise:
  Leverage industry-standard EDA tools to analyze timing, debug violations, and automate flows where applicable.

• Project Execution:
  Ensure on-time delivery of timing closure milestones across multiple programs.

Qualifications:

Required Qualifications

• Experience:
  10+ years of experience in Static Timing Analysis (STA) for ASIC or FPGA designs.
   

• Leadership:
  3+ years of experience managing or leading engineering teams.
   

• Technical Expertise:

  • Deep knowledge of STA concepts (setup/hold, clock domain crossing, timing constraints)

  • Strong experience with timing signoff tools (e.g., PrimeTime or equivalent)

  • Understanding of synthesis, place & route, and full chip implementation flows
     

• Design Flow Knowledge:
  Solid understanding of:

  • RTL design (Verilog/SystemVerilog)

  • Timing closure methodologies

  • Low-power and high-performance design challenges
     

• Debug & Analysis:
  Strong skills in root-cause analysis of timing violations and driving closure across complex designs.
   

• Education:
  Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.

Preferred Qualifications

• Experience with FPGA architecture and design flows

• Familiarity with advanced nodes and high-speed designs

• Exposure to scripting/automation (e.g., Tcl, Python) for timing analysis

• Experience working in large-scale, distributed engineering environments

Why Join Altera

• Lead critical STA efforts for next-generation FPGA platforms

• Work on cutting-edge technology in AI, data center, and networking applications

• Collaborate with world-class engineering teams across silicon design and implementation

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