Job Summary: 

We are seeking a highly motivated and detail-oriented Analog Mixed-Signal CAD Engineer to join our design automation team. In this role, you will develop, maintain, and support CAD tools and design flows for analog and mixed-signal IC design. You will work closely with circuit designers, layout engineers, and EDA vendors to ensure efficient and robust design environments. 

Key Responsibilities: 

• Develop and maintain analog/mixed-signal design flows using industry-standard EDA tools (Cadence Virtuoso, Spectre, etc.). 
• Automate design tasks using scripting languages (e.g., Python, SKILL, Tcl, Perl). 
• Support schematic, layout, simulation, and verification environments. 
• Collaborate with design teams to understand requirements and improve design productivity. 
• Integrate and validate PDKs (Process Design Kits) and technology files. 
• Provide documentation, training, and support for CAD tools and flows. 
• Interface with EDA vendors to evaluate and deploy new tools and features. 
• Monitor and resolve CAD tool issues, ensuring high availability and performance. 

Required Qualifications: 

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field. 
• 3+ years of experience in analog/mixed-signal CAD or EDA tool development. 
• Strong knowledge of analog/mixed-signal IC design methodologies. 
• Proficiency in scripting languages such as SKILL, Python, Tcl, or Perl. 
• Experience with Cadence Virtuoso, Spectre, and AMS simulation environments. 
• Familiarity with PDK integration and technology file management. 
• Excellent problem-solving, communication, and teamwork skills. 

Preferred Qualifications: 

• Experience with digital-on-top (DoT) or mixed-signal verification flows. 
• Knowledge of version control systems (e.g., Git, Perforce). 
• Familiarity with Unix/Linux environments and shell scripting. 
• Exposure to advanced process nodes (e.g., 7nm, 5nm). 

Job Summary: We are seeking a talented Senior Design Verification Engineer to join our team. The ideal candidate will play a key role in verifying the functionality and performance of our digital and mixed-signal designs. You will work closely with the design and development teams to create and execute comprehensive verification plans, ensuring the robustness and reliability of our products.

Key Responsibilities:

• Develop and implement test plans and testbenches for verification of sub-blocks in high-speed Ethernet, UALink, PCIE PHY (64b/66b Encoder/Decoder, FEC encoder/decoder, DSP, FFE, DFE, MLSD).
• Identify, document, and debug functional issues found during verification, collaborating with design engineers for resolution.
• Develop and apply coverage models to ensure thorough validation of the design.
• Work closely with architects, designers, and software teams to comprehend the design architecture and contribute to high-level verification strategy.
• Stay up-to-date with industry best practices and emerging tools for design verification.

Qualifications:

• Bachelor’s in Electrical Engineering, Computer Engineering, or a related field.
• 2+ year of experience in DV.
• Strong proficiency in verification languages such as System Verilog, UVM (Universal Verification Methodology).
• Experience with simulation tools (e.g., Cadence Xcelium, Synopsys VCS, or Mentor Graphics QuestaSim).
• Familiarity with scripting languages such as Python, Perl, or Shell scripting for automation purposes.
• In-depth understanding of digital design principles, verification methodologies, and industry-standard protocols.
• Excellent analytical, debugging, and problem-solving skills.
• Strong teamwork and communication abilities.

Pay and Benefits

• Competitive salary.
• Performance bonus each year.
• Flexible working time.
• Health check each year.
• Insurance for engineer and family.
• Lunch Allowance.
• Company trips.