We are seeking an experienced Analog/Mixed-Signal (AMS) Circuit Design Engineer to join our high-performance design team working on next-generation transceiver IPs targeting the TSMC 5/3nm technology node. In this role, you will design high-speed analog and mixed-signal circuits used in multi-gigabit transceivers, collaborating with layout, verification, and system teams to ensure robust performance, power efficiency, and successful silicon validation at advanced process nodes.

Key Responsibilities

• Design critical AMS blocks such as PLLs, CDRs, LDOs, bias generators, and ADC/DAC components for wireline transceivers. 
• Perform transistor-level design, simulation, and optimization for performance, power, and area across process, voltage, and temperature (PVT) corners.
• Work closely with layout engineers to guide floorplanning, matching-sensitive layout, and parasitic-aware design. • Perform design verification using pre- and post-layout simulations (transient, AC, noise, Monte Carlo, corner sweep).
• Ensure robust operation under variation, jitter, power supply noise, and crosstalk conditions.
• Create and maintain design documentation, design reviews, and specifications
• Collaborate with system architects, digital design, and firmware teams to define and optimize mixed-signal interface behavior.
• Support silicon bring-up, lab measurement correlation, and debug of design issues.
• Use industry-standard tools (e.g., Virtuoso, Spectre, HSPICE, ADE, MATLAB, Python) for design and analysis.

Required Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Microelectronics, or related field.
• 5+ years of experience in analog/mixed-signal circuit design in deep-submicron or FinFET technologies.
• Strong experience with:
  • Transistor-level design and simulation in advanced nodes (≤ 5nm).
  • Designing analog blocks for high-speed transceivers (e.g., clocking, bias, analog front ends).
  • SPICE simulation tools and AMS verification environments.
  • Deep understanding of noise, jitter, linearity, bandwidth, gain, impedance matching, and power trade-offs.
• Familiarity with layout interaction and parasitic-aware circuit optimization.
• Solid debugging, problem-solving, and documentation skills.

Benefits

• Competitive salary
• 13th month salary
• Performance bonus each year
• Flexible working time
• Health check each year
• Insurance for engineer and family
• Lunch Allowance
• Company trips.