We are looking for a person ready to take up the challenge of working in a high-profile project where we design and integrate multiple chiplets into a System-in-package, in collaboration with external stakeholders. You will work with Tenstorrent worldwide experts and leaders in the USA, Japan and other countries, and help us make our IP even better. This is a CPU tech-leadership role focused on driving power analysis and projections for the development of CPU chiplet with an emphasis on power analysis. The role involves defining CPUrail planning while collaborating closely with SoC and Board teams. Responsibilities include optimizing the system PDN for Block rails, and managing the power vector plan for comprehensive coverage of Chip level. The position requires driving power analysis on RTL and Netlist using tools like Joules and PrimePower, working with RTL design, synthesis, and physical design teams to measure and optimize power, and evaluating new power optimization techniques at various design stages. Additionally, the role involves tabulating metrics results for analysis comparison and workingwith post-silicon teams to correlate projections with silicon power measurements.

This role is hybrid, based out of Tokyo, Japan

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Extensive experience in power analysis and optimization for complex ASICs (typically 10+ years of ASIC or related design experience).
• Comfortable working across RTL, synthesis, and physical design stages, including low‑power implementation techniques and ECO‑based timing closure.
• Proficient with power analysis tools (e.g., Joules, PrimePower) and scripting (Tcl plus at least one of Python or similar).
• Strong analytical and problem‑solving skills, with clear written and verbal communication when collaborating across SoC, board, and post‑silicon teams.
• Nice to have: familiarity with UPF/CPF low‑power intent, Verilog/SystemVerilog, CPU micro‑architecture and its power challenges, and basic thermal analysis.

What We Need

• Own power analysis and projections for the CPU chiplet, with emphasis on defining and tracking power metrics throughout the design cycle.
• Define and maintain the power vector plan for comprehensive chiplet‑level and chip‑level coverage.
• Drive power analysis on RTL and netlist using tools such as Joules and PrimePower, partnering with RTL design, synthesis, and physical design teams to measure and optimize power.
• Evaluate and propose new power optimization techniques at RTL, synthesis, and physical design stages, and implement changes via timing ECO and flow updates.
• Tabulate and compare power metrics and reports across design iterations, and work with post‑silicon teams to correlate projections with silicon measurements.

What You Will Learn

• How to define and execute a power strategy for a 2nm CPU chiplet within a multi‑chiplet system‑in‑package, including rail planning and system‑level PDN optimization.
• Best practices for end‑to‑end power closure, from RTL through netlist and physical design, in collaboration with global RTL, SoC, and board teams.
• How to correlate pre‑silicon power models with real silicon behavior and feed lessons learned back into next‑generation CPU and SiP architectures.
• How Tenstorrent integrates CPU chiplets, AI accelerators, and board‑level power delivery into a cohesive high‑performance platform.

We are looking for a senior physical design engineer to join Tenstorrent’s AIDC Yayoi project, driving chiplet-level and chip-top physical implementation of high-performance CPU-based SoCs in a cutting-edge system-in-package environment.

This role is hybrid, based out of Tokyo, Japan.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• You have a Bachelor’s, Master’s, or PhD in electrical engineering, computer engineering, or computer science, with extensive experience (typically 10+ years) in SoC/ASIC/GPU/CPU physical design on taped-out designs.
• You are highly skilled with industry-standard tools (e.g., Synopsys/Cadence) and physical verification, and comfortable scripting in TCL and at least one other language (e.g., Python).
• You are a strong collaborator who can guide and mentor junior engineers, communicate clearly with global stakeholders, and navigate complex technical trade-offs to drive designs to closure.
• You are organized and data-driven, able to build implementation plans, monitor PPA and schedule metrics, communicate resource needs, and proactively identify and manage risks.

What We Need

• Lead chiplet and chip-top implementation for a high-profile, multi-chiplet System-in-Package project and place and route for high-speed CPU core designs in advanced nodes (5nm and below).
• Own chip-top floorplanning and integration: BUS and fabric planning, bump and IO placement, and hierarchical top/bottom floorplanning to achieve timing and PPA closure at chip level.
• Drive full physical verification and convergence, electrical rules, DRC/LVS, noise, and electromigration checks
• Take ownership of chip-level synthesis, BUS and bump planning, SoC floorplanning, and chip-top PV and EMIR, while providing technical leadership and mentoring to junior team members.

What You Will Learn

• Deep expertise in system-in-package design and multi-chiplet integration, working hands-on project with complex chip-top interfaces and constraints.
• Best practices for high-frequency, advanced-node (5nm and below) CPU design implementation, including cutting-edge timing closure, EMIR, and sign-off methodologies.
• How to operate in a highly collaborative global environment, partnering daily with Tenstorrent experts and leaders across Japan, the USA, and other regions, as well as external stakeholders.
• Advanced strategies for scaling physical design flows, improving reproducibility of convergence, and optimizing project PPA and schedule across multiple tapeouts.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This position requires access to technology that requires a U.S. export license for persons whose most recent country of citizenship or permanent residence is a U.S. EAR Country Groups D:1, E1, or E2 country. 

We are looking for a Staff Digital Design Engineer to help define, build, and optimize high-performance chiplet based SoC architectures. This role is ideal for engineers who thrive at the intersection of microarchitecture, RTL implementation, and performance and power aware design.

This role is hybrid, based out of Tokyo.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A digital design expert with a deep understanding of computer architecture and IP microarchitecture.
• Skilled in RTL development (Verilog/VHDL) and familiar with full ASIC flows.
• Comfortable optimizing for power, performance, and area (PPA) under aggressive design goals.
• A naturally collaborative and technical engineer — you thrive in spec definition, peer reviews, and team-wide planning.
• Strong synthesis and timing closure awareness to support backend teams.

What We Need

• Proficiency in hardware description languages (HDLs) such as Verilog, SystemVerilog or VHDL.
• Architecture and RTL implementation of Tenstorrent’s custom IP blocks and SoC components.
• Performance-aware design decisions for compute, interconnect, or memory-heavy blocks.
• Occasional contributions to validation using emulation, FPGA prototyping, or UVM flows.
• Prior experience in on-chip fabric and interconnect designs and basic understanding of RISC-V Architecture and debug experience is preferable.

What You Will Learn

• How cutting-edge chiplet design are built, from spec to silicon.
• What it takes to collaborate with teams designing novel processor and memory architectures.
• How cross-functional workflows come together across design, DV, physical, and firmware teams.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This position requires access to technology that requires a U.S. export license for persons whose most recent country of citizenship or permanent residence is a U.S. EAR Country Groups D:1, E1, or E2 country.