#LI-VP1

Job Summary: We are seeking a talented Senior Design Verification Engineer to join our team. The ideal candidate will play a key role in verifying the functionality and performance of our digital and mixed-signal designs. You will work closely with the design and development teams to create and execute comprehensive verification plans, ensuring the robustness and reliability of our products.

Key Responsibilities:

• Develop and implement test plans and testbenches for verification of sub-blocks in high-speed Ethernet, UALink, PCIE PHY (64b/66b Encoder/Decoder, FEC encoder/decoder, DSP, FFE, DFE, MLSD).
• Identify, document, and debug functional issues found during verification, collaborating with design engineers for resolution.
• Develop and apply coverage models to ensure thorough validation of the design.
• Work closely with architects, designers, and software teams to comprehend the design architecture and contribute to high-level verification strategy.
• Stay up-to-date with industry best practices and emerging tools for design verification.

Qualifications:

• Bachelor’s in Electrical Engineering, Computer Engineering, or a related field.
• 2+ year of experience in DV.
• Strong proficiency in verification languages such as System Verilog, UVM (Universal Verification Methodology).
• Experience with simulation tools (e.g., Cadence Xcelium, Synopsys VCS, or Mentor Graphics QuestaSim).
• Familiarity with scripting languages such as Python, Perl, or Shell scripting for automation purposes.
• In-depth understanding of digital design principles, verification methodologies, and industry-standard protocols.
• Excellent analytical, debugging, and problem-solving skills.
• Strong teamwork and communication abilities.

Pay and Benefits

• Competitive salary.
• Performance bonus each year.
• Flexible working time.
• Health check each year.
• Insurance for engineer and family.
• Lunch Allowance.
• Company trips.