Technologists at WorldQuant research, design, code, test and deploy firmwide platforms and tooling while working collaboratively with researchers. Our environment is relaxed yet intellectually driven. We seek people who think in code and are motivated by being around like-minded people.

What We Offer:

• Competitive and attractive compensation package with clear career road-map – where you feel challenged everyday
• We offer a strong culture of learning and development: training courses, library, speakers, share and learn events
• Learn from who sits next to you! Working in WQ you are surrounded by smart and talented people
• Premium Health Insurance and Employee Assistance Program
• Generous time-off policy, re-creation sabbatical leave (based on tenure), Trade Union benefits for staff and family
• Team building activities every month: Local engagement events – Employee clubs: football, ping-pong, badminton, yoga, running, PS5, movies, etc.
• Annual company trip and occasional global conferences – opportunity to travel and connect with our global teams
• Happy-hour with tea break, snacks and meals every day in the office!
  
  #LI-QM1

Job Summary: We are seeking a talented Senior Design Verification Engineer to join our team. The ideal candidate will play a key role in verifying the functionality and performance of our digital and mixed-signal designs. You will work closely with the design and development teams to create and execute comprehensive verification plans, ensuring the robustness and reliability of our products.

Key Responsibilities:

• Develop and implement test plans and testbenches for verification of sub-blocks in high-speed Ethernet, UALink, PCIE PHY (64b/66b Encoder/Decoder, FEC encoder/decoder, DSP, FFE, DFE, MLSD).
• Identify, document, and debug functional issues found during verification, collaborating with design engineers for resolution.
• Develop and apply coverage models to ensure thorough validation of the design.
• Work closely with architects, designers, and software teams to comprehend the design architecture and contribute to high-level verification strategy.
• Stay up-to-date with industry best practices and emerging tools for design verification.

Qualifications:

• Bachelor’s in Electrical Engineering, Computer Engineering, or a related field.
• 2+ year of experience in DV.
• Strong proficiency in verification languages such as System Verilog, UVM (Universal Verification Methodology).
• Experience with simulation tools (e.g., Cadence Xcelium, Synopsys VCS, or Mentor Graphics QuestaSim).
• Familiarity with scripting languages such as Python, Perl, or Shell scripting for automation purposes.
• In-depth understanding of digital design principles, verification methodologies, and industry-standard protocols.
• Excellent analytical, debugging, and problem-solving skills.
• Strong teamwork and communication abilities.

Pay and Benefits

• Competitive salary.
• Performance bonus each year.
• Flexible working time.
• Health check each year.
• Insurance for engineer and family.
• Lunch Allowance.
• Company trips.

The company seeks a highly motivated and team-oriented individual to work with both layout and design engineers across multiple time zones

As an Integrated Circuit Designer - Layout, you will be part of a key team designing and developing sophisticated advanced node CMOS products.

Key Job Duties:

• The design and development of the layout for integrated circuits according to electronics engineering principles, using software to create design schematics and diagrams. This will include [floor planning, creating layouts of building blocks and integrating layouts for circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, and CDRs in advanced CMOS nodes. Your focus will include minimizing parasitic and skew, matching, EMIR, and antenna rules on top of DRC and LVS]
• The management of manufacturing process of the products, including technology yield and performance of the products. 
• The development of test programmes and procedures to ensure the products meet their performance specifications.
• The provision of advice on aspects of semiconductor process technology and maintain and repair semiconductor process equipment.

Basic Qualifications:

• At least a bachelor’s degree in electrical engineering

Required Experience:

• 4+ years of experience in the development of layouts for highspeed analog IC designs in fin FET technology.
• Experience with layout extraction tools and to analyzing layout parasitic to achieve high quality layout for highspeed circuits.
• EMIR and antenna DRC rules aware layout practices.
• Experience writing SKILL and TCL scripts is highly recommended

Pay and Benefits

• Competitive salary.
• 13th month salary.
• Performance bonus each year.
• Long Term Incentive (LTI)
• Health check each year.
• Insurance for engineer and family.
• Lunch Allowance.
• Company trips.