The Anduril Battlespace Awareness Radar team develops state-of-the-art radar systems, deployed to tackle the most significant security challenges of America and its allies. The Radar team is seeking an Electrical Test Engineer to help us test the next generation of US radars. The Radar team is responsible for all aspects of radar system development, from the ideation stage through initial production.  In this role, you will work closely with an interdisciplinary technical team to perform testing and collaborate with design engineers to mature the prototypes into products. 

WHAT YOU’LL DO

• Conduct integration and developmental testing of complex electrical subystems, including high speed digital and RF components.
• Work closely with other electrical, mechanical, software, firmware, and test engineers to deliver fully functional products.
• Conduct environmental testing to ensure the reliability of our radars in various environments.
• Create and update test procedures for validating printed circuit board performance against design targets. Design test automation to streamline this testing where possible.
• Stay current with emerging technologies and industry trends to drive innovation and maintain our technological edge.

REQUIRED QUALIFICATIONS

• Bachelor’s Degree in Electrical Engineering or equivalent, with 3+ years of experience testing and troubleshooting complex board designs.
• Experience with analog and digital electronics testing and troubleshooting.
• Competence with test equipment such as oscilloscopes, logic analyzers, current-probes, and automation of tests.
• Familiarity with standard interfaces such as Ethernet, CAN, I2C, SPI, PCIe, USB, etc..
• Knowledge of modern analog and digital electronics and electronic circuits.
• Comfortable with a variety of electronic CAD tools (Altium preferred, Eagle and others acceptable).
• Experience with test automation scripting (e.g., Python) for data acquisition and control.
• Experience in testing and debugging for signal integrity / power integrity.
• Strong time management and organizational abilities, with a demonstrated ability to deliver projects on time and within budget.
• Excellent problem-solving skills, with the ability to think creatively and adapt to diverse and evolving challenges.
• Eligible to obtain and maintain an active U.S. Secret security clearance (use appropriate one from here - Recruiter to own)

PREFERRED QUALIFICATIONS

• Familiarity with common MCU, CPU, FPGA devices and technologies.
• Experience with RF electronics testing and troubleshooting.
• Experience with RF test equipment such has VNAs, signal analyzers, signal generators, and power meters.
• Experience with environmental testing procedures and standards to pass MIL-STD-810.
• Experience developing test fixtures to support board testing and troubleshooting

We request transcripts as part of the early application process to understand your academic background and how your coursework supports the skills deemed critical for the role. Transcripts help us assess your technical and analytical abilities, complementing our interview process in which we also evaluate practical experience and cultural fit. If you choose not to share your transcripts, you will need to provide detailed information regarding your academic performance in relevant courses, including projects and coursework specifics, to ensure we evaluate your academic accomplishments properly. If you do provide academic transcripts, feel free to redact non-technical information (e.g., student ID, dates, non-technical coursework, etc.). Unofficial transcripts obtained online acceptable for this assessment.

Location: This role is based at our Louisville, CO office with the option to work a few days a week remotely. 
Travel: Up to 5%
Job ID: 1569

The Role

As the Senior Manager of Flight Software at Capella, you will lead the team responsible for developing and maintaining the software that runs Capella’s satellite fleet in space. You will oversee the full flight software organization, supporting mission-critical development and on-orbit operations across multiple programs. In this role, you will set the technical direction and execution strategy for flight software, while building and scaling a high-performing engineering team. You’ll partner closely with electrical, FPGA, systems, and ground software teams to deliver robust and reliable spacecraft software. This position offers the opportunity to shape the future of Capella’s flight software architecture, drive engineering excellence, and ensure consistent delivery of high-quality software across the fleet.

Responsibilities

• Lead and manage the flight software engineering team, including hiring, onboarding, performance management, and career development.
• Own the overall technical direction, architecture, and execution strategy for flight software across programs.
• Ensure consistent delivery of high-quality, mission-critical software for on-orbit and pre-launch systems.
• Drive and uphold engineering best practices, including code reviews, automated testing, documentation, and design reviews.
• Collaborate with cross-functional leaders to align software development with system-level requirements and mission goals.
• Oversee software planning, roadmap development, and prioritization across multiple efforts.
• Support and guide architectural decisions, trade studies, and long-term technical investments.
• Maintain strong visibility into program execution, proactively identifying risks and ensuring timely delivery of milestones.
• Foster a culture of ownership, accountability, and continuous improvement within the team.
• Contribute to strategic planning and organizational growth as Capella scales.

Qualifications

• Bachelor's degree in computer science, computer engineering, electrical engineering, or a related field (advanced degree preferred).
• 10+ years of experience in software engineering, with 2+ years managing or leading engineering teams (embedded or aerospace preferred).
• Strong background in real-time embedded systems, including bare-metal, RTOS, and Linux environments.
• Proficiency in C and C++ (C++ experience highly preferred); experience with scripting languages such as Python or shell scripting.
• Experience defining system architecture and technical strategy.
• Familiarity with embedded Linux, Linux kernel modules, and development tools.
• Experience with microcontrollers and SoCs (e.g., Xilinx Zynq) and hardware/software integration.
• Strong communication and leadership skills, with the ability to align cross-functional teams and drive execution.
• Working knowledge of modern software development practices including Git, CI/CD, and automated testing.

Required Qualification

To conform to U.S. Government space technology export regulations, including the International Traffic in Arms Regulations (ITAR), Capella Employees must be a U.S. citizen, lawful U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum, or be eligible to obtain the required authorizations from the U.S. Department of State and/or the U.S. Department of Commerce, as applicable. Learn more about ITAR here.

Compensation 

The approximate base salary range for this position is $192,979 - $252,659. The total compensation package includes base salary, bonus, equity, and a range of benefits available on our career site. 

ABOUT THE TEAM

The Space Imaging team is seeking a Systems Engineer to join our team. The Imaging Space team is responsible for system architecture definition, trade analyses, and modeling/validating system performance for spaceborne EO/IR systems.

In this role, you will be responsible for defining active EO/IR system architectures. You will perform radiometric performance modeling as well as laboratory, ground, and flight testing. To predict real-world performance, you will also model atmospheric and environmental effects for land, sea, and air targets. You will leverage your analyses to inform system-level architectural trades. As needed, you will also lead small teams of engineers from concept ideation through system definition and development.

You should have a track record of successfully working on fast-paced, highly technical, interdisciplinary teams. Proficiency in analytical toolchains or languages (e.g., MATLAB, Python) is required. Experience with industry standard EO/IR modeling software packages (e.g. MODTRAN, SPIRITS, AFSIM) is a plus. Prior experience working with space sensors and systems is highly desirable.

WHAT YOU’LL DO

• Define system architectures via detailed trade studies and analyses.
• Adapt or derive physics-based models of sensor system performance and derive requirements based on those models.
• Take ownership over the development of prototype sensor systems in a lab environment.
• Support both laboratory-based and field-based experiments and demonstrations.
• Engage technically with the hardware, software, and mission teams to define, integrate, and deliver high performance systems to our customers.
• Validate models against laboratory and real-world data.
• Coordinate and communicate with both external & internal stakeholders with varying degrees of technical background.

REQUIRED QUALIFICATIONS

• Model development and validation in one or more domains relevant to remote sensing
• Ability to decompose complex systems into functional parts, with clearly defined interfaces and requirements for each.
• Experience in system design and development from initial concept through test and delivery to customer.
• Strong laboratory skills (rapid prototyping, design of experiments) and familiarity with opto-electrical test and measurement equipment.
• Willingness to travel to test sites, as needed.
• Must be able to obtain and hold a U.S. security clearance.

PREFERRED QUALIFICATIONS

• Knowledge of current and next-generation advanced sensing systems and platforms
• Active and passive sensing domain experience (e.g., LiDAR, EO/IR, Radar)
• Experience with laser systems, including opto-mechanical scanning and beam steering techniques.
• Knowledge of electro-mechanical control systems, including their performance requirements and verification methodologies.
• Experience with LiDAR/Radar signal processing techniques, and knowledge of their implementation on real-time embedded platforms (FPGA, MCU, etc.).
• Experience with signature and/or scenario modeling/software packages (MODTRAN, SPIRITS, AFSIM).
• Space domain experience (architecting sensors for operation in space environments)

ABOUT THE TEAM

The Anduril Battlespace Awareness Radar team develops innovative and differentiated radar solutions to tackle significant security challenges for America and its allies. We are looking for highly collaborative engineers that will bring significant expertise, experience and energy to the team's endeavors.  

ABOUT THE JOB

Anduril seeking a skilled and experienced Edge Software Deployment Engineer to join our radar software team. The ideal candidate will be responsible for deploying, managing, and securing software that runs on the embedded, heterogeneous processors within our radar systems. This role requires a unique blend of embedded systems knowledge, DevOps practices, and experience with diverse hardware architectures.

WHAT YOU WILL DO

• DevOps for Embedded Systems: Adapt standard DevOps principles and tools for the unique constraints of embedded systems for Radar, which includes managing fleet-wide software updates for devices with intermittent connectivity.
• Security: Integrate security best practices and tools into the development and deployment process from the beginning (DevSecOps). This includes core security hardening (e.g., implementing STIGs), kernel hardening (e.g., using Address Space Layout Randomization, Control Flow Integrity, and securing boot processes), securing the software supply chain, managing updates, and implementing robust security controls on embedded hardware.
• Deployment and Provisioning: Lead the design and automation of the edge provisioning pipeline, from operating system setup to application deployment and monitoring.
• Continuous Integration/Continuous Deployment (CI/CD): Design, implement, and maintain CI/CD pipelines using tools like CircleCI to automate the build, testing, and deployment of software to edge devices.
• Operating Systems (OS): Manage and customize embedded Linux distributions (e.g., using Yocto or NixOS) for performance, reliability, and security on ARM and GPU architectures.
• Heterogeneous Architecture Support: Deploy and manage software across our diverse hardware platform, which includes:
  • Nvidia Jetson: Deploy, optimize, and manage software on Nvidia Jetson GPUs
  • FPGAs: Interact with HDL firmware for FPGAs (Altera Agilex, Xilinx Ultrascale) and C++ applications for soft processors within FPGAs,  using development toolchains like Quartus and Vivado.
  • CPU Architectures: Deploy and manage software for ARM CPU architectures.
• System Integration: Collaborate with hardware, firmware, and software engineering teams to ensure seamless hardware-software integration.
• Troubleshooting: Provide technical support and troubleshoot software issues on fielded devices.

REQUIRED QUALIFICATIONS

• 8+ Years of experience and a Bachelor's degree in Computer Science, Electrical Engineering, or a related technical field
• Proven experience in a DevOps, SRE, or embedded systems role.
• Deep expertise in Linux internals and system-level configuration.
• Experience with declarative configuration management, preferably with Nix or NixOS, for creating reproducible build environments.
• Experience with CI/CD tools such as CircleCI.
• Proficiency in scripting languages like Python and Bash.
• Hands-on experience with hardware-in-the-loop (HITL) and system integration labs (SIL).
• Experience with containerization (Docker) and orchestration tailored for resource-constrained edge environments.
• Solid understanding of cybersecurity principles for embedded and edge devices, including core hardening techniques.
• Excellent communication and problem-solving skills.
• Eligible to obtain and maintain an active U.S. Top Secret security clearance

DESIRED SKILLS (PLUS)

• Experience with bootloaders like U-Boot and secure boot processes.
• Familiarity with FPGA development tools such as Quartus and Vivado.
• Knowledge of network protocols and security on embedded systems.
• Experience deploying embedded systems in air-gapped or intermittently connected environments

ABOUT THE TEAM

The Anduril Imaging team develops state-of-the-art imaging systems across both hardware and software, deployed to tackle the most significant security challenges of America and its allies. The team is heavily involved in utilizing computer vision, perception, electro-optical, infrared, and sensor data to give our war fighters and allies an advantage.

ABOUT THE JOB

Anduril Imaging’s System Engineering team is seeking a Systems Engineer to join our team. The System Engineering team is responsible for system architecture definition, trade analyses, and modeling/validating system performance for land, sea, air, and space EO/IR applications.

In this role, you will be responsible for defining active EO/IR system architectures.  You will perform radiometric performance modeling as well as laboratory, ground, and flight testing.  To predict real-world performance, you will also model atmospheric and environmental effects for land, sea, and air targets. You will leverage your analyses to inform system-level architectural trades.  As needed, you will also lead small teams of engineers from concept ideation through system definition and development.

You should have a track record of successfully working on fast-paced, highly technical, interdisciplinary teams.  Proficiency in analytical toolchains or languages (e.g., MATLAB, Python) is required.  Experience with industry standard EO/IR modeling software packages (e.g. MODTRAN, SPIRITS, AFSIM) is a plus.

WHAT YOU’LL DO

• Define system architectures via detailed trade studies and analyses.
• Adapt or derive physics-based models of sensor system performance and derive requirements based on those models.
• Take ownership over the development of prototype sensor systems in a lab environment.
• Support both laboratory-based and field-based experiments and demonstrations.
• Engage technically with the hardware, software, and mission teams to define, integrate, and deliver high performance systems to our customers.
• Validate models against laboratory and real-world data.
• Coordinate and communicate with both external & internal stakeholders with varying degrees of technical background.

REQUIRED QUALIFICATIONS

• Model development and validation in one or more domains relevant to remote sensing
• Ability to decompose complex systems into functional parts, with clearly defined interfaces and requirements for each.
• Experience in system design and development from initial concept through test and delivery to customer.
• Strong laboratory skills (rapid prototyping, design of experiments) and familiarity with opto-electrical test and measurement equipment.
• Willingness to travel to test sites, as needed.
• Must be able to obtain and hold a U.S. security clearance.

PREFERRED QUALIFICATIONS 

• Knowledge of current and next-generation advanced sensing systems and platforms
• Active and passive sensing domain experience (e.g., LiDAR, EO/IR, Radar)
• Experience with laser systems, including opto-mechanical scanning and beam steering techniques.
• Knowledge of electro-mechanical control systems, including their performance requirements and verification methodologies.
• Experience with LiDAR/Radar signal processing techniques, and knowledge of their implementation on real-time embedded platforms (FPGA, MCU, etc.).
• Experience with signature and/or scenario modeling/software packages (MODTRAN, SPIRITS, AFSIM).

Hudson River Trading (HRT) is seeking a Physical Design Engineer with a broad, versatile skillset to join our growing Hardware team. In this role, you will help deliver performance-critical ASICs and advance our physical design methodologies on leading-edge process nodes.

The Hardware team at HRT builds high-performance compute engines using FPGA and ASIC technology to drive low-latency trading decisions on global markets. We create custom solutions across the full spectrum of speed and sophistication, from bespoke circuits to world-class machine learning accelerators.

Responsibilities

• Drive design-for-test (DFT) methodologies and implementation 
• Contribute to physical implementation, from RTL handoff through GDSII on advanced process nodes 
• Partner on floorplanning and physical optimization for high-performance, latency-critical designs
• Close timing across multiple modes and corners while optimizing power, performance, and area (PPA)
• Diagnose and resolve physical design issues such as timing bottlenecks, congestion, and IR/EM violations
• Build, maintain, and improve repeatable, automated physical design flows
• Develop scripts and tooling to improve productivity, robustness, and insight into design behavior
• Collaborate closely with RTL, architecture, and other hardware engineers to influence design decisions early

Qualifications

• Experience working in high-performance ASIC design environments
• Strong fundamentals in digital logic, circuit design, and process technology
• Familiarity with DFT concepts and testing methodologies
• Strong scripting and automation skills (Python, Tcl, shell), including parsing and analyzing tool outputs
• Ability to design robust methodologies, diagnose complex failures, and improve physical design flows
• Applied use of statistics in analyzing timing, power, or design data (preferred)
• Hands-on experience with static timing analysis and timing closure methodologies
• Expertise using industry-standard physical design and signoff tools (e.g., Innovus, PrimeTime)

This job is accepting ongoing applications and there is no application deadline.

The estimated base salary range for this position is 200,000 to 300,000 USD per year (or local equivalent). The base pay offered may vary depending on multiple individualized factors, including location, job-related knowledge, skills, and experience.

This role will also be eligible for discretionary performance-based bonuses and a competitive benefits package which includes medical, dental, vision, basic life insurance, and enrollment in our company’s retirement savings plans. Employees will receive sick and parental leave, as well as other paid time off (including 20 vacation days and 10 paid holidays in the US). Please note that benefits and time off policies will vary across non-US locations.

In any materials you submit, you may redact or remove age-identifying information such as age, date of birth, or dates of school attendance or graduation. You will not be penalized for redacting or removing this information.

The Hardware team at Hudson River Trading (HRT) creates high performance compute engines using FPGA and ASIC technology to drive low latency trading decisions on global markets. We build custom solutions across the spectrum of speed and smarts: from bespoke circuits to world-class machine learning accelerators.

These high performance designs require even higher performance verification. We are looking for experienced Design Verification (DV) engineers who are skilled at writing testbenches and building verification environments to exercise complex HDL. Our ideal candidate is not only an ace tester, but a practicing toolsmith. You know the EDA landscape and want to be part of a team actively working to rethink, redesign, and surpass the status quo. For example, members of our team are active maintainers of popular open source projects such as Slang, Verilator, and Cocotb.

FPGA and ASIC verification is part of an innovative, growing team at HRT which is integral to the success of our trading. You can expect to always be challenged by the ever-changing financial markets as you work to ensure correctness and robustness of our critical hardware in an extremely fast-paced, real-time environment. No financial experience is necessary.

Responsibilities

• Creating testbenches and tests for our hardware platform, leveraging a hybrid open-source/proprietary, highly flexible environment
• Writing detailed verification plans
• Quickly root-cause RTL bugs
• Collaborating directly with designers for rapid bringup of new projects and debugging of existing designs
• Managing test suites and continuous integration infrastructure
• Developing and improving open-source and internal tools

Qualifications 

• Superb debug and analytical skills 
• Professional experience (2+ years) in RTL functional verification for FPGA or ASIC
• Experience with code and functional coverage collection/analysis
• Experience with SystemVerilog and industry-standard frameworks such as UVM
• Experience with Python
• Comfortable in a Linux environment
• Familiarity with Verilator and/or Cocotb preferred
• C++ experience is a plus
• A bachelor’s degree in computer science, electrical engineering, or a related field

The estimated base salary range for this position is 175,000 to 250,000 USD per year (or local equivalent). The base pay offered may vary depending on multiple individualized factors, including location, job-related knowledge, skills, and experience. This role will also be eligible for discretionary performance-based bonuses and a competitive benefits package.

The Hardware team at Hudson River Trading (HRT) creates high performance compute engines using FPGA and ASIC technology to drive low latency trading decisions on global markets. We build custom solutions across the spectrum of speed and smarts: from bespoke circuits to world-class machine learning accelerators.

FPGAs and ASICs are critical pieces of our technology stack. We are looking for talented hardware developers to architect and design complex systems on a highly collaborative global team. In this role, you'll identify efficient ways to perform on-the-fly transformations of market data and implement models with complex data structures in RTL. Deep knowledge of SystemVerilog, FPGA internals and/or ASIC primitives, computer architecture, and vendor tool suites are essential to succeeding in this role. Expertise in networking protocols, CPU design, and/or machine learning accelerators is a big plus. No financial experience is necessary.

Responsibilities

• Collaborate with a cross-functional team to develop and deploy custom FPGA and/or ASIC solutions for a wide range of trading applications
• Investigate new technologies and tools
• Contribute to a nimble hardware development tech stack

Qualifications

• Ability to describe hardware designs at a high level, low level, or anywhere in between
• Brilliant design, optimization, debugging and problem solving skills
• Professional experience (2+ years) in RTL design for FPGA or ASIC
• Expert SystemVerilog development skills with a thorough understanding of the language 
• Expert on low level FPGA or ASIC architectures, with a deep understanding of what makes them "tick"
• Skilled in network communications, processing pipelines, and/or machine learning
• Working knowledge of Python and/or C++
• Comfortable in a Linux environment
• Strong verification experience
• Familiarity with AMD Vivado is a plus
• A bachelor’s degree in computer science, electrical engineering, or a related field

This job is accepting ongoing applications and there is no application deadline.

The estimated base salary range for this position is 200,000 to 300,000 USD per year (or local equivalent). The base pay offered may vary depending on multiple individualized factors, including location, job-related knowledge, skills, and experience.

This role will also be eligible for discretionary performance-based bonuses and a competitive benefits package which includes medical, dental, vision, basic life insurance, and enrollment in our company’s retirement savings plans. Employees will receive sick and parental leave, as well as other paid time off (including 20 vacation days and 10 paid holidays in the US). Please note that benefits and time off policies will vary across non-US locations.

In any materials you submit, you may redact or remove age-identifying information such as age, date of birth, or dates of school attendance or graduation. You will not be penalized for redacting or removing this information.