About Akuna: 

Akuna Capital is an innovative trading firm with a strong focus on collaboration, cutting-edge technology, data driven solutions, and automation. We specialize in providing liquidity as an options market-maker – meaning we are committed to providing competitive quotes that we are willing to both buy and sell. To do this successfully, we design and implement our own low latency technologies, trading strategies, and mathematical models. 

Our Founding Partners first conceptualized Akuna in their hometown of Sydney. They opened the firm’s first office in 2011 in the heart of the derivatives industry and the options capital of the world – Chicago. Today, Akuna is proud to operate from additional offices in Sydney, Shanghai, London, and Singapore. 

What you’ll do as a Senior FPGA Engineer at Akuna: 

We are looking for Senior FPGA Engineers to accelerate various portions of our trading platform. Members of the Hardware Development team will work with cutting-edge FPGA technology and high-performance computing architectures – owning projects end-to-end and making Akuna’s systems faster and smarter. In this role, you will: 

• Own projects - driving project progression from inception, requirements, architecture, design entry, timing closure and verification
• Partner closely with the Low Latency, Trading and other teams to foster and develop ideas that performance 
• Develop and maintain RTL in Verilog/SystemVerilog
• Write and maintain verification environments
• Design optimization for timing closure
• Develop and maintain project documentation 

Qualities that make great candidates: 

• 10+ years of experience in FPGA or ASIC digital logic design – network traffic experience a strong plus
• Deep Verilog/SystemVerilog or VHDL skills
• Solid grasp of static timing analysis, synthesis, and place-and-route tools  
• Familiarity with algorithms, data structures, and verification/unit testing workflows
• Python and Bash scripting fluency
• Enthusiasm for collaboration with other FPGA team members as well as members from software and trading teams
• Open mindedness for novel development approaches and architectures
• Bachelor’s degree in Computer or Electrical Engineering, or related field; master’s degree a plus 
• The ability to react quickly and accurately to rapidly changing market conditions, including the ability to quickly and accurately respond and/or solve math and coding problems are essential functions of the role

In addition to technical skillsets, Akuna values the unique perspectives people can bring to the table to collaboratively solve complex problems and drive Akuna forward. We want everyone to feel empowered to apply. We welcome your application and encourage you to take the first steps toward your future with us!

In accordance with Illinois Equal Pay Act, the minimum base salary starts at $145,000. Exact compensation offered may vary based on many factors including, but not limited to, the candidate’s experience, qualifications, and skill set. This role is also eligible for a discretionary performance bonus as part of the total compensation package and includes a comprehensive benefits package that may encompass employer-paid medical, dental, vision, retirement contributions, paid time off, and other benefits. The minimum base salary herein was determined in good faith by Akuna Capital LLC.

Qube Research & Technologies (QRT) is a global quantitative and systematic investment manager, operating in all liquid asset classes across the world. We are a technology and data driven group implementing a scientific approach to investing. Combining data, research, technology and trading expertise has shaped QRT’s collaborative mindset which enables us to solve the most complex challenges. QRT’s culture of innovation continuously drives our ambition to deliver high quality returns for our investors. 

Your future role within QRT:

QRT are a rapidly growing hedge fund trading globally in competitive financial markets across Europe, the Middle East and Asia. As part of the next phase of development we are rolling out hardware platforms to accelerate our trading systems. FPGA development will be at the heart of many of these systems with a focus on high frequency trading. 

We are looking for talented hardware engineers with a track record of achievement in any domain. You may have experience of finance and trading, but it is not essential. You probably enjoy solving complex system problems where hardware and software come together to provide high performance solutions. We are looking for a range of experience from graduates through to senior engineers, so your achievements may be in academia or industry.

You will have the opportunity to work with the latest technologies and have your voice heard in this fast paced firm. Working with trading teams you will take ownership of:

• Translating trading ideas into the most appropriate solutions
• Develop RTL on the latest FPGAs with modern design flows
• Following through into production, analysing results and optimising

Your present skillset:

• A deep understanding of FPGA architecture leading to efficient designs
• Full lifecycle RTL development including automated verification
• Python scripting
• A working knowledge of C/C++ development
• An ability to see through complexity to identify simple solutions
• A realisation that good teamwork is essential to modern development

 
Base salary range for this position is $180,000 to $280,000 per year. 

QRT Total Compensation includes discretionary performance-based bonuses and a competitive benefits package.

DRW is a diversified trading firm with over 3 decades of experience bringing sophisticated technology and exceptional people together to operate in markets around the world. We value autonomy and the ability to quickly pivot to capture opportunities, so we operate using our own capital and trading at our own risk.

Headquartered in Chicago with offices throughout the U.S., Canada, Europe, and Asia, we trade a variety of asset classes including Fixed Income, ETFs, Equities, FX, Commodities and Energy across all major global markets. We have also leveraged our expertise and technology to expand into three non-traditional strategies: real estate, venture capital and cryptoassets.

We operate with respect, curiosity and open minds. The people who thrive here share our belief that it’s not just what we do that matters–it's how we do it. DRW is a place of high expectations, integrity, innovation and a willingness to challenge consensus.

We are currently seeking a FPGA Engineer to join one of our trading teams. While DRW has been leveraging FPGA technology for a number of years, you will have the opportunity to build an FPGA application from scratch for an existing team. We’re seeking a candidate that has a strong understanding of software and hardware interaction. This person will participate in the full development lifecycle, including system and block level testing, of low latency high throughput FPGA design.

This role is for the Chicago office only.

Responsibilities: 

• Architect and implement new FPGA applications (synthesis, place & route, static timing analysis, documentation) from the ground up
• Research and evaluate a variety of cutting-edge FPGA hardware and technologies
• Propose creative solutions to overcome FPGA/hardware limitations
• Liaise directly with software and other design teams
• Conduct lab debugging and characterization of new hardware

Candidate Requirements: 

• Bachelor’s degree or higher, Computer/Electrical Engineering with 3+ years of experience within the field; (Master’s degree or higher also counts for experience)
• Solid Hardware Engineering experience, especially with FPGA
• Highly autonomous with a can-do attitude able to lead an FPGA based project from system requirements to production
• Strong capacity to quickly evaluate FPGA based project feasibility based on hardware limitation
• Strong skills in RTL logic design (Verilog) and verification; 2+ years of experience writing Verilog
• Experience in FPGA design flow including synthesis, place & route , static timing analysis is required
• Experience with the design of system-on-chip (SOC) architectures, memory & processor subsystems, networking, and peripheral interconnect is required
• Knowledge of the TCP/IP stack
• Strong working knowledge of either XILINX or ALTERA FPGA design flow
• Experience with functional verification utilizing high-level methodologies (e.g. System Verilog) is a plus.
• Excellent research and data gathering skills

The annual base salary range for this position is $150,000 to $250,000 depending on the candidate’s experience, qualifications, and relevant skill set. The position is also eligible for an annual discretionary bonus. In addition, DRW offers a comprehensive suite of employee benefits including group medical, pharmacy, dental and vision insurance, 401k (with discretionary employer match), short and long-term disability, life and AD&D insurance, health savings accounts, and flexible spending accounts.

For more information about DRW's processing activities and our use of job applicants' data, please view our Privacy Notice at https://drw.com/privacy-notice.

California residents, please review the California Privacy Notice for information about certain legal rights at https://drw.com/california-privacy-notice.

#LI-BL1

The Hardware team at Hudson River Trading (HRT) creates high performance compute engines using FPGA and ASIC technology to drive low latency trading decisions on global markets. We build custom solutions across the spectrum of speed and smarts: from bespoke circuits to world-class machine learning accelerators.

These high performance designs require even higher performance verification. We are looking for experienced Design Verification (DV) engineers who are skilled at writing testbenches and building verification environments to exercise complex HDL. Our ideal candidate is not only an ace tester, but a practicing toolsmith. You know the EDA landscape and want to be part of a team actively working to rethink, redesign, and surpass the status quo. For example, members of our team are active maintainers of popular open source projects such as Slang, Verilator, and Cocotb.

FPGA and ASIC verification is part of an innovative, growing team at HRT which is integral to the success of our trading. You can expect to always be challenged by the ever-changing financial markets as you work to ensure correctness and robustness of our critical hardware in an extremely fast-paced, real-time environment. No financial experience is necessary.

Responsibilities

• Creating testbenches and tests for our hardware platform, leveraging a hybrid open-source/proprietary, highly flexible environment
• Writing detailed verification plans
• Quickly root-cause RTL bugs
• Collaborating directly with designers for rapid bringup of new projects and debugging of existing designs
• Managing test suites and continuous integration infrastructure
• Developing and improving open-source and internal tools

Qualifications 

• Superb debug and analytical skills 
• Professional experience (2+ years) in RTL functional verification for FPGA or ASIC
• Experience with code and functional coverage collection/analysis
• Experience with SystemVerilog and industry-standard frameworks such as UVM
• Experience with Python
• Comfortable in a Linux environment
• Familiarity with Verilator and/or Cocotb preferred
• C++ experience is a plus
• A bachelor’s degree in computer science, electrical engineering, or a related field

The estimated base salary range for this position is 175,000 to 250,000 USD per year (or local equivalent). The base pay offered may vary depending on multiple individualized factors, including location, job-related knowledge, skills, and experience. This role will also be eligible for discretionary performance-based bonuses and a competitive benefits package.

Hudson River Trading (HRT) is seeking a Physical Design Engineer with a broad, versatile skillset to join our growing Hardware team. In this role, you will help deliver performance-critical ASICs and advance our physical design methodologies on leading-edge process nodes.

The Hardware team at HRT builds high-performance compute engines using FPGA and ASIC technology to drive low-latency trading decisions on global markets. We create custom solutions across the full spectrum of speed and sophistication, from bespoke circuits to world-class machine learning accelerators.

Responsibilities

• Drive design-for-test (DFT) methodologies and implementation 
• Contribute to physical implementation, from RTL handoff through GDSII on advanced process nodes 
• Partner on floorplanning and physical optimization for high-performance, latency-critical designs
• Close timing across multiple modes and corners while optimizing power, performance, and area (PPA)
• Diagnose and resolve physical design issues such as timing bottlenecks, congestion, and IR/EM violations
• Build, maintain, and improve repeatable, automated physical design flows
• Develop scripts and tooling to improve productivity, robustness, and insight into design behavior
• Collaborate closely with RTL, architecture, and other hardware engineers to influence design decisions early

Qualifications

• Experience working in high-performance ASIC design environments
• Strong fundamentals in digital logic, circuit design, and process technology
• Familiarity with DFT concepts and testing methodologies
• Strong scripting and automation skills (Python, Tcl, shell), including parsing and analyzing tool outputs
• Ability to design robust methodologies, diagnose complex failures, and improve physical design flows
• Applied use of statistics in analyzing timing, power, or design data (preferred)
• Hands-on experience with static timing analysis and timing closure methodologies
• Expertise using industry-standard physical design and signoff tools (e.g., Innovus, PrimeTime)

This job is accepting ongoing applications and there is no application deadline.

The estimated base salary range for this position is 200,000 to 300,000 USD per year (or local equivalent). The base pay offered may vary depending on multiple individualized factors, including location, job-related knowledge, skills, and experience.

This role will also be eligible for discretionary performance-based bonuses and a competitive benefits package which includes medical, dental, vision, basic life insurance, and enrollment in our company’s retirement savings plans. Employees will receive sick and parental leave, as well as other paid time off (including 20 vacation days and 10 paid holidays in the US). Please note that benefits and time off policies will vary across non-US locations.

In any materials you submit, you may redact or remove age-identifying information such as age, date of birth, or dates of school attendance or graduation. You will not be penalized for redacting or removing this information.

The Hardware team at Hudson River Trading (HRT) creates high performance compute engines using FPGA and ASIC technology to drive low latency trading decisions on global markets. We build custom solutions across the spectrum of speed and smarts: from bespoke circuits to world-class machine learning accelerators.

FPGAs and ASICs are critical pieces of our technology stack. We are looking for talented hardware developers to architect and design complex systems on a highly collaborative global team. In this role, you'll identify efficient ways to perform on-the-fly transformations of market data and implement models with complex data structures in RTL. Deep knowledge of SystemVerilog, FPGA internals and/or ASIC primitives, computer architecture, and vendor tool suites are essential to succeeding in this role. Expertise in networking protocols, CPU design, and/or machine learning accelerators is a big plus. No financial experience is necessary.

Responsibilities

• Collaborate with a cross-functional team to develop and deploy custom FPGA and/or ASIC solutions for a wide range of trading applications
• Investigate new technologies and tools
• Contribute to a nimble hardware development tech stack

Qualifications

• Ability to describe hardware designs at a high level, low level, or anywhere in between
• Brilliant design, optimization, debugging and problem solving skills
• Professional experience (2+ years) in RTL design for FPGA or ASIC
• Expert SystemVerilog development skills with a thorough understanding of the language 
• Expert on low level FPGA or ASIC architectures, with a deep understanding of what makes them "tick"
• Skilled in network communications, processing pipelines, and/or machine learning
• Working knowledge of Python and/or C++
• Comfortable in a Linux environment
• Strong verification experience
• Familiarity with AMD Vivado is a plus
• A bachelor’s degree in computer science, electrical engineering, or a related field

This job is accepting ongoing applications and there is no application deadline.

The estimated base salary range for this position is 200,000 to 300,000 USD per year (or local equivalent). The base pay offered may vary depending on multiple individualized factors, including location, job-related knowledge, skills, and experience.

This role will also be eligible for discretionary performance-based bonuses and a competitive benefits package which includes medical, dental, vision, basic life insurance, and enrollment in our company’s retirement savings plans. Employees will receive sick and parental leave, as well as other paid time off (including 20 vacation days and 10 paid holidays in the US). Please note that benefits and time off policies will vary across non-US locations.

In any materials you submit, you may redact or remove age-identifying information such as age, date of birth, or dates of school attendance or graduation. You will not be penalized for redacting or removing this information.

At Optiver we pride ourselves on being real engineers, not just coders. Our engineers work closely with traders to identify the business problems we face and determine how they should be solved. We apply a disciplined and scientific approach. We engineer simple, well-architected solutions that meet the dynamic needs of our traders. Our passion is to solve problems which really matter to the business, and we take pride in the quality of our solutions.

Hardware Engineers at Optiver build hardware-based trading systems ranging from low latency algorithms to high bandwidth computation. They are responsible for owning all aspects of the development process from ideation to implementation creating bespoke solutions to our complex trading problems. Their systems have little room for failure which add to the stability of the market, not detract from it. Working in close collaboration with software engineers and traders, hardware engineers deeply understand our trading problems and create dynamic, well-architected systems that make an impact in a matter of days and weeks rather than months and years.

What you’ll do: 

• Accelerate network infrastructure and trading system components with high-speed hardware designs.
• Research new low-latency techniques and platforms and identify opportunities for integration with our trading system.
• Work in a multidisciplinary team of traders, software developers, and infrastructure engineers.
• Leverage the best hardware available or build in-house versions to ensure our FPGAs can interface with cutting edge server hardware.
• Manage relationships with 3rd party vendors.

What you’ll get:

You’ll join a culture of collaboration and excellence, surrounded by curious thinkers and creative problem-solvers. Motivated by a passion for continuous improvement, you’ll thrive in a supportive, high-performing environment alongside talented colleagues, collectively tackling some of the toughest challenges in the financial markets.

In addition, you’ll receive:

• The opportunity to work alongside best-in-class professionals from over 40 different countries
• A highly competitive compensation package
• Global profit-sharing pool and performance-based bonus structure
• 401(k) match up to 50%
• Comprehensive health, mental, dental, vision, disability, and life coverage
• 25 paid vacation days alongside market holidays
• Extensive office perks, including breakfast, lunch and snacks, regular social events, clubs, sporting leagues and more

Who you are:

• A Bachelor’s degree in CE, EE, CS, or related technical field.
• Experience designing, coding, testing, and verifying FPGAs and/or ASICs.
• Experience coding in VHDL, Verilog, SystemVerilog as well as C or C++.
• Experience with RTL synthesis, writing timing, area, and other relevant constraints.
• Experience with digital simulators and self-checking test benches.
• Experience supporting post-silicon bring-up and debugging a plus.
• Ability to work closely with software developers to rapidly deliver integrated systems.

Who we are:

At Optiver, our mission is to improve the market by injecting liquidity, providing accurate pricing, increasing transparency, and stabilising the market no matter the conditions. With a focus on continuous improvement, we prioritise safeguarding the health and efficiency of the markets for all participants. As one of the largest market making institutions, we are a respected partner on 100+ exchanges across the globe.

Optiver Chicago’s culture parallels the energetic city we’re immersed in. Home to the Chicago Board of Trade, Chicago Board Options Exchange, and Chicago Mercantile Exchange, Chicago has established itself as the trading capital of the US. Active on leading US exchanges, Optiver’s Chicago office trades a wide range of products from listed derivatives to cash equities, ETFs, bonds and foreign exchange

Our differences are our edge. Optiver does not discriminate on the basis of race, religion, color, sex, gender identity, sexual orientation, age, physical or mental disability, or other legally protected characteristics.

Optiver is looking to add FPGA Engineers to its Automated Trading Systems (ATS) team. ATS solve a variety of problems with high degrees of difficulty: managing scarce bandwidth resources, responding to market events with extremely low latency, and automatically pricing diverse sets of financial instruments with near-zero error tolerance. We build systems with little room for failure which add to the stability of the market, not detract from it. These systems must be simple, flexible, and well-architected so they can quickly be changed to meet the dynamic needs of our traders. We already have a team of great engineers, but we need more.

Optiver Hardware Engineers:

• Accelerate network infrastructure and trading system components with high speed hardware designs.
• Research new low-latency techniques and identify opportunities for integration with our trading system.
• Work in a multidisciplinary team of traders, software developers, and infrastructure engineers.
• Leverage the best hardware available, ensuring our FPGAs can interface with cutting edge server hardware.

What you'll need:

• A Bachelor’s degree in CE, EE, CS, or related technical field
• Experience designing FPGAs in VHDL or Verilog. We use VHDL.
• Experience coding in VHDL, Verilog, SystemVerilog, C, or C++
• Experience with digital simulators and self-checking test benches a plus
• Ability to work closely with software developers to rapidly deliver integrated systems.

Who we are:

Optiver is a tech-driven trading firm and leading global market maker. As one of the oldest market making institutions, we are a trusted partner of 70+ exchanges across the globe. Our mission is to constantly improve the market by injecting liquidity, providing accurate pricing, increasing transparency and acting as a stabilising force no matter the market conditions. With a focus on continuous improvement, we participate in the safeguarding of healthy and efficient markets for everyone who participates.

Based in ‘The Domain’ neighborhood, Optiver’s Austin office serves as the firm’s innovation nucleus, with a strong focus on quantitative research, software and hardware engineering initiatives. With tech innovation an integral part of our core business, the booming city proved an ideal backdrop for our heavy investment into machine learning, research infrastructure and big data computing. What’s more, with world-class music, food and art scenes, as well as countless scenic outdoor activities, the quality of life for Austin Optiverians is second to none.

Please only apply to one of our Job Postings. At the bottom of the application questions below you'll have the option to indicate if there are any other roles here at Radix that you might be interested in. Please do not submit multiple applications for different positions.  

As part of the FPGA team, you’ll work with cutting-edge technology to improve performance and latency of our systems. As a member of a small and dynamic team, you’ll not only work to solve production issues but also come to the table with new and innovative ideas for automated trading.

Job Functions:

• Design and build new scalable systems
• Maintaining FPGA code
• Use Python for unit testing
• Use model-sim for simulation
• Debug and fix FPGA issues
• Innovate and design solutions that will overcome current limitations 

Key Capabilities:

• PhD in Electrical Engineering, Computer Architecture, or another closely-related engineering discipline (in the progress of obtaining or has obtained)
• Experience coding in VHDL/verilog
• Proficiency with Python for unit testing
• Used Xilnix and/or Altera FPGAs
• Familiar with Modelsim
• Previously worked on large FPGA stratix V or/and Virtex ultra-scale+ is a plus
• Knowledge of networking protocols:IP,/TCP/UDP etc.
• Highly analytical mindset
• Excellent communication skills, both written and oral
• Results oriented, highly flexible, team player
• Can tackle new things without a lot of help; fast learner
• Driven and self-guided
• Ability to function independently and take ownership
• Ability to multitask and iterate quickly towards a better solution

Geneva Trading is seeking a Mid-Level System Engineer to join our Core Infrastructure team in Chicago. This is a high-impact role where you will manage the intersection of elite hardware, Linux optimization, and low-latency networking. You will be responsible for ensuring our global trading platform remains performant, resilient, and highly automated.

Key Responsibilities

• Linux Infrastructure: Provision, configure, and maintain high-performance Red Hat/CentOS/Ubuntu environments.
• Automation & Orchestration: Build and maintain Infrastructure as Code (IaC) pipelines using Ansible, Terraform, or SaltStack.
• System Tuning: Fine-tune BIOS, kernel settings, and NICs (Solarflare/Mellanox) to squeeze every microsecond out of the stack.
• Network Integration: Collaborate with the Network Engineering team to manage high-bandwidth, low-latency trading paths.
• Monitoring: Proactively monitor system health and latency metrics using Prometheus, Grafana, or Telegraf.
• Hardware Lifecycle: Manage the deployment and troubleshooting of enterprise-grade bare-metal servers (Dell, HP, Supermicro).

Soft Skills & Communication

• Crisis Composure: Ability to remain calm and focused during high-volatility market events or system outages.
• Trader Interaction: Translate complex technical issues into concise updates for non-technical stakeholders (Traders and Quants) in real-time.
• Collaboration: A proactive communicator who documents "post-mortems" and shares knowledge across the engineering team to prevent recurring issues.

Required Skills & Qualifications

• Advanced Linux: Deep knowledge of the Linux kernel, system internals, and performance profiling tools.
• Scripting: Strong proficiency in Python or Bash for building tools and automating workflows.
• Server Architecture: Experience with modern server hardware, including CPU pinning, NUMA, and PCIe optimization.

Preferred Qualifications 

• Certifications: CCNA (Cisco Certified Network Associate) or equivalent networking knowledge.
• HFT Experience: Previous experience in a high-frequency trading or high-growth fintech environment.
• Low-Latency Tech: Exposure to kernel bypass (Onload), PTP (Precision Time Protocol), or FPGA integration.

Compensation

Base Salary Range: $100,000 - $150,000, plus eligibility for a performance-based bonus.

Final compensation will be determined based on the candidate’s skills, experience, education, and qualifications. In addition to base salary, Geneva Trading offers a competitive total rewards package, including a comprehensive benefits program. Learn more about our employee incentives here: https://www.genevatrading.com/employee-incentives/

Application expected to close: 6/01/2026

Are you excited by the idea of applying your hardware development expertise to power ultra-low-latency trading systems? Do you want to explore new architectures that push the limits of performance and help take some of our most sophisticated trading strategies to the next level? If so, we encourage you to read on! 

At CTC, we’re looking for a Senior FPGA Engineer to join our FPGA development team to do just that and more. As a member, you'll work closely with other specialists, traders, and quants to design and build the next generation of end-to-end trading systems. While helping craft our development environment and processes, you’ll architect solutions, influence design choices across teams, and see your work translate into real-time impact. 

Responsibilities

• Partner with a skilled team to define and implement a pragmatic architectural vision with a focus on ultra-low-latency and reliability. 
• Collaborate with senior technology leaders to continuously improve our trading platform design. 
• Build a deep understanding of trading workflows, quantitative models, and system performance needs while working with a multidisciplinary team. 
• Develop an implementation roadmap in partnership with Quant and Trading to deliver incremental improvements in trading performance and long-term architectural innovation. 
• Lead design implementation efforts, contribute to team code reviews, and champion best practices around performance, logic, standard methodologies and maintainability issues to ensure code-level consistency and scalability. 

Qualifications

• Proven experience and expertise with FPGA development. 
• Advanced proficiency using HDLs, with an emphasis on SystemVerilog or VHDL. 
• Comfortable working in Python and/or C++ for developing tools, testbenches, and integrations. 
• Demonstrated understanding of computer architectures. 
• Enthusiasm for applying modern, agile design and testing practices. 

Nice to Have 

• Experience in financial markets or trading environments. 
• Knowledge of common networking protocols like TCP/UDP and multicast. 

Maven is a market-leading proprietary trading firm deploying its own capital across discretionary, systematic, and market-making strategies. Backed by deep expertise in trading, technology, and research, we are relentlessly focused on improving liquidity across global listed derivatives. Through advanced execution and pricing technologies, we improve how financial markets operate.

Working on our trading floor, you will work alongside traders, quant researchers and other developers to help us expand system connectivity to new markets, optimise order execution algorithms, improve our trading strategies and build new automated pricing systems and infrastructure to support the expansion of our options market making business. The work you do will have a direct, regular and highly visible impact on the firm's success.

The skills you will have:

• Excellent C++ (11/14/17/20/23)
• Template programming
• Ultra low latency design
• Performance tuning and analysis
• Good numerical skills
• The ability to solve new and unfamiliar problems quickly and creatively
• An efficient and diligent approach with a strong attention to detail
• Excellent written and verbal communication skills
• An Interest in trading and finance

Things we would like to see but are not essential:

• Knowledge of financial markets & securities (particularly futures and options)
• Experience in the other programming languages: Python, C# or JavaScript
• Experience with NoSQL and time-series databases
• Knowledge of multiple derivative exchange platforms
• Network communication protocols UDP and TCP
• Network acceleration using proprietary drivers and kernel bypass
• Understanding of and optimisation for modern Intel architecture

What you will be doing with us:

• Full lifecycle of software development for market making, working alongside traders and developers in other teams, such as FPGA, data analytics and UI developers
• Developing low latency exchange connectivity components for new markets

We pride ourselves on being able to rapidly deliver well-engineered software into production. You will be able to see the impact of your work immediately and will be in a unique position to have a direct impact on trading revenue. We make extensive use of automated testing and peer code review to ensure quality and maintainability while keeping time-to-market short.

Our Benefits

At Maven our goal is to create an environment that empowers and motivates our employees to maximize their potential. Our comprehensive benefits package is designed to optimize performance, reward our employees, and allow them time to pursue their passions.

Benefits at Maven include medical, dental, and vision coverage for employees and their dependents, employer paid short term and long term disability and life insurance, as well as paid parental leave. Maven also offers retirement plans with an employer match and an annual learning and development stipend for all employees.

Compensation 

Salary Range: $150000 - $200000, plus a discretionary bonus.

Career Description

Simplex is looking for smart, curious, and driven individuals to join our technology team. Technology at Simplex is the core of the business. We are a technology company, specializing in high speed trading. We are looking for great people to work on all aspects of our trading system. The job will require lots of programming and working on new projects on a regular basis. Will own the entire development life cycle of projects (develop, simulate, image test, deployment).

What will you be doing?

• Designing FPGA logic to support various trading objectives
• Analyzing the results on a day to day basis and looking for methods to speed up designs

Skills and Experience:

• Verilog/System Verilog
• Working on timing closure of designs/experience with STA
• Experience with developing and verifying FPGA designs
• Experience developing low latency applications

Nice to have Skills:

• Experience with Python a plus
• Experience with ASIC designs a plus
• Experience in equity options/financial markets a plus