ASIC Jobs in Bristol.
All active ASIC roles based in Bristol.
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Fractile is building silicon, systems and software which will redefine the frontier of AI: running the world’s most advanced models at radically higher speed and lower cost. We have an exceptional team across hardware and software capable of bringing about this change, and we are growing fast to meet demand and deliver our product at scale.
Join the team implementing DFT for a large, multi-core AI accelerator ASIC. You will work on scan, ATPG, and memory test, contributing to a robust and scalable test solution while developing your expertise in advanced SoC design.
Key Responsibilities
- Contribute to the DFT architecture of a multi-core AI accelerator SoC
- Drive integration of DFT tools into the EDA flow
- Implement scan insertion, compression, and test logic
- Generate and analyze ATPG patterns for structural faults
- Support MBIST implementation for embedded memories
- Work with physical design to ensure clean scan chain implementation and timing closure
- Develop scripts and automation to improve DFT workflows
- Support silicon bring-up, debug, and test analysis
- Work with test and product engineering teams to bring up and debug ATPG patterns on ATE, supporting production test and yield ramp
Required Experience
- Degree in Electrical Engineering, Computer Engineering, or similar
- Experience in DFT, digital design, or related ASIC development
- Good understanding of scan, ATPG, memory BIST and digital test concepts
- Familiarity with mainstream EDA tools
- Scripting skills (Python, Tcl, or similar)
Profile
- Eager to learn and grow in DFT and large-scale ASIC design
- Detail-oriented and comfortable working with complex systems
- Collaborative and responsive in a fast-moving team
How we work
- Ownership and execution: you will have full agency to drive your work forward
- Rapid iteration: we all work directly with top leadership to move from idea to hardware on ambitious timelines
- Full-stack engagement: hardware, software, silicon, and modelling teams all work closely together to create a product with generational impact
- Optimistic and pragmatic: we possess the will to win, and to do the hard work to get us there
- Team player mentality: the mission is bigger than any of us, and we have the curiosity and technical focus to see the best idea shipped, no matter who’s it is
About us
- Founded in 2022, team of 80+ which is expanding rapidly
- Modern, open offices in London and Bristol
- Collaborative, problem-solving culture built on deep curiosity, entrepreneurial initiative and technical fluency
Export control and security clearance
Certain roles may involve working on technologies subject to export restrictions. Applicants may be required to undergo additional eligibility checks to ensure compliance with applicable law.
Ready to apply?
Apply to Fractile- Drive the physical implementation of ASIC/SoC designs, including floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off.
- Lead or contribute to full-chip execution, block ownership, team leadership, or chip leadership, depending on project needs.
- Work on synthesis, timing analysis (STA), and optimisation to achieve the best PPA metrics.
- Own power planning and analysis, addressing IR drop, electromigration, and related effects.
- Ensure design rule check (DRC), layout vs. schematic (LVS), and other physical verification compliance.
- Collaborate with DFT engineers to integrate design-for-test (DFT) structures into the physical implementation.
- Develop and improve flows in EDA tools such as Cadence Innovus, Synopsys Fusion Compiler, Mentor Graphics Calibre, and others.
- Work closely with RTL and architecture teams to drive design feasibility, constraints, and physical-aware RTL design.
- Mentor junior engineers and contribute to building strong physical design practices across the team.
- Work with advanced AI tools and models to improve productivity, analysis, and design quality.
• Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a related field.
10+ years of experience in physical design for advanced technology nodes (e.g., 7nm, 5nm, or below).
• Strong proficiency in EDA tools for place & route, STA, and sign-off.
• Solid understanding of CMOS technology, semiconductor physics, and process limitations.
• Expertise in timing closure, signal integrity, IR drop analysis, and formal verification.
• Proficiency in scripting languages like TCL, Perl, or Python for automation.
• Proven ability to take ownership of complex designs and drive them to completion.
• Experience mentoring engineers and leading physical design efforts.
• Excellent problem-solving skills, communication, and teamwork in a collaborative design environment.
• Experience in high-performance computing (HPC), AI accelerators, or networking chips.
• Experience or strong interest in leveraging advanced AI tools and models within engineering workflows.
- Ownership and execution: you will have full agency to drive your work forward
- Rapid iteration: we all work directly with top leadership to move from idea to hardware on ambitious timelines
- Full-stack engagement: hardware, software, silicon, and modelling teams all work closely together to create a product with generational impact
- Optimistic and pragmatic: we possess the will to win, and to do the hard work to get us there
- Team player mentality: the mission is bigger than any of us, and we have the curiosity and technical focus to see the best idea shipped, no matter who’s it is
- Founded in 2022, team of 90+ which is expanding rapidly
- Modern, open offices in London and Bristol
- Collaborative, problem-solving culture built on deep curiosity, entrepreneurial initiative and technical fluency
Certain roles may involve working on technologies subject to export restrictions. Applicants may be required to undergo additional eligibility checks to ensure compliance with applicable law.
Ready to apply?
Apply to FractileFractile is building silicon, systems and software which will redefine the frontier of AI: running the world’s most advanced models at radically higher speed and lower cost. We have an exceptional team across hardware and software capable of bringing about this change, and we are growing fast to meet demand and deliver our product at scale.
Define and lead the end-to-end DFT architecture for a large, multi-core AI accelerator SoC, taking ownership from early strategy through silicon bring-up and production. This role combines architectural leadership with hands-on execution, ensuring scalable, power-aware, and high-coverage test solutions while driving alignment across design, physical implementation, and test engineering teams.
Key Responsibilities
- Own and define the DFT architecture for a large AI accelerator SoC (scan, compression, MBIST, LBIST, boundary scan)
- Set DFT strategy, methodology, flow and signoff criteria
- Drive integration of DFT tools and flows into the overall EDA environment
- Define hierarchical DFT approach for multi-core designs and large memory systems
- Define scan architecture, compression strategy, and ATPG approach
- Define memory test and repair strategy for large embedded RAM
- Establish power-aware and at-speed test strategies
- Work closely with RTL and physical design to ensure clean DFT integration and timing closure
- Work with test and product engineering teams to bring up and debug ATPG patterns on ATE, supporting production test and yield ramp
- Mentor and guide DFT engineers
Required Experience
- Strong experience in DFT for complex ASIC/SoC designs (typically 10+ years)
- Proven ownership of DFT architecture on at least one large tapeout
- Deep expertise in scan, compression, ATPG, and MBIST
- Experience with industry tools (Synopsys or Tessent)
- Strong understanding of clocking, resets, power domains, and physical constraints
- Experience with silicon bring-up, debug, and yield ramp
Profile
- Comfortable owning ambiguous, high-impact problems
- Balances architectural thinking with hands-on execution
- Sets direction while staying close to implementation details
About us
- Founded in 2022, team of 80+ which is expanding rapidly
- Modern, open offices in London and Bristol
- Collaborative, problem-solving culture built on deep curiosity, entrepreneurial initiative and technical fluency
Export control and security clearance
Certain roles may involve working on technologies subject to export restrictions. Applicants may be required to undergo additional eligibility checks to ensure compliance with applicable law.
Ready to apply?
Apply to FractileFractile’s mission is to enable a new chapter in the AI revolution. We’re pioneering AI innovation where hardware and software join to create something extraordinary, unlocking the power of the world’s largest language models with speed increases of x100. Our team is rapidly expanding, and we're searching for visionary engineers, scientists, and thinkers who share our passion for pushing boundaries and redefining what's possible. If you're ready to join a dynamic group of innovators shaping AI's future, we want to hear from you!
We are seeking a Physical Design Engineer to contribute to our next-generation chip designs. As a Physical Design Engineer, you will support the implementation of complex IC physical designs, from synthesis to sign-off. You will collaborate with cross-functional teams, including logic design, verification, and process technology, to optimise performance, power, and area (PPA) while ensuring design integrity and manufacturability.
Key Responsibilities:
- Support the physical implementation of ASIC/SoC designs, including floor planning, placement, clock tree synthesis (CTS), routing, and sign-off.
- Work on synthesis, timing analysis (STA), and optimisation to achieve strong PPA metrics.
- Assist in power planning and analysis, addressing IR drop, electromigration, and related effects.
- Ensure design rule check (DRC), layout vs. schematic (LVS), and other physical verification compliance.
- Collaborate with DFT engineers to integrate design-for-test (DFT) structures into the physical implementation.
- Develop flows in EDA tools such as Cadence Innovus, Synopsys Fusion Compiler, Mentor Graphics Calibre, and others.
- Work closely with RTL and architecture teams to support design feasibility, constraints, and physical-aware RTL design.
- Work with advanced AI tools and models to improve productivity, analysis, and design quality.
Preferred Qualifications:
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
- 0–5 years of experience in physical design for advanced technology nodes (e.g., 7nm, 5nm, or below), including internships.
- Familiarity with EDA tools for place & route, STA, and sign-off.
- Basic understanding of CMOS technology, semiconductor physics, and process limitations.
- Exposure to timing closure, signal integrity, IR drop analysis, and formal verification.
- Proficiency in scripting languages like TCL, Perl, or Python for automation is a plus.
- Excellent problem-solving skills, communication, and teamwork in a collaborative design environment.
- Interest in working with advanced AI tools and models as part of the design workflow.
- Experience or coursework in high-performance computing (HPC), AI accelerators, or networking chips is a plus.
Ready to apply?
Apply to FractileFractile’s mission is to enable a new chapter in the AI revolution. We’re pioneering AI innovation where hardware and software join to create something extraordinary, unlocking the power of the world’s largest language models with speed increases of x100. Our team is rapidly expanding, and we're searching for visionary engineers, scientists, and thinkers who share our passion for pushing boundaries and redefining what's possible. If you're ready to join a dynamic group of innovators shaping AI's future, we want to hear from you!
We are seeking a highly skilled Senior/Principal Physical Design Engineer to contribute to our next-generation chip designs. As a Physical Design Engineer, you will be responsible for the end-to-end implementation of complex IC physical designs, from synthesis to sign-off, including opportunities for full-chip ownership. You will collaborate with cross-functional teams, including logic design, verification, and process technology, to optimise performance, power, and area (PPA) while ensuring design integrity and manufacturability.
Key Responsibilities:
- Drive the physical implementation of ASIC/SoC designs, including floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off, with potential responsibility for full-chip execution.
- Work on synthesis, timing analysis (STA), and optimisation to achieve the best PPA metrics.
- Perform power planning and analysis, addressing IR drop, electromigration, and low-power design techniques.
- Ensure design rule check (DRC), layout vs. schematic (LVS), and other physical verification compliance.
- Collaborate with DFT engineers to integrate design-for-test (DFT) structures into the physical implementation.
- Develop flows in EDA tools such as Cadence Innovus, Synopsys Fusion Compiler, Mentor Graphics Calibre, and others.
- Interface with foundries and process engineers to ensure manufacturability and yield optimisation.
- Work closely with RTL and architecture teams to drive design feasibility, constraints, and physical-aware RTL design.
- Work with advanced AI tools and models to improve productivity, analysis, and design quality.
Preferred Qualifications:
- Bachelor’ Master’s or PhD in Electrical Engineering, Computer Engineering, or a related field.
- 7+ years of experience in physical design for advanced technology nodes (e.g., 7nm, 5nm, or below).
- Strong proficiency in EDA tools for place & route, STA, and sign-off.
- Solid understanding of CMOS technology, semiconductor physics, and process limitations.
- Experience with low-power design methodologies, power optimisation techniques, and multi-power domain architectures.
- Expertise in timing closure, signal integrity, IR drop analysis, and formal verification.
- Proficiency in scripting languages like TCL, Perl, or Python for automation.
- Excellent problem-solving skills, communication, and teamwork in a collaborative design environment.
- Experience in high-performance computing (HPC), AI accelerators, or networking chips.
- Experience or strong interest in leveraging advanced AI tools and models within engineering workflows.
Ready to apply?
Apply to FractileAbout Graphcore
At Graphcore, we’re building the future of AI compute.
We’re a team of semiconductor, software and AI experts, with deep experience in creating the complete AI compute stack - from silicon and software to infrastructure at datacenter scale.
As part of the SoftBank Group, backed by significant long-term investment, we are delivering key technology into the fast-growing SoftBank AI ecosystem.
To meet the vast and exciting AI opportunity, Graphcore is expanding its teams around the world.
We are bringing together the brightest minds to solve the toughest problems, in a place where everyone has the opportunity to make an impact on the company, our products and the future of artificial intelligence.
The Team
The Verification team sits within the Silicon Design organisation. We ensure that the RTL delivered by Logical Design and used by Physical Design team implements Graphcore’s architectural needs and meets the company's quality standards. As a Director of Silicon Verification, you will help lead this multi-site organisation, define verification strategies across multiple silicon programs, and drive best in class execution to ensure high-quality, high-performance silicon delivery.
Role Summary
We are seeking a proven leader to help direct Graphcore’s verification strategy and methodologies. This role sets direction for the verification lifecycle including - planning, infrastructure, execution, coverage closure, debug strategy and sign-off for Graphcore’s complex, high performance AI accelerators.
Reporting to the Senior Director of Verification the Director will partner closely with other teams such as Architecture, Logical Design, Physical Design, DFT, Systems as well as Program Management teams to ensure accurate implementation, accelerated debug cycles, high coverage confidence and predictable silicon delivery.
Responsibilities
Leadership & Strategy
- Define the long-term vision, roadmap and strategy for silicon functional verification across all Graphcore silicon programs.
- Build, lead, and develop a high performing, globally distributed verification organisation.
- Establish scalable methodologies, leading edge verification techniques, and best practice processes.
- Drive automation, tooling and infrastructure evolution to improve productivity and verification quality.
- Evaluate emerging tools and technologies and drive adoption to deliver competitive advantage.
Technical Ownership
- Own verification planning, execution and sign off for all RTL blocks and top-level SoCs.
- Oversee definition of test plans including functional coverage targets. Drive close through prioritisation of test content and coverage signoff. Iterate plans to close verification gaps.
- Direct debugging strategies, triage processes and root-cause analysis workflows to enhance team productivity.
- Steer integration of verification technologies including formal methods, simulation acceleration/emulation and system level validation.
Cross Functional Collaboration
- Ensure high quality feedback to other functions within the Silicon Team.
- Partner with Architecture to influence and refine specifications for verifiability and risk reduction.
- Collaborate with Logical Design to align on design intent, architectural corner cases and test scenarios.
- Work closely with Physical Design and DFT teams to ensure coherent verification of interfaces, timing assumptions and test structures.
- Lead post-silicon debug alignment where needed, ensuring learning cycles feed back into RTL and verification methodology.
Execution & Delivery
- Deliver verification sign off on schedule across multiple parallel projects.
- Guide program risk management, resource planning, milestone creation, and verification budgeting.
- Drive consistent metrics-based verification management (structural and functional coverage, bug funnels, simulation performance, CI health, etc.).
- Provide scheduled reports into program management on progress with associated metrics based collaterol.
Essential Skills
- Demonstrated ability to lead, scale and inspire high performing verification teams.
- Extensive verification leadership experience within CPU, GPU, ASIC or SoC environments.
- Deep understanding of modern verification methodologies, flows, and infrastructure.
- Strong capability in SystemVerilog, Python, C++ and Linux-based workflows.
- Expertise in diagnosing complex logic issues across RTL, testbench and system level domains.
- Strong communication, collaboration and stakeholder management skills across global sites.
Desirable Skills
- UVM and advanced SystemVerilog Assertions (SVA).
- Experience with assembly languages and compiler toolchains (LLVM, GCC).
- Knowledge of DVCS tools (e.g., Git).
- Familiarity with distributed compute systems (SGE or other DRMS).
- Experience with XML, XPath/XSLT.
- Web technologies such as HTML/DOM, JavaScript, SQL.
- Exposure to emulation, FPGA prototyping, or formal verification tools.
Benefits
In addition to a competitive salary, Graphcore offers flexible working, a generous annual leave policy, private medical insurance and health cash plan, a dental plan, pension (matched up to 5%), life assurance and income protection. We have a generous parental leave policy and an employee assistance programme (which includes health, mental wellbeing, and bereavement support). We offer a range of healthy food and snacks at our central Bristol office and have our own barista bar! We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments.
Ready to apply?
Apply to Graphcore
About Graphcore
At Graphcore, we’re building the future of AI compute.
We’re a team of semiconductor, software and AI experts, with deep experience in creating the complete AI compute stack - from silicon and software to infrastructure at datacenter scale.
As part of the SoftBank Group, backed by significant long-term investment, we are delivering key technology into the fast-growing SoftBank AI ecosystem.
To meet the vast and exciting AI opportunity, Graphcore is expanding its teams around the world.
We are bringing together the brightest minds to solve the toughest problems, in a place where everyone has the opportunity to make an impact on the company, our products and the future of artificial intelligence.
The Team:
The verification team sits within the Silicon design team and is responsible for ensuring that the RTL created by the logical design team and used by the physical design team matches the architecture specification for Graphcore silicon. The Silicon Verification Lead is responsible for verification activities within Graphcore, helping the team meet the company objectives for quality silicon delivery.
Responsibilities
- Verification planning, specification and closure of functional coverage
- Providing feedback to architects
- Test generation and failure diagnosis/triage
- Contributing to shared verification infrastructure
- Ensuring good communication between sites
Essential skills:
• Verification experience in relevant industry
• Proven leadership and planning skills
• Highly motivated, a self starter, and a team player
• Ability to work across teams and programming languages to find root causes of deep and complex issues
• Experience of the verification process applied in CPU and/or ASIC environments
• System Verilog, Python, C++, Linux
Desirable skills:
• UVM
• SVA
• Assembly languages
• LLVM, GCC
• DVCS e.g. Git
• SGE or other DRMS
• XML and XPath/XSLT
• Web programming – HTML/DOM, Javascript, SQL
Benefits:
In addition to a competitive salary, Graphcore offers flexible working, a generous annual leave policy, private medical insurance and health cash plan, a dental plan, pension (matched up to 5%), life assurance and income protection. We have a generous parental leave policy and an employee assistance programme (which includes health, mental wellbeing, and bereavement support). We offer a range of healthy food and snacks at our central Bristol office and have our own barista bar! We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments
We welcome people of different backgrounds and experiences and are committed to building an inclusive work environment that makes Graphcore a great home for everyone. We are an equal opportunity employer and want to build a work environment where everyone is happy, productive and respectful so they can do their best work. If you have a disability or additional need that requires accommodation, just let us know.
Ready to apply?
Apply to Graphcore
About Graphcore
Graphcore is one of the world’s leading innovators in Artificial Intelligence compute.
It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry.
As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone.
Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation.
The Role:
We are looking to hire Post-Silicon Validation Engineers to join our collaborative, cross-functional development team validating cutting edge, high performance AI chips and platforms. You will play a critical role in supporting new product introductions and post-silicon validation. Working within the Post-Silicon Validation team, you will be involved with bringing first silicon to life, functionally validating it and working closely with many other teams to help it become a fully characterised and working product, reporting project status/progress to program management on a regular basis. You will have the opportunity to, and be responsible for, leading, mentoring, and providing technical guidance to other engineering team members. In this role, you can leverage your experience and industry knowledge to architect and drive implementation of continuous improvements to test infrastructure and processes.
The Post-Silicon Validation team sits within the Architecture and Validation team, we are responsible for validation of new silicon when it returns from manufacture, enabling and supporting the production SW and FW teams to bring up their software and also supporting the Silicon Characterisation team.
Responsibilities and Duties
- Plan, design, develop and debug silicon validation tests in bare metal C/C++ on FPGA/Emulator prior to first silicon
- Deploy silicon validation tests on first silicon and debugging them
- Develop automated test framework and regression test suites in Python to optimize validation efficiency
- Collaborate closely with engineers from many other disciplines on a variety of topics
- Work with Validation and Production Test engineering peers to implement best practices and continuous improvements to test methodologies
- Analyse test results, identify and debug failures/defects
- Contribute to shared test and validation infrastructure
- Provide feedback to architects
Essential skills:
- Strong experience in Bare metal / embedded C/C++
- Good knowledge of digital ASICs
- Be highly motivated, a self starter, and a team player
- Ability to work across teams and programming languages to find root causes of deep and complex issues
- Experience of the post-silicon validation process applied in digital ASIC environments
- Python, Linux
- Excellent communication skills and the ability to collaborate with others to solve problems
- Excellent problem-solving, analytical & diagnostic skills
Desirable skills:
- Driver level experience with one or more of the following is highly desirable:
- PCIe
- Ethernet
- Memory technologies (LPDDR, DDR, HBM, …)
- Other peripherals such as I2C, I3C, SPI, …
- Good knowledge of mixed-signal building blocks such as PLLs, high speed PHYs and IC control/communication protocols is highly desirable
- Experience of Arm CPUs, System IP and debug tools
- Experience of AMBA protocols
- Understanding of ML applications and their workloads
- Experience in Characterization, Failure Analysis, Test Development, Statistical analysis, and Customer Support
Benefits:
In addition to a competitive salary, Graphcore offers flexible working, a generous annual leave policy, private medical insurance and health cash plan, a dental plan, pension (matched up to 5%), life assurance and income protection. We have a generous parental leave policy and an employee assistance programme (which includes health, mental wellbeing, and bereavement support). We offer a range of healthy food and snacks at our central Bristol office and have our own barista bar! We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments.
Ready to apply?
Apply to Graphcore
About Graphcore
At Graphcore, we’re building the future of AI compute. We’re a team of semiconductor, software and AI experts, with deep experience in creating the complete AI compute stack - from silicon and software to infrastructure at datacenter scale. As part of the SoftBank Group, backed by significant long-term investment, we are delivering key technology into the fast-growing SoftBank AI ecosystem.To meet the vast and exciting AI opportunity, Graphcore is expanding its teams around the world. We are bringing together the brightest minds to solve the toughest problems, in a place where everyone has the opportunity to make an impact on the company, our products and the future of artificial intelligence.
Job Summary
As a Technical Programme Manager, you will lead the planning and delivery of complex silicon chip design programmes, focusing on execution across design, implementation and tape-out. You will work across the full development lifecycle, from early product definition through to production readiness.
You will partner with engineering managers and cross-functional teams (ASIC/SoC design, physical design, verification, DFT, CAD, product and operations) to ensure programmes are delivered on time, within scope and to a high standard. This role requires strong technical understanding, programme leadership, and the ability to manage dependencies in a fast-paced semiconductor environment.
The Team
Our Engineering Programme Management team sits at the heart of silicon innovation, enabling delivery of advanced chip technologies. We work across architecture, design, implementation and operations to drive alignment, execution and continuous improvement throughout the silicon lifecycle.
Key Responsibilities
- Lead planning, execution and day-to-day management of silicon design programmes, ensuring milestones and dependencies are clearly defined and tracked.
- Build and maintain integrated schedules across architecture, RTL, verification, physical design, DFT, CAD and tape-out.
- Drive alignment across engineering, product and operations on scope, priorities, resourcing and delivery plans.
- Support execution through key phases including specification, design reviews, implementation, sign-off and tape-out readiness.
- Manage scope changes, assessing impact on schedule and resources while maintaining stakeholder alignment.
- Identify risks, dependencies and challenges early, with clear mitigation and escalation plans.
- Coordinate cross-functional readiness for major milestones such as IP integration, design closure and tape-out.
- Provide regular updates on programme status, risks and recovery plans.
- Drive structured decision-making and accountability across teams.
- Capture lessons learned to improve programme management practices and workflows.
Candidate Profile
Essential
- Bachelor’s degree (or higher) in Electrical/Electronic Engineering, Computer Engineering, Computer Science, or a related field.
- 3–5 years’ experience in programme/project management or technical delivery within semiconductor, ASIC, SoC or hardware environments.
- Experience supporting silicon design programmes across RTL, verification, physical design and tape-out.
- Good understanding of the silicon development lifecycle, including design, integration, implementation and tape-out milestones.
- Experience working with cross-functional engineering teams.
- Strong organisational and planning skills, with the ability to manage dependencies and competing priorities.
- Strong problem-solving skills with a proactive approach to risk and issue management.
- Excellent communication and stakeholder management skills across technical and non-technical audiences.
- Self-motivated, collaborative, and effective in fast-moving environments.
Desirable
- Experience with ASIC/SoC development flows, including design reviews, implementation, sign-off and tape-out.
- Familiarity with RTL, physical design, DFT, CAD or silicon platform teams.
- Understanding of system-level considerations influencing chip design.
- Experience in AI, accelerator, datacentre or high-performance compute silicon programmes.
- Knowledge of semiconductor product development from concept to manufacturing handoff.
Ready to apply?
Apply to Graphcore
Senior/Principal Silicon Verification Engineer
Share this job
About Graphcore
At Graphcore, we’re building the future of AI compute.
We’re a team of semiconductor, software and AI experts, with deep experience in creating the complete AI compute stack - from silicon and software to infrastructure at datacenter scale.
As part of the SoftBank Group, backed by significant long-term investment, we are delivering key technology into the fast-growing SoftBank AI ecosystem.
To meet the vast and exciting AI opportunity, Graphcore is expanding its teams around the world.
We are bringing together the brightest minds to solve the toughest problems, in a place where everyone has the opportunity to make an impact on the company, our products and the future of artificial intelligence.
The Team:
The verification team sits within the Silicon design team and is responsible for ensuring that the RTL created by the logical design team and used by the physical design team matches the architecture specification for Graphcore silicon. The silicon verification engineer is responsible for verification activities within Graphcore, helping the team meet the company objectives for quality silicon delivery.
Responsibilities
- Verification planning, specification and closure of functional coverage
- Providing feedback to architects
- Test generation and failure diagnosis/triage
- Contributing to shared verification infrastructure
- Ensuring good communication between sites
Essential skills:
• Verification experience in relevant industry
• Proven leadership and planning skills
• Highly motivated, a self starter, and a team player
• Ability to work across teams and programming languages to find root causes of deep and complex issues
• Experience of the verification process applied in CPU and/or ASIC environments
• System Verilog, Python, C++, Linux
Desirable skills:
• UVM
• SVA
• Assembly languages
• LLVM, GCC
• DVCS e.g. Git
• SGE or other DRMS
• XML and XPath/XSLT
• Web programming – HTML/DOM, Javascript, SQL
Benefits:
In addition to a competitive salary, Graphcore offers flexible working, a generous annual leave policy, private medical insurance and health cash plan, a dental plan, pension (matched up to 5%), life assurance and income protection. We have a generous parental leave policy and an employee assistance programme (which includes health, mental wellbeing, and bereavement support). We offer a range of healthy food and snacks at our central Bristol office and have our own barista bar! We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments
We welcome people of different backgrounds and experiences and are committed to building an inclusive work environment that makes Graphcore a great home for everyone. We are an equal opportunity employer and want to build a work environment where everyone is happy, productive and respectful so they can do their best work. If you have a disability or additional need that requires accommodation, just let us know.
Ready to apply?
Apply to Graphcore
About Graphcore
At Graphcore, we’re building the future of AI compute.
We’re a team of semiconductor, software and AI experts, with deep experience in creating the complete AI compute stack - from silicon and software to infrastructure at datacenter scale.
As part of the SoftBank Group, backed by significant long-term investment, we are delivering key technology into the fast-growing SoftBank AI ecosystem.
To meet the vast and exciting AI opportunity, Graphcore is expanding its teams around the world.
We are bringing together the brightest minds to solve the toughest problems, in a place where everyone has the opportunity to make an impact on the company, our products and the future of artificial intelligence.
The Team:
The verification team sits within the Silicon design team and is responsible for ensuring that the RTL created by the logical design team and used by the physical design team matches the architecture specification for Graphcore silicon. The silicon verification engineer is responsible for verification activities within Graphcore, helping the team meet the company objectives for quality silicon delivery.
Responsibilities
- Verification planning, specification and closure of functional coverage
- Providing feedback to architects
- Test generation and failure diagnosis/triage
- Contributing to shared verification infrastructure
- Ensuring good communication between sites
Essential skills:
• Verification experience in relevant industry
• Proven leadership and planning skills
• Highly motivated, a self starter, and a team player
• Ability to work across teams and programming languages to find root causes of deep and complex issues
• Experience of the verification process applied in CPU and/or ASIC environments
• System Verilog, Python, C++, Linux
Desirable skills:
• UVM
• SVA
• Assembly languages
• LLVM, GCC
• DVCS e.g. Git
• SGE or other DRMS
• XML and XPath/XSLT
• Web programming – HTML/DOM, Javascript, SQL
Benefits:
In addition to a competitive salary, Graphcore offers flexible working, a generous annual leave policy, private medical insurance and health cash plan, a dental plan, pension (matched up to 5%), life assurance and income protection. We have a generous parental leave policy and an employee assistance programme (which includes health, mental wellbeing, and bereavement support). We offer a range of healthy food and snacks at our central Bristol office and have our own barista bar! We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments
We welcome people of different backgrounds and experiences and are committed to building an inclusive work environment that makes Graphcore a great home for everyone. We are an equal opportunity employer and want to build a work environment where everyone is happy, productive and respectful so they can do their best work. If you have a disability or additional need that requires accommodation, just let us know.
Ready to apply?
Apply to Graphcore