Fractile’s mission is to enable a new chapter in the AI revolution. We’re pioneering AI innovation where hardware and software join to create something extraordinary, unlocking the power of the world’s largest language models with speed increases of x100. Our team is rapidly expanding, and we're searching for visionary engineers, scientists, and thinkers who share our passion for pushing boundaries and redefining what's possible. If you're ready to join a dynamic group of innovators shaping AI's future, we want to hear from you!

We are seeking a highly skilled Senior/Principal Physical Design Engineer to contribute to our next-generation chip designs. As a Physical Design Engineer, you will be responsible for the end-to-end implementation of complex IC physical designs, from synthesis to sign-off, including opportunities for full-chip ownership. You will collaborate with cross-functional teams, including logic design, verification, and process technology, to optimise performance, power, and area (PPA) while ensuring design integrity and manufacturability.

Key Responsibilities:

• Drive the physical implementation of ASIC/SoC designs, including floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off, with potential responsibility for full-chip execution.
• Work on synthesis, timing analysis (STA), and optimisation to achieve the best PPA metrics.
• Perform power planning and analysis, addressing IR drop, electromigration, and low-power design techniques.
• Ensure design rule check (DRC), layout vs. schematic (LVS), and other physical verification compliance.
• Collaborate with DFT engineers to integrate design-for-test (DFT) structures into the physical implementation.
• Develop flows in EDA tools such as Cadence Innovus, Synopsys Fusion Compiler, Mentor Graphics Calibre, and others.
• Interface with foundries and process engineers to ensure manufacturability and yield optimisation.
• Work closely with RTL and architecture teams to drive design feasibility, constraints, and physical-aware RTL design.
• Work with advanced AI tools and models to improve productivity, analysis, and design quality.

Preferred Qualifications:

• Bachelor’ Master’s or PhD in Electrical Engineering, Computer Engineering, or a related field.
• 7+ years of experience in physical design for advanced technology nodes (e.g., 7nm, 5nm, or below).
• Strong proficiency in EDA tools for place & route, STA, and sign-off.
• Solid understanding of CMOS technology, semiconductor physics, and process limitations.
• Experience with low-power design methodologies, power optimisation techniques, and multi-power domain architectures.
• Expertise in timing closure, signal integrity, IR drop analysis, and formal verification.
• Proficiency in scripting languages like TCL, Perl, or Python for automation.
• Excellent problem-solving skills, communication, and teamwork in a collaborative design environment.
• Experience in high-performance computing (HPC), AI accelerators, or networking chips.
• Experience or strong interest in leveraging advanced AI tools and models within engineering workflows.

Fractile’s mission is to enable a new chapter in the AI revolution. We’re pioneering AI innovation where hardware and software join to create something extraordinary, unlocking the power of the world’s largest language models with speed increases of x100. Our team is rapidly expanding, and we're searching for visionary engineers, scientists, and thinkers who share our passion for pushing boundaries and redefining what's possible. If you're ready to join a dynamic group of innovators shaping AI's future, we want to hear from you!

We are seeking a Physical Design Engineer to contribute to our next-generation chip designs. As a Physical Design Engineer, you will support the implementation of complex IC physical designs, from synthesis to sign-off. You will collaborate with cross-functional teams, including logic design, verification, and process technology, to optimise performance, power, and area (PPA) while ensuring design integrity and manufacturability.

Key Responsibilities:

• Support the physical implementation of ASIC/SoC designs, including floor planning, placement, clock tree synthesis (CTS), routing, and sign-off.
• Work on synthesis, timing analysis (STA), and optimisation to achieve strong PPA metrics.
• Assist in power planning and analysis, addressing IR drop, electromigration, and related effects.
• Ensure design rule check (DRC), layout vs. schematic (LVS), and other physical verification compliance.
• Collaborate with DFT engineers to integrate design-for-test (DFT) structures into the physical implementation.
• Develop flows in EDA tools such as Cadence Innovus, Synopsys Fusion Compiler, Mentor Graphics Calibre, and others.
• Work closely with RTL and architecture teams to support design feasibility, constraints, and physical-aware RTL design.
• Work with advanced AI tools and models to improve productivity, analysis, and design quality.

Preferred Qualifications:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 0–5 years of experience in physical design for advanced technology nodes (e.g., 7nm, 5nm, or below), including internships.
• Familiarity with EDA tools for place & route, STA, and sign-off.
• Basic understanding of CMOS technology, semiconductor physics, and process limitations.
• Exposure to timing closure, signal integrity, IR drop analysis, and formal verification.
• Proficiency in scripting languages like TCL, Perl, or Python for automation is a plus.
• Excellent problem-solving skills, communication, and teamwork in a collaborative design environment.
• Interest in working with advanced AI tools and models as part of the design workflow.
• Experience or coursework in high-performance computing (HPC), AI accelerators, or networking chips is a plus.

Fractile’s mission is to enable a new chapter in the AI revolution. We’re pioneering AI innovation where hardware and software join to create something extraordinary, unlocking the power of the world’s largest language models with speed increases of x100. Our team is rapidly expanding, and we're searching for visionary engineers, scientists, and thinkers who share our passion for pushing boundaries and redefining what's possible. If you're ready to join a dynamic group of innovators shaping AI's future, we want to hear from you!

We are seeking a highly skilled Senior/Principal Physical Design Engineer to contribute to our next-generation chip designs. As a Physical Design Engineer, you will be responsible for the end-to-end implementation of complex IC physical designs, from synthesis to sign-off, including opportunities for full-chip ownership. You will collaborate with cross-functional teams, including logic design, verification, and process technology, to optimise performance, power, and area (PPA) while ensuring design integrity and manufacturability.

Key Responsibilities:

• Drive the physical implementation of ASIC/SoC designs, including floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off, with potential responsibility for full-chip execution.
• Work on synthesis, timing analysis (STA), and optimisation to achieve the best PPA metrics.
• Perform power planning and analysis, addressing IR drop, electromigration, and low-power design techniques.
• Ensure design rule check (DRC), layout vs. schematic (LVS), and other physical verification compliance.
• Collaborate with DFT engineers to integrate design-for-test (DFT) structures into the physical implementation.
• Develop flows in EDA tools such as Cadence Innovus, Synopsys Fusion Compiler, Mentor Graphics Calibre, and others.
• Interface with foundries and process engineers to ensure manufacturability and yield optimisation.
• Work closely with RTL and architecture teams to drive design feasibility, constraints, and physical-aware RTL design.
• Work with advanced AI tools and models to improve productivity, analysis, and design quality.

Preferred Qualifications:

• Bachelor’ Master’s or PhD in Electrical Engineering, Computer Engineering, or a related field.
• 7+ years of experience in physical design for advanced technology nodes (e.g., 7nm, 5nm, or below).
• Strong proficiency in EDA tools for place & route, STA, and sign-off.
• Solid understanding of CMOS technology, semiconductor physics, and process limitations.
• Experience with low-power design methodologies, power optimisation techniques, and multi-power domain architectures.
• Expertise in timing closure, signal integrity, IR drop analysis, and formal verification.
• Proficiency in scripting languages like TCL, Perl, or Python for automation.
• Excellent problem-solving skills, communication, and teamwork in a collaborative design environment.
• Experience in high-performance computing (HPC), AI accelerators, or networking chips.
• Experience or strong interest in leveraging advanced AI tools and models within engineering workflows.

Hudson River Trading (HRT) is hiring an AI Researcher to join the HAIL team. HAIL (HRT AI Labs) is the team at HRT responsible for developing and maintaining our most powerful models, which are used by our trading teams to drive a significant fraction of our trading. We are building and deploying "foundation models for markets", that ingest and train on vast amounts of market data, to make predictions about future market state. We are seeking experienced AI researchers to join our team to accelerate our efforts.

Researchers have great independence to pursue the research directions they think would be most impactful as part of a small focused team with minimal bureaucracy. They are enabled by state-of-the-art research clusters with very high GPU-to-researcher ratios, and supported by excellent engineering, hardware, and systems teams to realize their vision. Your work will be directly, clearly, highly impactful on the business, and it will be challenging: this is a field with no easy or obvious solutions. You'll be responsible for improving every part of our models: from featurization of data, to architecture design, to training dynamics, to how trading decisions are made.

Qualifications

• Must have two or more years work experience in deep learning research, for any domain: robotics, biology, chemistry, physics, audio, video, etc.
• Experience translating methods between areas of application is highly valued.
• LLM experience is valuable, but not necessary.
• Strong engineering skills valued, especially any of: GPU kernel development, lower-level Pytorch/JAX development, intermediate C++, FPGA/ASIC experience, HPC experience.

The estimated base salary range for this position is 200,000 to 300,000 USD per year (or local equivalent). The base pay offered may vary depending on multiple individualized factors, including location, job-related knowledge, skills, and experience. 

This role will also be eligible for discretionary performance-based bonuses and a competitive benefits package which includes medical, dental, vision, basic life insurance, and enrollment in our company’s retirement savings plans. Employees will receive sick and parental leave, as well as other paid time off (including 20 vacation days and 10 paid holidays in the US). Please note that benefits and time off policies will vary across non-US locations.

The Hardware team at Hudson River Trading (HRT) creates high performance compute engines using FPGA and ASIC technology to drive low latency trading decisions on global markets. We build custom solutions across the spectrum of speed and smarts: from bespoke circuits to world-class machine learning accelerators.

These high performance designs require even higher performance verification. We are looking for experienced Design Verification (DV) engineers who are skilled at writing testbenches and building verification environments to exercise complex HDL. Our ideal candidate is not only an ace tester, but a practicing toolsmith. You know the EDA landscape and want to be part of a team actively working to rethink, redesign, and surpass the status quo. For example, members of our team are active maintainers of popular open source projects such as Slang, Verilator, and Cocotb.

FPGA and ASIC verification is part of an innovative, growing team at HRT which is integral to the success of our trading. You can expect to always be challenged by the ever-changing financial markets as you work to ensure correctness and robustness of our critical hardware in an extremely fast-paced, real-time environment. No financial experience is necessary.

Responsibilities

• Creating testbenches and tests for our hardware platform, leveraging a hybrid open-source/proprietary, highly flexible environment
• Writing detailed verification plans
• Quickly root-cause RTL bugs
• Collaborating directly with designers for rapid bringup of new projects and debugging of existing designs
• Managing test suites and continuous integration infrastructure
• Developing and improving open-source and internal tools

Qualifications 

• Superb debug and analytical skills 
• Professional experience (2+ years) in RTL functional verification for FPGA or ASIC
• Experience with code and functional coverage collection/analysis
• Experience with SystemVerilog and industry-standard frameworks such as UVM
• Experience with Python
• Comfortable in a Linux environment
• Familiarity with Verilator and/or Cocotb preferred
• C++ experience is a plus
• A bachelor’s degree in computer science, electrical engineering, or a related field

The estimated base salary range for this position is 175,000 to 250,000 USD per year (or local equivalent). The base pay offered may vary depending on multiple individualized factors, including location, job-related knowledge, skills, and experience. This role will also be eligible for discretionary performance-based bonuses and a competitive benefits package.

Hudson River Trading (HRT) is seeking a Physical Design Engineer with a broad, versatile skillset to join our growing Hardware team. In this role, you will help deliver performance-critical ASICs and advance our physical design methodologies on leading-edge process nodes.

The Hardware team at HRT builds high-performance compute engines using FPGA and ASIC technology to drive low-latency trading decisions on global markets. We create custom solutions across the full spectrum of speed and sophistication, from bespoke circuits to world-class machine learning accelerators.

Responsibilities

• Drive design-for-test (DFT) methodologies and implementation 
• Contribute to physical implementation, from RTL handoff through GDSII on advanced process nodes 
• Partner on floorplanning and physical optimization for high-performance, latency-critical designs
• Close timing across multiple modes and corners while optimizing power, performance, and area (PPA)
• Diagnose and resolve physical design issues such as timing bottlenecks, congestion, and IR/EM violations
• Build, maintain, and improve repeatable, automated physical design flows
• Develop scripts and tooling to improve productivity, robustness, and insight into design behavior
• Collaborate closely with RTL, architecture, and other hardware engineers to influence design decisions early

Qualifications

• Experience working in high-performance ASIC design environments
• Strong fundamentals in digital logic, circuit design, and process technology
• Familiarity with DFT concepts and testing methodologies
• Strong scripting and automation skills (Python, Tcl, shell), including parsing and analyzing tool outputs
• Ability to design robust methodologies, diagnose complex failures, and improve physical design flows
• Applied use of statistics in analyzing timing, power, or design data (preferred)
• Hands-on experience with static timing analysis and timing closure methodologies
• Expertise using industry-standard physical design and signoff tools (e.g., Innovus, PrimeTime)

This job is accepting ongoing applications and there is no application deadline.

The estimated base salary range for this position is 200,000 to 300,000 USD per year (or local equivalent). The base pay offered may vary depending on multiple individualized factors, including location, job-related knowledge, skills, and experience.

This role will also be eligible for discretionary performance-based bonuses and a competitive benefits package which includes medical, dental, vision, basic life insurance, and enrollment in our company’s retirement savings plans. Employees will receive sick and parental leave, as well as other paid time off (including 20 vacation days and 10 paid holidays in the US). Please note that benefits and time off policies will vary across non-US locations.

In any materials you submit, you may redact or remove age-identifying information such as age, date of birth, or dates of school attendance or graduation. You will not be penalized for redacting or removing this information.

About the Position

We are looking to hire an ASIC Physical Design Engineer to help us design, test and deploy advanced hardware. As part of our Ultra Low Latency team, you'll have the opportunity to collaborate with people in areas across the firm, including trading, networking and research infrastructure.

This isn't a traditional PD role. We're a small team where everyone works across the chip design process, and we expect our PD engineers to lead with physical design expertise but think like chip designers. You should be comfortable owning a PD flow end-to-end, but also able to read and write RTL and reason about design decisions that cross the front-end/back-end boundary. 

If you've spent your career exclusively in PD, this probably isn't the right fit—but if you've worked across the stack, either because you started as an RTL designer and moved into PD, or because you were on a smaller team where you had to wear multiple hats, we'd love to talk.

We're big believers in the ability of tools to improve the productivity, reliability and day-to-day joy of hardware engineering. That's why we created Hardcaml, a hardware development toolchain embedded in OCaml. We don't expect you to know OCaml (we'll teach you here), but we are looking for hardware engineers who are excited about the advantages that better tools can bring, and are willing to try new things as a result.

About You

• You have 8+ years hands-on experience building and running modern physical design flows (e.g., floorplanning, place and route, timing closure, physical verification, power analysis)
• You don't need to have optimised every last detail of every flow, but you should have broad enough experience across PD that you can own a flow end-to-end and know where the risks are
• Beyond PD, you can read and write RTL and understand how front-end design decisions affect physical implementation—and vice versa; You think about physical design in the context of the overall chip, not just as a downstream consumer of a netlist
• You're interested in using software engineering techniques to improve the hardware design process, and you have experience programming in a high-level language (Python, C++, Haskell, etc.)
• Fluent in English

If you're a recruiting agency and want to partner with us, please reach out to agency-partnerships@janestreet.com.

About the Position

We are looking to hire an experienced ASIC Engineer to help us design, test and deploy advanced hardware designs. As part of our Ultra Low Latency team, you’ll have the opportunity to collaborate with people in areas across the firm, including trading, networking and research infrastructure. We are looking for someone who can contribute to all of our projects and be happy to work on both FPGA-based and ASIC-based technologies.

We’re big believers in the ability of tools to improve the productivity, reliability and day-to-day joy of hardware engineering. That’s why we created Hardcaml, a hardware development toolchain embedded in OCaml. We don’t expect you to know OCaml (we’ll teach you here), but we are looking for hardware engineers who are excited about the advantages that better tools can bring, and are willing to try new things as a result.

About You

• Have 4+ years practical experience in RTL design and verification
• Experienced in ASIC design using either Synopsys or Cadence flows, including at least one of the following:
  
  • Front-end RTL design and synthesis
  • Back-end physical design
  • Verification (including formal)
• Interested in using software engineering techniques to improve the hardware design process, and experience programming in some high-level languages (Python, C++, Java, Haskell, etc.)
• Fluent in English 

If you're a recruiting agency and want to partner with us, please reach out to agency-partnerships@janestreet.com. 

Maven is a market-leading proprietary trading firm deploying its own capital across discretionary, systematic, and market-making strategies. Backed by deep expertise in trading, technology, and research, we are relentlessly focused on improving liquidity across global listed derivatives. Through advanced execution and pricing technologies, we improve how financial markets operate.

Overview:

Where technology meets trading, the Maven FPGA team is pushing the bleeding edge of hardware and proprietary designs to maintain and gain advantage in an increasingly competitive environment. With operations in London, New York, Hong Kong and Chicago, we build technology in support of global trading operations across multiple exchanges, asset classes, and trading strategies. Our teams are small and nimble, with a firm commitment to growth, and a strategic view of investment in people, tools, and the necessary platforms to extend our leadership.

The Role:

Within our team, you will work with traders and technologists to seek and exploit opportunities to gain competitive advantage through FPGA systems. By means of reduced latencies, higher throughput, or increased robustness, you will enable the company to increase the efficiency of existing strategies and open up entirely new trading opportunities previously inaccessible. With a number of greenfield projects in scope, candidates who are proactive and self-driven can grow into leadership roles for the firm’s future. Whilst financial experience is a plus, your engineering talents, problem solving abilities, and eagerness to take on new challenges are of significantly higher importance to us.

The skills you will have:

• SystemVerilog
• Source control management
• 5+ years FPGA experience
• Automated verification
• HLS or other DSP flow experience for FPGA
• Comfortable attacking new and unfamiliar problems
• Interest in trading

Things we would like to see but are not essential:

• Python, TCL
• Low latency design
• ASIC
• Network and packet processing
• Financial market data
• Trading systems
• Software development

WHAT WE OFFER

• Competitive compensation 
• Group Pension plan 
• Annual discretionary bonus 
• Fully catered breakfast, lunch and snacks. 
• 25 days’ annual leave
• Informal dress code 
• Private healthcare and life assurance
• Cycle-to-work scheme
• Monthly company events
• Private Gym