About the Company:

At SK Hynix Memory Solution, we're at the forefront of semiconductor innovation, developing advanced memory solutions that power everything from smartphones to data centers. As a global leader in DRAM and NAND flash technologies, we drive the evolution of advancing mobile technology, empowering cloud computing, and pioneering future technologies. Our cutting-edge memory technologies are essential in today's most advanced electronic devices and IT infrastructure, enabling enhanced performance and user experiences across the digital landscape.

We're looking for innovative minds to join our mission of shaping the future of technology. At SK Hynix Memory, you'll be part of a team that's pioneering breakthrough memory solutions while maintaining a strong commitment to sustainability. We're not just adapting to technological change – we're driving it, with significant investments in artificial intelligence, machine learning, and eco-friendly solutions and operational practices. As we continue to expand our market presence and push the boundaries of what's possible in semiconductor technology, we invite you to be part of our journey to creating the next generation of memory solutions that will define the future of computing.

About The Role

You will join the System on Chip (SoC) Design Team at SK hynix memory solutions America, a group dedicated to delivering best-in-class controllers for high-performance SSDs. This team spans the full design cycle—from micro-architecture and RTL design to timing closure and tapeout readiness—enabling next-generation enterprise and AI data center storage solutions.

Responsibilities

• RTL design (Verilog/SystemVerilog) for IP based on existing module or new specifications.
• Collaborate, create clear documentation and communication with Design Verification, Silicon Validation, and Firmware teams to ensure design quality.

Minimum Qualifications

• Education: Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field.
• Experience: 6+ years of hands-on experience in ASIC/SoC design.
• Proficiency in logic design and micro-architecture; RTL coding in Verilog and/or SystemVerilog language.
• Experience with Lint, CDC, synthesis, power analysis and DV coverage tool.

Preferred Qualifications

• Advanced Education: Master’s or PhD in Electrical Engineering with working experiences.
• Domain Knowledge: NAND Flash, memory controller, datapath design, NVMe, PCIe, UCIe, DDR, CPU subsystem, Network Interconnect, AMBA, error correction code.
• Proficiency in AI tool to generate synthesizable and functional RTL code.
• Knowledge of design verification approaches to enhance verification coverage.

REGARDING COMPENSATION:

SK hynix memory solutions America Inc. offers you the opportunity to apply your skills to exciting projects while working with innovative teams. Our compensation package is complimented by a generous benefits package including medical, dental, vision, life insurance and a company 401(k) match, as well as cafeteria, onsite gym and much more. If you are motivated by technical challenges, we offer a collaborative work environment that encourages career growth.

The salary offered to a selected candidate will be tailored based on several factors, including the location, job grade, relevant knowledge, skills, and experience. We also take into account the internal equity among our current team members to ensure fairness and competitiveness.

Role Overview

Astera Labs is seeking a Physical Design Engineering Manager to lead a team of physical design engineers at our Toronto site, driving the implementation of connectivity ASICs within our Signal Connectivity Group. This group is responsible for products that enable high-speed serial connectivity including PCIe retimers, Ethernet retimers, and signal conditioning solutions—deployed across the world's largest AI clusters and hyperscale data centers.

As an Physical Design Manager Engineering Manager, you will combine hands-on technical leadership with people management, owning physical design execution from RTL to GDSII while building and mentoring a high-performing team. You will drive floorplanning, place-and-route, timing closure, and sign-off for complex designs requiring deep understanding of high-speed physical layer interfaces and SerDes integration at TSMC advanced nodes. This role is fully on-site at our Toronto location.

Basic Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field; Master's preferred.
• 12+ years of experience in physical design implementation of complex SoCs at advanced nodes (7nm and below).
• 2+ years of experience leading teams or projects with demonstrated ability to mentor and develop engineers.
• Hands-on expertise across the physical design flow: synthesis, place-and-route, CTS, extraction, timing closure, EM-IR, DRC/LVS, and equivalence checking.
• Proficiency with Cadence Innovus and/or Synopsys Fusion Compiler/ICC2 and supporting toolchains.
• Strong scripting ability in Tcl, Python, and/or Perl.
• Professional attitude with the ability to prioritize a dynamic list of tasks, plan and prepare for customer meetings in advance, and work with minimal guidance.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind! 

Required Experience

• Build, lead, and mentor a physical design team, owning Physical Design execution and team development for Signal Connectivity Group products.
• Drive block and top-level physical design implementation from floorplan through tapeout for retimer and signal conditioning ASICs.
• Own floorplanning, macro placement, power grid design, clock tree synthesis, and place-and-route for complex blocks and full-chip designs.
• Drive timing closure at both block and full-chip levels, developing and maintaining timing constraints and signoff methodology.
• Ensure DRC/LVS/EM-IR closure and physical verification sign-off to foundry requirements.
• Integrate hard macros, high-speed SerDes, analog IP, and third-party IP blocks, ensuring seamless physical integration at block boundaries.
• Collaborate with RTL, DFT, STA, EMIR, and verification teams to drive design convergence from synthesis through sign-off.
• Work with IP vendors for both RTL and hard-macro integration, ensuring placement constraints and routing guidelines are met.
• Drive team execution, hiring, career development, and sprint planning for the Toronto PD team.
• Establish physical design best practices, flow improvements, and quality checks to scale execution across multiple concurrent programs.
• Coordinate with global PD teams (San Jose, Irvine, Bangalore) to ensure consistent methodology and design quality.
• Experience with Cadence and/or Synopsys physical design tools/flows.
• Familiarity and working knowledge of SystemVerilog/Verilog.

Preferred Experience

• Deep understanding of high-speed SerDes physical layer, including equalization, CDR, and signal integrity considerations impacting physical design.
• Experience with PCIe, Ethernet, or retimer/signal conditioning ASIC implementation.
• Knowledge of physical layer timing challenges specific to high-speed serial interfaces.
• Hands-on experience with UPF-based multi-voltage/multi-power-domain implementations.
• Familiarity with advanced packaging or multi-die integration and its impact on physical design.
• Experience with ECO methodologies and DFT-aware physical design.
• Knowledge of EMIR-aware implementation techniques and early-stage IR drop mitigation.
• Track record of building and scaling physical design teams through multiple tapeouts.
• Knowledge of agentic AI solutions for EDA automation.

Salary range is CAD $180,000 to $220,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives, and benefits.

SPACE SYSTEMS

At Rocket Lab, we’re not just launching rockets — we're building the future of space. Our Space Systems team builds everything from complete spacecraft, precision payloads to the components and subsystems that allow them to thrive in space, like solar panels, flight software, star trackers, optical systems, separation systems, radios, and more.

Our Space Systems team has enabled more than 1,700 missions, ranging from interplanetary exploration, in-space manufacturing to national security and defense initiatives. The team has built spacecraft, payloads, and components for missions to the Moon and Mars, working with partners including NASA, the Space Development Agency, and the U.S. Space Force. Whether it’s a single high-performance spacecraft, constellation, or the vertically integrated components that help them get to space — our world class Space Systems team is empowering some of the boldest and most ambitious space missions.

SENIOR FPGA ENGINEER II

Rocket Lab’s Optical Systems division solves mission-critical space domain and Intelligence, Surveillance, and Reconnaissance (ISR) challenges for Department of Defense (DoD) and Intelligence Community (IC) customers. Our vision is to revolutionize the space-based payload market with innovative and novel designs for space, terrestrial, and airborne environments. Building on more than 20 years of electro-optical and infrared systems innovation from Geost, Optical Systems delivers solutions to the warfighter for responsive, scalable sensing solutions across all orbital domains.

You will be a Senior FPGA Engineer II based at our Rocket Lab Optical Systems worksites in Long Beach, CA; Littleton, CO; Phoenix, AZ; Albuquerque, NM; Chantilly, VA; and Tucson, AZ. You will design Xilinx FPGAs in VHDL to support Tranche 3 of the Space Development Agency’s Proliferated Warfighter Space Architecture (PWSA).

WHAT YOU’LL GET TO DO

• Work with the hardware design team on requirements.
• Complete FPGA logic design, coding, simulation, and testing.
• Support hardware and software development teams in bring-up and test of products.
• Provide subject-matter expertise regarding design and automated test development procedures to customers and production support team.
• Perform research and analysis of data, such as customer proposed specifications, datasheets, or manuals to determine design approach and/or feasibility.
• Execute debugging of the design in the lab.
• Perform synthesis, implementation, and timing analysis.

YOU’LL BRING THESE QUALIFICATIONS AS SENIOR FPGA ENGINEER II:

• Bachelor’s degree in computer engineering or electrical engineering or equivalent discipline with 8+ years of experience
• Experience in FPGA firmware design with VHDL.
• Ability to obtain and maintain an U.S. Government Security Clearance

THESE QUALIFICATIONS WOULD BE NICE TO HAVE: 

• Experience with Xilinx/AMD Versal architecture
• Experience with FPGAs and embedded systems in a radiation environment, including SEU/SEL impact and mitigation.
• Experience in FPGA- or ASIC-based image processing algorithms.
• Experience in both creating IP from scratch in RTL and integrating existing IP into RTL and block designs.
• Familiarity with C, Python or MATLAB and/or experience translating algorithms from a scripted language to HDL.
• Experience with software interfaces including interrupts and DMA.
• Experience with DDR4, Aurora, and high-speed transceiver design and verification.
• Familiarity with AXI Stream and AXI Memory Mapped interfaces.
• PCB design and schematic capture and layout with tools such as Altium Designer.

ADDITIONAL REQUIREMENTS:

• Specific vision abilities required by this job include close vision, distance vision, peripheral vision, depth perception, and the ability to focus
• Regularly required to sit, use hands and fingers, operate computer keyboard and controls, and communicate verbally and in writing
• Must be physically able to commute to buildings

SPACE SYSTEMS

At Rocket Lab, we’re not just launching rockets — we're building the future of space. Our Space Systems team builds everything from complete spacecraft, precision payloads to the components and subsystems that allow them to thrive in space, like solar panels, flight software, star trackers, optical systems, separation systems, radios, and more.

Our Space Systems team has enabled more than 1,700 missions, ranging from interplanetary exploration, in-space manufacturing to national security and defense initiatives. The team has built spacecraft, payloads, and components for missions to the Moon and Mars, working with partners including NASA, the Space Development Agency, and the U.S. Space Force. Whether it’s a single high-performance spacecraft, constellation, or the vertically integrated components that help them get to space — our world class Space Systems team is empowering some of the boldest and most ambitious space missions.

SENIOR FPGA ENGINEER II

Rocket Lab’s Optical Systems division solves mission-critical space domain and Intelligence, Surveillance, and Reconnaissance (ISR) challenges for Department of Defense (DoD) and Intelligence Community (IC) customers. Our vision is to revolutionize the space-based payload market with innovative and novel designs for space, terrestrial, and airborne environments. Building on more than 20 years of electro-optical and infrared systems innovation from Geost, Optical Systems delivers solutions to the warfighter for responsive, scalable sensing solutions across all orbital domains.

You will be a Senior FPGA Engineer II based at our Rocket Lab Optical Systems worksites in Long Beach, CA; Littleton, CO; Phoenix, AZ; Albuquerque, NM; Chantilly, VA; and Tucson, AZ. You will design Xilinx FPGAs in VHDL to support Tranche 3 of the Space Development Agency’s Proliferated Warfighter Space Architecture (PWSA).

WHAT YOU’LL GET TO DO

• Work with the hardware design team on requirements.
• Complete FPGA logic design, coding, simulation, and testing.
• Support hardware and software development teams in bring-up and test of products.
• Provide subject-matter expertise regarding design and automated test development procedures to customers and production support team.
• Perform research and analysis of data, such as customer proposed specifications, datasheets, or manuals to determine design approach and/or feasibility.
• Execute debugging of the design in the lab.
• Perform synthesis, implementation, and timing analysis.

YOU’LL BRING THESE QUALIFICATIONS AS SENIOR FPGA ENGINEER II:

• Bachelor’s degree in computer engineering or electrical engineering or equivalent discipline with 8+ years of experience
• Experience in FPGA firmware design with VHDL.
• Ability to obtain and maintain an U.S. Government Security Clearance

THESE QUALIFICATIONS WOULD BE NICE TO HAVE: 

• Experience with Xilinx/AMD Versal architecture
• Experience with FPGAs and embedded systems in a radiation environment, including SEU/SEL impact and mitigation.
• Experience in FPGA- or ASIC-based image processing algorithms.
• Experience in both creating IP from scratch in RTL and integrating existing IP into RTL and block designs.
• Familiarity with C, Python or MATLAB and/or experience translating algorithms from a scripted language to HDL.
• Experience with software interfaces including interrupts and DMA.
• Experience with DDR4, Aurora, and high-speed transceiver design and verification.
• Familiarity with AXI Stream and AXI Memory Mapped interfaces.
• PCB design and schematic capture and layout with tools such as Altium Designer.

ADDITIONAL REQUIREMENTS:

• Specific vision abilities required by this job include close vision, distance vision, peripheral vision, depth perception, and the ability to focus
• Regularly required to sit, use hands and fingers, operate computer keyboard and controls, and communicate verbally and in writing
• Must be physically able to commute to buildings

SPACE SYSTEMS

At Rocket Lab, we’re not just launching rockets — we're building the future of space. Our Space Systems team builds everything from complete spacecraft, precision payloads to the components and subsystems that allow them to thrive in space, like solar panels, flight software, star trackers, optical systems, separation systems, radios, and more.

Our Space Systems team has enabled more than 1,700 missions, ranging from interplanetary exploration, in-space manufacturing to national security and defense initiatives. The team has built spacecraft, payloads, and components for missions to the Moon and Mars, working with partners including NASA, the Space Development Agency, and the U.S. Space Force. Whether it’s a single high-performance spacecraft, constellation, or the vertically integrated components that help them get to space — our world class Space Systems team is empowering some of the boldest and most ambitious space missions.

SENIOR FPGA ENGINEER II

Rocket Lab’s Optical Systems division solves mission-critical space domain and Intelligence, Surveillance, and Reconnaissance (ISR) challenges for Department of Defense (DoD) and Intelligence Community (IC) customers. Our vision is to revolutionize the space-based payload market with innovative and novel designs for space, terrestrial, and airborne environments. Building on more than 20 years of electro-optical and infrared systems innovation from Geost, Optical Systems delivers solutions to the warfighter for responsive, scalable sensing solutions across all orbital domains.

You will be a Senior FPGA Engineer II based at our Rocket Lab Optical Systems our headquarters in Long Beach, CA and at our worksites in Littleton, CO; Phoenix, AZ; Albuquerque, NM; Chantilly, VA; and Tucson, AZ. You will design Xilinx FPGAs in VHDL to support Tranche 3 of the Space Development Agency’s Proliferated Warfighter Space Architecture (PWSA).

WHAT YOU’LL GET TO DO

• Work with the hardware design team on requirements.
• Complete FPGA logic design, coding, simulation, and testing.
• Support hardware and software development teams in bring-up and test of products.
• Provide subject-matter expertise regarding design and automated test development procedures to customers and production support team.
• Perform research and analysis of data, such as customer proposed specifications, datasheets, or manuals to determine design approach and/or feasibility.
• Execute debugging of the design in the lab.
• Perform synthesis, implementation, and timing analysis.

YOU’LL BRING THESE QUALIFICATIONS AS SENIOR FPGA ENGINEER II:

• Bachelor’s degree in computer engineering or electrical engineering or equivalent discipline with 8+ years of experience
• Experience in FPGA firmware design with VHDL.
• Ability to obtain and maintain an U.S. Government Security Clearance

THESE QUALIFICATIONS WOULD BE NICE TO HAVE: 

• Experience with Xilinx/AMD Versal architecture
• Experience with FPGAs and embedded systems in a radiation environment, including SEU/SEL impact and mitigation.
• Experience in FPGA- or ASIC-based image processing algorithms.
• Experience in both creating IP from scratch in RTL and integrating existing IP into RTL and block designs.
• Familiarity with C, Python or MATLAB and/or experience translating algorithms from a scripted language to HDL.
• Experience with software interfaces including interrupts and DMA.
• Experience with DDR4, Aurora, and high-speed transceiver design and verification.
• Familiarity with AXI Stream and AXI Memory Mapped interfaces.
• PCB design and schematic capture and layout with tools such as Altium Designer.

ADDITIONAL REQUIREMENTS:

• Specific vision abilities required by this job include close vision, distance vision, peripheral vision, depth perception, and the ability to focus
• Regularly required to sit, use hands and fingers, operate computer keyboard and controls, and communicate verbally and in writing
• Must be physically able to commute to buildings

SPACE SYSTEMS

At Rocket Lab, we’re not just launching rockets — we're building the future of space. Our Space Systems team builds everything from complete spacecraft, precision payloads to the components and subsystems that allow them to thrive in space, like solar panels, flight software, star trackers, optical systems, separation systems, radios, and more.

Our Space Systems team has enabled more than 1,700 missions, ranging from interplanetary exploration, in-space manufacturing to national security and defense initiatives. The team has built spacecraft, payloads, and components for missions to the Moon and Mars, working with partners including NASA, the Space Development Agency, and the U.S. Space Force. Whether it’s a single high-performance spacecraft, constellation, or the vertically integrated components that help them get to space — our world class Space Systems team is empowering some of the boldest and most ambitious space missions.

SENIOR FPGA ENGINEER II

Rocket Lab’s Optical Systems division solves mission-critical space domain and Intelligence, Surveillance, and Reconnaissance (ISR) challenges for Department of Defense (DoD) and Intelligence Community (IC) customers. Our vision is to revolutionize the space-based payload market with innovative and novel designs for space, terrestrial, and airborne environments. Building on more than 20 years of electro-optical and infrared systems innovation from Geost, Optical Systems delivers solutions to the warfighter for responsive, scalable sensing solutions across all orbital domains.

You will be a Senior FPGA Engineer II based at our Rocket Lab Optical Systems worksites in Long Beach, CA; Littleton, CO; Phoenix, AZ; Albuquerque, NM; Chantilly, VA; and Tucson, AZ. You will design Xilinx FPGAs in VHDL to support Tranche 3 of the Space Development Agency’s Proliferated Warfighter Space Architecture (PWSA).

WHAT YOU’LL GET TO DO

• Work with the hardware design team on requirements.
• Complete FPGA logic design, coding, simulation, and testing.
• Support hardware and software development teams in bring-up and test of products.
• Provide subject-matter expertise regarding design and automated test development procedures to customers and production support team.
• Perform research and analysis of data, such as customer proposed specifications, datasheets, or manuals to determine design approach and/or feasibility.
• Execute debugging of the design in the lab.
• Perform synthesis, implementation, and timing analysis.

YOU’LL BRING THESE QUALIFICATIONS AS SENIOR FPGA ENGINEER II:

• Bachelor’s degree in computer engineering or electrical engineering or equivalent discipline with 8+ years of experience
• Experience in FPGA firmware design with VHDL.
• Ability to obtain and maintain an U.S. Government Security Clearance

THESE QUALIFICATIONS WOULD BE NICE TO HAVE: 

• Experience with Xilinx/AMD Versal architecture
• Experience with FPGAs and embedded systems in a radiation environment, including SEU/SEL impact and mitigation.
• Experience in FPGA- or ASIC-based image processing algorithms.
• Experience in both creating IP from scratch in RTL and integrating existing IP into RTL and block designs.
• Familiarity with C, Python or MATLAB and/or experience translating algorithms from a scripted language to HDL.
• Experience with software interfaces including interrupts and DMA.
• Experience with DDR4, Aurora, and high-speed transceiver design and verification.
• Familiarity with AXI Stream and AXI Memory Mapped interfaces.
• PCB design and schematic capture and layout with tools such as Altium Designer.

ADDITIONAL REQUIREMENTS:

• Specific vision abilities required by this job include close vision, distance vision, peripheral vision, depth perception, and the ability to focus
• Regularly required to sit, use hands and fingers, operate computer keyboard and controls, and communicate verbally and in writing
• Must be physically able to commute to buildings

SPACE SYSTEMS

At Rocket Lab, we’re not just launching rockets — we're building the future of space. Our Space Systems team builds everything from complete spacecraft, precision payloads to the components and subsystems that allow them to thrive in space, like solar panels, flight software, star trackers, optical systems, separation systems, radios, and more.

Our Space Systems team has enabled more than 1,700 missions, ranging from interplanetary exploration, in-space manufacturing to national security and defense initiatives. The team has built spacecraft, payloads, and components for missions to the Moon and Mars, working with partners including NASA, the Space Development Agency, and the U.S. Space Force. Whether it’s a single high-performance spacecraft, constellation, or the vertically integrated components that help them get to space — our world class Space Systems team is empowering some of the boldest and most ambitious space missions.

SENIOR FPGA ENGINEER II

Rocket Lab’s Optical Systems division solves mission-critical space domain and Intelligence, Surveillance, and Reconnaissance (ISR) challenges for Department of Defense (DoD) and Intelligence Community (IC) customers. Our vision is to revolutionize the space-based payload market with innovative and novel designs for space, terrestrial, and airborne environments. Building on more than 20 years of electro-optical and infrared systems innovation from Geost, Optical Systems delivers solutions to the warfighter for responsive, scalable sensing solutions across all orbital domains.

As a Senior FPGA Engineer II based at our Rocket Lab Optical Systems worksites in Chantilly, VA, you will support Tranche 3 of the U.S. Space Development Agency's (SDA) Proliferated Warfighter Space Architecture (PWSA) by designing FPGAs for spacecraft payloads.

WHAT YOU’LL GET TO DO

• Work with the hardware design team on requirements.
• Complete FPGA logic design, coding, simulation, and testing.
• Support hardware and software development teams in bring-up and test of products.
• Provide subject-matter expertise regarding design and automated test development procedures to customers and production support team.
• Perform research and analysis of data, such as customer proposed specifications, datasheets, or manuals to determine design approach and/or feasibility.
• Execute debugging of the design in the lab.
• Perform synthesis, implementation, and timing analysis.

YOU’LL BRING THESE QUALIFICATIONS AS SENIOR FPGA ENGINEER II:

• Bachelor’s degree in computer engineering or electrical engineering or equivalent discipline with 8+ years of experience
• Experience in FPGA firmware design with VHDL.
• Ability to obtain and maintain an U.S. Government Security Clearance

THESE QUALIFICATIONS WOULD BE NICE TO HAVE: 

• Experience with Xilinx/AMD Versal architecture
• Experience with FPGAs and embedded systems in a radiation environment, including SEU/SEL impact and mitigation.
• Experience in FPGA- or ASIC-based image processing algorithms.
• Experience in both creating IP from scratch in RTL and integrating existing IP into RTL and block designs.
• Familiarity with C, Python or MATLAB and/or experience translating algorithms from a scripted language to HDL.
• Experience with software interfaces including interrupts and DMA.
• Experience with DDR4, Aurora, and high-speed transceiver design and verification.
• Familiarity with AXI Stream and AXI Memory Mapped interfaces.
• PCB design and schematic capture and layout with tools such as Altium Designer.

ADDITIONAL REQUIREMENTS:

• Specific vision abilities required by this job include close vision, distance vision, peripheral vision, depth perception, and the ability to focus
• Regularly required to sit, use hands and fingers, operate computer keyboard and controls, and communicate verbally and in writing
• Must be physically able to commute to buildings

SPACE SYSTEMS

At Rocket Lab, we’re not just launching rockets — we're building the future of space. Our Space Systems team builds everything from complete spacecraft, precision payloads to the components and subsystems that allow them to thrive in space, like solar panels, flight software, star trackers, optical systems, separation systems, radios, and more.

Our Space Systems team has enabled more than 1,700 missions, ranging from interplanetary exploration, in-space manufacturing to national security and defense initiatives. The team has built spacecraft, payloads, and components for missions to the Moon and Mars, working with partners including NASA, the Space Development Agency, and the U.S. Space Force. Whether it’s a single high-performance spacecraft, constellation, or the vertically integrated components that help them get to space — our world class Space Systems team is empowering some of the boldest and most ambitious space missions.

SENIOR FPGA ENGINEER II

Rocket Lab’s Optical Systems division solves mission-critical space domain and Intelligence, Surveillance, and Reconnaissance (ISR) challenges for Department of Defense (DoD) and Intelligence Community (IC) customers. Our vision is to revolutionize the space-based payload market with innovative and novel designs for space, terrestrial, and airborne environments. Building on more than 20 years of electro-optical and infrared systems innovation from Geost, Optical Systems delivers solutions to the warfighter for responsive, scalable sensing solutions across all orbital domains.

You will be a Senior FPGA Engineer II based at our Rocket Lab Optical Systems worksites in Long Beach, CA; Littleton, CO; Phoenix, AZ; Albuquerque, NM; Chantilly, VA; and Tucson, AZ. You will design Xilinx FPGAs in VHDL to support Tranche 3 of the Space Development Agency’s Proliferated Warfighter Space Architecture (PWSA).

WHAT YOU’LL GET TO DO

• Work with the hardware design team on requirements.
• Complete FPGA logic design, coding, simulation, and testing.
• Support hardware and software development teams in bring-up and test of products.
• Provide subject-matter expertise regarding design and automated test development procedures to customers and production support team.
• Perform research and analysis of data, such as customer proposed specifications, datasheets, or manuals to determine design approach and/or feasibility.
• Execute debugging of the design in the lab.
• Perform synthesis, implementation, and timing analysis.

YOU’LL BRING THESE QUALIFICATIONS AS SENIOR FPGA ENGINEER II:

• Bachelor’s degree in computer engineering or electrical engineering or equivalent discipline with 8+ years of experience
• Experience in FPGA firmware design with VHDL.
• Ability to obtain and maintain an U.S. Government Security Clearance

THESE QUALIFICATIONS WOULD BE NICE TO HAVE: 

• Experience with Xilinx/AMD Versal architecture
• Experience with FPGAs and embedded systems in a radiation environment, including SEU/SEL impact and mitigation.
• Experience in FPGA- or ASIC-based image processing algorithms.
• Experience in both creating IP from scratch in RTL and integrating existing IP into RTL and block designs.
• Familiarity with C, Python or MATLAB and/or experience translating algorithms from a scripted language to HDL.
• Experience with software interfaces including interrupts and DMA.
• Experience with DDR4, Aurora, and high-speed transceiver design and verification.
• Familiarity with AXI Stream and AXI Memory Mapped interfaces.
• PCB design and schematic capture and layout with tools such as Altium Designer.

ADDITIONAL REQUIREMENTS:

• Specific vision abilities required by this job include close vision, distance vision, peripheral vision, depth perception, and the ability to focus
• Regularly required to sit, use hands and fingers, operate computer keyboard and controls, and communicate verbally and in writing
• Must be physically able to commute to buildings

About Akuna: 

Akuna Capital is an innovative trading firm with a strong focus on collaboration, cutting-edge technology, data driven solutions, and automation. We specialize in providing liquidity as an options market-maker – meaning we are committed to providing competitive quotes that we are willing to both buy and sell. To do this successfully, we design and implement our own low latency technologies, trading strategies, and mathematical models. 

Our Founding Partners first conceptualized Akuna in their hometown of Sydney. They opened the firm’s first office in 2011 in the heart of the derivatives industry and the options capital of the world – Chicago. Today, Akuna is proud to operate from additional offices in Sydney, Shanghai, London, and Singapore. 

What you’ll do as a Senior FPGA Engineer at Akuna: 

We are looking for Senior FPGA Engineers to accelerate various portions of our trading platform. Members of the Hardware Development team will work with cutting-edge FPGA technology and high-performance computing architectures – owning projects end-to-end and making Akuna’s systems faster and smarter. In this role, you will: 

• Own projects - driving project progression from inception, requirements, architecture, design entry, timing closure and verification
• Partner closely with the Low Latency, Trading and other teams to foster and develop ideas that performance 
• Develop and maintain RTL in Verilog/SystemVerilog
• Write and maintain verification environments
• Design optimization for timing closure
• Develop and maintain project documentation 

Qualities that make great candidates: 

• 10+ years of experience in FPGA or ASIC digital logic design – network traffic experience a strong plus
• Deep Verilog/SystemVerilog or VHDL skills
• Solid grasp of static timing analysis, synthesis, and place-and-route tools  
• Familiarity with algorithms, data structures, and verification/unit testing workflows
• Python and Bash scripting fluency
• Enthusiasm for collaboration with other FPGA team members as well as members from software and trading teams
• Open mindedness for novel development approaches and architectures
• Bachelor’s degree in Computer or Electrical Engineering, or related field; master’s degree a plus 
• The ability to react quickly and accurately to rapidly changing market conditions, including the ability to quickly and accurately respond and/or solve math and coding problems are essential functions of the role

In addition to technical skillsets, Akuna values the unique perspectives people can bring to the table to collaboratively solve complex problems and drive Akuna forward. We want everyone to feel empowered to apply. We welcome your application and encourage you to take the first steps toward your future with us!

In accordance with Illinois Equal Pay Act, the minimum base salary starts at $145,000. Exact compensation offered may vary based on many factors including, but not limited to, the candidate’s experience, qualifications, and skill set. This role is also eligible for a discretionary performance bonus as part of the total compensation package and includes a comprehensive benefits package that may encompass employer-paid medical, dental, vision, retirement contributions, paid time off, and other benefits. The minimum base salary herein was determined in good faith by Akuna Capital LLC.

Staff Data Scientist -  Experimentation & Measurement 

Overview:

As a Staff Data Scientist on the Decision Science team at PlayStation, you will take a leading role in designing and interpreting experiments that evaluate the impact of key initiatives and programs. You’ll help shape how millions of players around the world experience PlayStation by bringing statistical rigor, clear measurement strategies, and deep causal inference expertise to some of the most critical initiatives across the company. This highly visible role will advance our experimentation practices and ensure that data-driven insights inform the way we build, market, and evolve our products.

What You’ll Be Doing:

• Design, execute, and interpret A/B tests and quasi-experiments, and apply advanced causal inference methods when experimentation isn’t feasible.
• Partner with cross-functional teams (product, engineering, marketing) to embed experimentation into development and iteration cycles and communicate results with the company’s senior leadership.
• Mentor and guide other Data Scientists, providing thought leadership and technical direction.
• Serve as a thought leader on best practices for hypothesis development, metric selection, test structure, and results communication.
• Help define and contribute to centralized experimentation frameworks, tools, and documentation to scale best practices across the company.
• Independently extract, transform, and analyze data from complex systems using SQL, Python, and other analytics tools.
• Communicate findings clearly to technical and non-technical stakeholders, helping drive business decisions with rigor and clarity.
• Stay current on new methodologies in experimentation and causal analysis, and bring fresh perspectives to the team’s work.
• Your insights will directly influence how PlayStation builds, markets, and evolves products across our ecosystem.

asic Requirements:

• Bachelor’s degree or equivalent.
• 6+ years of experience in a data science experimentation/causal inference-focused role (4+ with PhD).
• Deep expertise in A/B testing and causal inference, including quasi-experimental methods.
• Proficiency in SQL and Python for data extraction, transformation, and analysis.
• Broad and applied knowledge of statistical techniques.
• Experience with machine learning modeling is a plus.
• Proven ability to influence product and business decisions through clear, actionable insights.
• Experience contributing to or developing experimentation frameworks, best practices, or internal tooling.
  
  Preferred Requirements:
  • Master’s or PhD in Statistics, Economics, or Econometrics. Other degrees in quantitative disciplines may be considered.
  • Bonus: Interest in or knowledge of video games, gaming platforms, or player behavior.

#LI-KC

At Tenstorrent, we build open, state of art compute for AI and RISC‑V. You will create and own our quality organization across hardware systems and custom silicon, setting the standards that let us scale fast without sacrificing reliability. This role requires regular domestic and international travel to suppliers, contract manufacturers, and Tenstorrent sites.

This role is hybrid, based out of Toronto, ON.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• 7+ years driving hardware or semiconductor quality across design, process, incoming, supplier, and systems.
• Experienced with servers, PCs, and/or PCIe cards, plus ASIC or custom silicon quality.
• Comfortable leading global CM and supplier audits and traveling frequently worldwide.
• You have experience working in companies that have transitioned from R&D to Product focused. 
• Have built a quality org and QMS from zero and can explain your design choices.

What We Need

• Build the quality team from scratch, including org design, hiring, and cross‑functional ownership.
• Own the QMS, including ISO 9001, documentation, audits, KPIs, and continuous improvement.
•  Drive Design for Quality for hardware and silicon, from bring‑up through post‑silicon validation.
•  Define manufacturing controls, FMEAs, control plans, NPI quality gates, and supplier quality programs.

What You Will Learn

• How to apply open, state of art compute to demanding hardware and silicon quality problems.
• To shape quality culture, metrics, and supplier relationships for a fast‑growing silicon company.
• How reliability data, field returns, and standards like JEDEC and IPC drive product decisions.
• To scale quality systems that support hyperscaler, cloud, and semiconductor startup customers.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

PsiQuantum’s mission is to build the first useful quantum computers—machines capable of delivering the breakthroughs the field has long promised. Since our founding in 2016, our singular focus has been to build and deploy million-qubit, fault-tolerant quantum systems. 

Quantum computers harness the laws of quantum mechanics to solve problems that even the most advanced supercomputers or AI systems will never reach. Their impact will span energy, pharmaceuticals, finance, agriculture, transportation, materials, and other foundational industries. 

Our architecture and approach is based on silicon photonics. By leveraging the advanced semiconductor manufacturing industry—including partners like GlobalFoundries—we use the same high-volume processes that already produce billions of chips for telecom and consumer electronics. Photonics offers natural advantages for scale: photons don’t feel heat, are immune to electromagnetic interference, and integrate with existing cryogenic cooling and standard fiber-optic infrastructure. 

In 2024, PsiQuantum announced government-funded projects to support the build-out of our first utility-scale quantum computers in Brisbane, Australia, and Chicago, Illinois. These initiatives reflect a growing recognition that quantum computing will be strategically and economically defining—and that now is the time to scale. 

PsiQuantum also develops the algorithms and software needed to make these systems commercially valuable. Our application, software, and industry teams work directly with leading Fortune 500 companies—including Lockheed Martin, Mercedes-Benz, Boehringer Ingelheim, and Mitsubishi Chemical—to prepare quantum solutions for real-world impact. 

Quantum computing is not an extension of classical computing. It represents a fundamental shift—and a path to mastering challenges that cannot be solved any other way. The potential is enormous, and we have a clear path to make it real. 

Come join us. 

Job Summary:

PsiQuantum is seeking a Quantum Electronics Engineer to support the development of advanced electronic and electro-optic systems for quantum computing.

In this role, you will work closely with senior engineers to design and implement high-performance electronic solutions for controlling and reading out quantum photonic hardware. This includes RF design, electro-optic modulation, and low-latency control systems.

Responsibilities:

• Design and develop RF and high-speed electronic systems for quantum hardware applications.
• Support the design of electro-optic (EO) packages and modulator driving electronics.
• Develop low-latency electronic solutions for quantum system control and readout.
• Work on readout systems for superconducting nanowire single-photon detectors (SNSPDs).
• Collaborate with photonics and quantum teams to integrate electronics with optical systems.
• Assist in FPGA-based system design and implementation for control and data acquisition.
• Participate in debugging and optimization of complex quantum hardware systems.

Experience/Qualifications:

• Degree (PhD or equivalent experience) in Electrical Engineering, Physics, or a related field.
• Strong background in RF and high-speed electronic design.
• Experience working with electro-optic systems or photonic hardware.
• Understanding of signal integrity, noise, and timing in high-performance systems.
• Hands-on laboratory experience with electronic test and measurement equipment.

Desired Skills:

• Experience designing electronics for quantum or cryogenic systems.
• Familiarity with FPGA development and programming.
• Knowledge of superconducting nanowire detectors and readout electronics.
• Experience with low-latency system design and high-speed data acquisition.
• Experience with ASIC design or collaboration with ASIC development teams for high-speed or low-latency electronic systems.

PsiQuantum provides equal employment opportunity for all applicants and employees. PsiQuantum does not unlawfully discriminate on the basis of race, color, religion, sex (including pregnancy, childbirth, or related medical conditions), gender identity, gender expression, national origin, ancestry, citizenship, age, physical or mental disability, military or veteran status, marital status, domestic partner status, sexual orientation, genetic information, or any other basis protected by applicable laws.

Note: PsiQuantum will only reach out to you using an official PsiQuantum email address and will never ask you for bank account information as part of the interview process. Please report any suspicious activity to recruiting@psiquantum.com.

We are not accepting unsolicited resumes from employment agencies.

Anduril’s Electrical Engineering Team is seeking a Wireless Systems Principal Engineer with a strong background in modulation/demodulation, forward error correction, multiple access, duplexing schemes used in wireless communications. In this role, you design, adapt, and optimize wireless communication waveforms for use by autonomous vehicles to communicate with each other and with human operators.  Familiarity with tradeoffs concerning performance, resiliency and range is necessary.  You will also work with embedded SW and FPGA engineers to optimize capability while maintaining the big picture mission and system view with an eye to both verification and validation of the end system. Additionally, you will guide the SW and FW engineers to develop SW/FW/HW to integrate wireless systems with autonomous vehicles and their controllers.  The preferred person for this role has a strong background in the effects of signal processing, communication systems architectures upon the users that rely upon them. Additionally, experience in providing technical approach to System Engineers, FPGA and SW engineers, and schedule status including work estimates and staff resource estimates to program management is preferred.  Substantial experience in the use of Matlab for waveform, network, and traffic design and simulation is highly preferred.

WHAT YOU’LL DO

• Guide embedded SW engineers and FPGA engineers in trade studies, implementation and optimization of waveforms to the autonomous applications.
• Collaborate with a multidisciplinary team of systems, software, firmware and hardware engineers to support integration activities.

REQUIRED QUALIFICATIONS

• Strong, demonstrated leadership of DSP engineers in the comms sector to include technical and programmatic leadership aspects - demonstrated ability to understand simple and innovative algorithms and work with program management, software and firmware groups to deliver compelling capabilities
• Familiarity with design of Modulation, Demodulation, Error Correction Schemes, Symmetric and Asymmetric Encryption and their affects on systems that use them.
• Familiarity with CSMA, CDMA, TDMA, FDMA, FDM, TDM, DAMA and similar communications protocols and their affect on throughput, system capacity, jitter, latency, and link integrity
• Familiarity with DSSS, FHSS, Chirp Spread Spectrum, OFDM, PSK, FSK, and similar modulation systems and their affects on links that use them.
• Experience with deceiver design parameters including: AGC, Frequency and Phase correction, DC and I/Q offset compensation, equalization, ACI and CCI mitigation
• Familiarity with MATLAB and/or Simulink.
• Experience with embedded devices for DSP, including FPGA, GPU, ASIC, and/or Software Defined Radios and the tradeoffs between which is best for what circumstances.
• Demonstrated algorithm design and implementation
• Ability to analyze and simulate algorithm performance and present findings to audience without deep technical knowledge of subject
• Familiar with commercial and/or military wireless and satellite communication standards
• Enthusiastic about both working with a team and executing DSP work individually
• Some travel required especially for review prep, reviews and integration activities, roughly 25% on average
• Must be able to obtain and hold a U.S. security clearance

PREFERRED QUALIFICATIONS

• BSEE or higher with an emphasis on Digital Signal Processing and/or information theory and practical experience
• MIMO, phased array, and beamforming experience
• Strong experience with DSP implementation for embedded devices and/or software defined radios
• Demonstrated technical task leadership of embedded SW and FPGA engineering and interfacing with program management
• Systems Engineering and mission analysis experience

Fractile’s mission is to enable a new chapter in the AI revolution. We’re pioneering AI innovation where hardware and software join to create something extraordinary, unlocking the power of the world’s largest language models with speed increases of x100. Our team is rapidly expanding, and we're searching for visionary engineers, scientists, and thinkers who share our passion for pushing boundaries and redefining what's possible. If you're ready to join a dynamic group of innovators shaping AI's future, we want to hear from you!

We are seeking a highly skilled Senior/Principal Physical Design Engineer to contribute to our next-generation chip designs. As a Physical Design Engineer, you will be responsible for the end-to-end implementation of complex IC physical designs, from synthesis to sign-off, including opportunities for full-chip ownership. You will collaborate with cross-functional teams, including logic design, verification, and process technology, to optimise performance, power, and area (PPA) while ensuring design integrity and manufacturability.

Key Responsibilities:

• Drive the physical implementation of ASIC/SoC designs, including floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off, with potential responsibility for full-chip execution.
• Work on synthesis, timing analysis (STA), and optimisation to achieve the best PPA metrics.
• Perform power planning and analysis, addressing IR drop, electromigration, and low-power design techniques.
• Ensure design rule check (DRC), layout vs. schematic (LVS), and other physical verification compliance.
• Collaborate with DFT engineers to integrate design-for-test (DFT) structures into the physical implementation.
• Develop flows in EDA tools such as Cadence Innovus, Synopsys Fusion Compiler, Mentor Graphics Calibre, and others.
• Interface with foundries and process engineers to ensure manufacturability and yield optimisation.
• Work closely with RTL and architecture teams to drive design feasibility, constraints, and physical-aware RTL design.
• Work with advanced AI tools and models to improve productivity, analysis, and design quality.

Preferred Qualifications:

• Bachelor’ Master’s or PhD in Electrical Engineering, Computer Engineering, or a related field.
• 7+ years of experience in physical design for advanced technology nodes (e.g., 7nm, 5nm, or below).
• Strong proficiency in EDA tools for place & route, STA, and sign-off.
• Solid understanding of CMOS technology, semiconductor physics, and process limitations.
• Experience with low-power design methodologies, power optimisation techniques, and multi-power domain architectures.
• Expertise in timing closure, signal integrity, IR drop analysis, and formal verification.
• Proficiency in scripting languages like TCL, Perl, or Python for automation.
• Excellent problem-solving skills, communication, and teamwork in a collaborative design environment.
• Experience in high-performance computing (HPC), AI accelerators, or networking chips.
• Experience or strong interest in leveraging advanced AI tools and models within engineering workflows.

Fractile’s mission is to enable a new chapter in the AI revolution. We’re pioneering AI innovation where hardware and software join to create something extraordinary, unlocking the power of the world’s largest language models with speed increases of x100. Our team is rapidly expanding, and we're searching for visionary engineers, scientists, and thinkers who share our passion for pushing boundaries and redefining what's possible. If you're ready to join a dynamic group of innovators shaping AI's future, we want to hear from you!

We are seeking a highly skilled Senior/Principal Physical Design Engineer to contribute to our next-generation chip designs. As a Physical Design Engineer, you will be responsible for the end-to-end implementation of complex IC physical designs, from synthesis to sign-off, including opportunities for full-chip ownership. You will collaborate with cross-functional teams, including logic design, verification, and process technology, to optimise performance, power, and area (PPA) while ensuring design integrity and manufacturability.

Key Responsibilities:

• Drive the physical implementation of ASIC/SoC designs, including floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off, with potential responsibility for full-chip execution.
• Work on synthesis, timing analysis (STA), and optimisation to achieve the best PPA metrics.
• Perform power planning and analysis, addressing IR drop, electromigration, and low-power design techniques.
• Ensure design rule check (DRC), layout vs. schematic (LVS), and other physical verification compliance.
• Collaborate with DFT engineers to integrate design-for-test (DFT) structures into the physical implementation.
• Develop flows in EDA tools such as Cadence Innovus, Synopsys Fusion Compiler, Mentor Graphics Calibre, and others.
• Interface with foundries and process engineers to ensure manufacturability and yield optimisation.
• Work closely with RTL and architecture teams to drive design feasibility, constraints, and physical-aware RTL design.
• Work with advanced AI tools and models to improve productivity, analysis, and design quality.

Preferred Qualifications:

• Bachelor’ Master’s or PhD in Electrical Engineering, Computer Engineering, or a related field.
• 7+ years of experience in physical design for advanced technology nodes (e.g., 7nm, 5nm, or below).
• Strong proficiency in EDA tools for place & route, STA, and sign-off.
• Solid understanding of CMOS technology, semiconductor physics, and process limitations.
• Experience with low-power design methodologies, power optimisation techniques, and multi-power domain architectures.
• Expertise in timing closure, signal integrity, IR drop analysis, and formal verification.
• Proficiency in scripting languages like TCL, Perl, or Python for automation.
• Excellent problem-solving skills, communication, and teamwork in a collaborative design environment.
• Experience in high-performance computing (HPC), AI accelerators, or networking chips.
• Experience or strong interest in leveraging advanced AI tools and models within engineering workflows.

Fractile’s mission is to enable a new chapter in the AI revolution. We’re pioneering AI innovation where hardware and software join to create something extraordinary, unlocking the power of the world’s largest language models with speed increases of x100. Our team is rapidly expanding, and we're searching for visionary engineers, scientists, and thinkers who share our passion for pushing boundaries and redefining what's possible. If you're ready to join a dynamic group of innovators shaping AI's future, we want to hear from you!

We are seeking a Physical Design Engineer to contribute to our next-generation chip designs. As a Physical Design Engineer, you will support the implementation of complex IC physical designs, from synthesis to sign-off. You will collaborate with cross-functional teams, including logic design, verification, and process technology, to optimise performance, power, and area (PPA) while ensuring design integrity and manufacturability.

Key Responsibilities:

• Support the physical implementation of ASIC/SoC designs, including floor planning, placement, clock tree synthesis (CTS), routing, and sign-off.
• Work on synthesis, timing analysis (STA), and optimisation to achieve strong PPA metrics.
• Assist in power planning and analysis, addressing IR drop, electromigration, and related effects.
• Ensure design rule check (DRC), layout vs. schematic (LVS), and other physical verification compliance.
• Collaborate with DFT engineers to integrate design-for-test (DFT) structures into the physical implementation.
• Develop flows in EDA tools such as Cadence Innovus, Synopsys Fusion Compiler, Mentor Graphics Calibre, and others.
• Work closely with RTL and architecture teams to support design feasibility, constraints, and physical-aware RTL design.
• Work with advanced AI tools and models to improve productivity, analysis, and design quality.

Preferred Qualifications:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 0–5 years of experience in physical design for advanced technology nodes (e.g., 7nm, 5nm, or below), including internships.
• Familiarity with EDA tools for place & route, STA, and sign-off.
• Basic understanding of CMOS technology, semiconductor physics, and process limitations.
• Exposure to timing closure, signal integrity, IR drop analysis, and formal verification.
• Proficiency in scripting languages like TCL, Perl, or Python for automation is a plus.
• Excellent problem-solving skills, communication, and teamwork in a collaborative design environment.
• Interest in working with advanced AI tools and models as part of the design workflow.
• Experience or coursework in high-performance computing (HPC), AI accelerators, or networking chips is a plus.

Fractile’s mission is to enable a new chapter in the AI revolution. We’re pioneering AI innovation where hardware and software join to create something extraordinary, unlocking the power of the world’s largest language models with speed increases of x100. Our team is rapidly expanding, and we're searching for visionary engineers, scientists, and thinkers who share our passion for pushing boundaries and redefining what's possible. If you're ready to join a dynamic group of innovators shaping AI's future, we want to hear from you!

We are seeking a Physical Design Engineer to contribute to our next-generation chip designs. As a Physical Design Engineer, you will support the implementation of complex IC physical designs, from synthesis to sign-off. You will collaborate with cross-functional teams, including logic design, verification, and process technology, to optimise performance, power, and area (PPA) while ensuring design integrity and manufacturability.

Key Responsibilities:

• Support the physical implementation of ASIC/SoC designs, including floor planning, placement, clock tree synthesis (CTS), routing, and sign-off.
• Work on synthesis, timing analysis (STA), and optimisation to achieve strong PPA metrics.
• Assist in power planning and analysis, addressing IR drop, electromigration, and related effects.
• Ensure design rule check (DRC), layout vs. schematic (LVS), and other physical verification compliance.
• Collaborate with DFT engineers to integrate design-for-test (DFT) structures into the physical implementation.
• Develop flows in EDA tools such as Cadence Innovus, Synopsys Fusion Compiler, Mentor Graphics Calibre, and others.
• Work closely with RTL and architecture teams to support design feasibility, constraints, and physical-aware RTL design.
• Work with advanced AI tools and models to improve productivity, analysis, and design quality.

Preferred Qualifications:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 0–5 years of experience in physical design for advanced technology nodes (e.g., 7nm, 5nm, or below), including internships.
• Familiarity with EDA tools for place & route, STA, and sign-off.
• Basic understanding of CMOS technology, semiconductor physics, and process limitations.
• Exposure to timing closure, signal integrity, IR drop analysis, and formal verification.
• Proficiency in scripting languages like TCL, Perl, or Python for automation is a plus.
• Excellent problem-solving skills, communication, and teamwork in a collaborative design environment.
• Interest in working with advanced AI tools and models as part of the design workflow.
• Experience or coursework in high-performance computing (HPC), AI accelerators, or networking chips is a plus.

Fractile’s mission is to enable a new chapter in the AI revolution. We’re pioneering AI innovation where hardware and software join to create something extraordinary, unlocking the power of the world’s largest language models with speed increases of x100. Our team is rapidly expanding, and we're searching for visionary engineers, scientists, and thinkers who share our passion for pushing boundaries and redefining what's possible. If you're ready to join a dynamic group of innovators shaping AI's future, we want to hear from you!

We are seeking a highly skilled Senior/Principal Physical Design Engineer to contribute to our next-generation chip designs. As a Physical Design Engineer, you will be responsible for the end-to-end implementation of complex IC physical designs, from synthesis to sign-off, including opportunities for full-chip ownership. You will collaborate with cross-functional teams, including logic design, verification, and process technology, to optimise performance, power, and area (PPA) while ensuring design integrity and manufacturability.

Key Responsibilities:

• Drive the physical implementation of ASIC/SoC designs, including floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off, with potential responsibility for full-chip execution.
• Work on synthesis, timing analysis (STA), and optimisation to achieve the best PPA metrics.
• Perform power planning and analysis, addressing IR drop, electromigration, and low-power design techniques.
• Ensure design rule check (DRC), layout vs. schematic (LVS), and other physical verification compliance.
• Collaborate with DFT engineers to integrate design-for-test (DFT) structures into the physical implementation.
• Develop flows in EDA tools such as Cadence Innovus, Synopsys Fusion Compiler, Mentor Graphics Calibre, and others.
• Interface with foundries and process engineers to ensure manufacturability and yield optimisation.
• Work closely with RTL and architecture teams to drive design feasibility, constraints, and physical-aware RTL design.
• Work with advanced AI tools and models to improve productivity, analysis, and design quality.

Preferred Qualifications:

• Bachelor’ Master’s or PhD in Electrical Engineering, Computer Engineering, or a related field.
• 7+ years of experience in physical design for advanced technology nodes (e.g., 7nm, 5nm, or below).
• Strong proficiency in EDA tools for place & route, STA, and sign-off.
• Solid understanding of CMOS technology, semiconductor physics, and process limitations.
• Experience with low-power design methodologies, power optimisation techniques, and multi-power domain architectures.
• Expertise in timing closure, signal integrity, IR drop analysis, and formal verification.
• Proficiency in scripting languages like TCL, Perl, or Python for automation.
• Excellent problem-solving skills, communication, and teamwork in a collaborative design environment.
• Experience in high-performance computing (HPC), AI accelerators, or networking chips.
• Experience or strong interest in leveraging advanced AI tools and models within engineering workflows.

Principal Engineer, SOC Design

What You’ll Do

The DRAM Development Lab (DDL) is part of Samsung’s Memory Business Unit, the industry's technology and volume leader in DRAM, HBM and NAND Flash.  DDL’s vision is to solve key problems of Cloud & Data center by developing the new technology for memory and storage. The SOC team within DDL focuses on the development of silicon solutions. We are an integral part of Samsung’s strong R&D focus & lab innovation engine. We work closely with development teams to bring feature innovation to product roadmaps.

Come join the team that is creating new computing system architectures needed to support emerging machine learning applications, data analytics and edge computing. You’ll focus on enhancement of memory and storage capability by developing prototype and production controllers.

Job ID:  42866

Location: Daily onsite presence at our San Jose or Folsom office in alignment with our Flexible Work policy

• Participate in architectural definitions and responsible for micro architecture of subsystem and/or chip level.
• Responsible for top integration, logic design and RTL implementation along with quality check (Assertion, Lint, CDC, and STA).
• Reviews 3^rd party IPs including ARM cores, DDR controller, and UCIe PHY 
• Responsible for integrating the third part IPs and sub system at top level
• Work closely with architects and verification engineers to ensure sound design at SoC level.
• Work with physical designers on timing constraints, synthesis, DFT insertion, and static timing analysis

What You Bring

• Bachelors in Electrical, Computer Science or related with 20+ years of experience or Masters in Electrical, Computer Science or related Science with 18+ years of Industry Experience or PhD in Electrical, Computer Science or related Science with 15+ years of Industry experience preferred.
• Highly motivated with good verbal and written communication skills.
• Hands on knowledge & experience in ASIC design flow from design to tape out.
• Experience & Good knowledge in ATE vector generation, testing and silicon bring up.
• Experience in the commercial IPs such as UCIe, CPU, Ethernet, and DDR interfaces.
• Good understanding of PPA (performance, power, and area) trade-offs.
• Experience in SoC level synthesis, timing analysis, lint check, CDC checks.
• Experience in interfacing 3^rd party service companies for DFT/PI/PD.
• Good knowledge and experience in AMBA bus fabric, ARM cores.
• Self-motivated problem-solver with an ability to work well in a team.
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-SF1

The SoC Architect will serve as a key technical leader, translating client requirements into an optimal SoC blueprint that achieves aggressive PPA (Power, Performance, Area) targets and driving its successful implementation.  This role will be a critical leader who provides the technical blueprint that ultimately realizes our clients' business objectives and should have a deep understanding of the complexities of custom SoC development and the ability to leverage broad system knowledge to create innovative solutions.

Location:  Daily onsite presence at our San Jose headquarters in alignment with our Flexible Work Policy with an average of 20% travel per month.

Reports to: Team leader/Head of Custom SoC Solutions Team

What You’ll Do

Customer Requirement Definition and Architecture Design:

• Analyze and define the functional, performance, and power requirements based on the client's end product and application (e.g., mobile, edge device, data center or physical AI).
• Conceive and specify the Top-Level SoC Architecture and Microarchitecture, including CPU/GPU/NPU cores, memory subsystem, Interconnect (Coherent/Non-Coherent Fabric), and high-speed I/O interfaces (e.g., PCIe, UALink or ESUN).

Architecture Exploration and Validation:

• Evaluate various architectural trade-offs and validate architectural decisions using performance and power modeling (C/C++, SystemC).
• Provide technical guidance on IP selection, integration, and system optimization, and define the Design for Debug/Test/Excellence (DFx) strategy.

Technical Collaboration and Leadership:

• Collaborate closely with cross-functional teams (HW Design, Verification, Physical Design, Software) to ensure architectural specifications are accurately translated into the design and implementation phases.
• Identify and resolve technical risks throughout the project lifecycle, and lead technical communication with clients and

 What You Bring

• Bachelor’s Degree in Electrical Engineering, Computer Science, or related discipline and 10+ years of experience, or Master’s and 8+ years of experience. 
• 5+ years experience in SoC Architecture or System Engineering (experience in custom ASIC/SoC projects is a plus)
• Deep understanding of Computer Architecture and SoC Design (including CPU, GPU, Accelerators, Caches, and Memory Systems).
• Expert knowledge and design experience with on-chip interconnects (e.g., AMBA AXI/CHI) and High-Speed Interface protocols.
• In-depth knowledge of Power Management and low-power design techniques.
• Experience with SoC-level Clock, Reset, and Power Domain architecture.
• Comprehensive understanding of the overall RTL design and SoC design flow (Implementation & Verification).
• Excellent problem-solving skills to independently identify, analyze, and resolve complex technical issues.
• Ability to communicate and negotiate effectively with diverse stakeholders, including hardware and software engineering teams, managements, and clients.
• Proficiency in scripting languages such as Python/Perl
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-VL1

We are seeking a Technical Marketing Senior Manager to join our System LSI - Custom SoC Sales and Business Development Team in San Jose, CA.  In this role, you will be responsible for identifying new opportunities for custom SoC (ASIC) business, conducting pre-shaping activities including technical requirements review and commercial discussions with potential customers, and building relationships with customers across the US market. This customer-facing role is highly cross-functional, where you will also manage day-to-day account management activities on both the technical and business sides with internal and external teams. We are seeking a high- energy professional with strong communication skills towards internal stakeholders and customers, as well as the ability to lead and develop new processes and ideas.  The successful candidate will thrive in a fast-paced, dynamic environment and be able to develop strategic relationships with customer teams. 

Location:  Daily onsite presence at our San Jose headquarters in alignment with our Flexible Work Policy

Job ID: 42912

What You’ll Do

• Support the design-in activities and business operations by working with cross-functional teams across Engineering, Sales and Marketing teams to secure customer engagements.
• Act as local support interface for US customers for existing accounts and ongoing programs.
• Engage in engineering & commercial discussions with customers.
• Market survey and developing new customers and applications.
• Act as local POC for engineering/commercial VOC collecting and leading issue resolving by circling back internally with right internal POC.
• On-going and future projects reporting to both US and Korea Executives.
• Build relationships with internal stakeholder teams such as Marketing, Sales, Product Planning and development teams to know and understand S.LSI’s differentiated offerings and strategies.
• Work with customer teams to map their requirements to S.LSI offerings, identify potential gaps, and champion their cause by driving internal development teams to address their needs and deliver technical solutions.
• Develop and build relationships with customers’ teams to understand their technology needs, application requirements and jointly define the best silicon/platform solutions to enable customer’s products.

What You Bring

• Highly Technical Background with deep business acumen and the ability to synthesize technical and business information into clear, compelling executive-level presentations that influence internal and external stakeholders.
• Bachelor’s Degree in Engineering, Business, or related discipline and 10+ years of experience, or Master’s and 8+ years of experience. 
• Technical sales and/or Marketing experience, management experience, technical/customer program management, or field applications engineering experience.
• Both Pre and Post Sales Customer Support.
• Good understanding of Semiconductor Industry, especially in SoC (System on Chip).
• Understanding or past experience with ASIC design and manufacturing flow, including advanced packaging is a Plus.
• Ability to analyze customer’s problem and needs from the component to system and application level based on customer’s requirements and purpose the solution that maps out to Samsung LSI’s offering.
• Frequent work and meetings are required with Korea.
• Korean language proficiency is a plus but not required.
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-MD1

What You’ll Do

As a seasoned Senior Technical Project Manager (ASIC) you will lead complex silicon development projects from specification definition through tape-out, fabrication, and post-silicon validation. You will be the primary face of Samsung’s (SLSI’s) ASIC design, verification, physical design, firmware, foundry and advanced packaging teams to the customer and ensure the timely delivery of all collateral. This role requires a strong technical background in semiconductors combined with exceptional program management skills to navigate risks and drive execution excellence.

Location: Daily onsite presence at our San Jose headquarters in alignment with our Flexible Work Policy.

Reports to: Team leader/Head of Custom SoC Solutions Team.

Job ID: 42809

Key Responsibilities

• End-to-End Program Ownership: Work with customers from initial concept and specification stage to silicon tape-out, bring-up, and production. This includes not only technical, but also spans commercial and legal domains.
• Project Planning & Scheduling: Develop and maintain detailed project plans, milestones, and resource allocation. Proactively identify and resolve bottlenecks and critical path issues.
• Cross-Functional Coordination: Collaborate with Architecture, RTL, Verification, Physical Design (PnR), DFT, Firmware, Emulation and Packaging teams to ensure aligned deliverables. Participate in cross functional meetings and identify and eliminate bottlenecks.
• Risk Management: Proactively identify risks and develop mitigation plans to avoid tape-out delays. Hold the development teams accountable for the scheduled quality deliverables.

 What you bring

• Education: Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field with 15+ years or a Master’s degree with 13+ years.
• Experience: 10+ years in the semiconductor industry, with at least 5+ years in technical program/project management for ASIC/SoC products.
• Technical Knowledge: Deep understanding of the full ASIC design flow (RTL, Simulation, Synthesis, STA, PnR, DFT, Tape-out).
• Methodologies: Proven experience working with advanced process nodes and high-speed design.
• Tools: Proficiency in project management tools (Jira, Confluence, MS Project) and familiarity with EDA tools (Synopsys, Cadence).
• Experience with complex packaging (2.5D/3D IC, Si interposers, TSV).
• Knowledge of automotive functional safety and other automotive industry requirements
• Experience with hardware emulation platforms (Palladium, Veloce, ZeBu).
• Leadership: Strong ability to influence cross-functional teams without direct authority.
• Problem-Solving: Ability to analyze technical problems and drive solutions in a fast-paced environment.
• Communication: Excellent verbal and written communication skills, tailoring technical information for various stakeholders.
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-MD1

The role is Design for Test (DFT) for high-performance designs going into industry leading AI/ML architectures. The person coming into this role will be involved in all implementation aspects from RTL to tapeout for various IPs on the chip. High level challenges include reducing test cost while attaining high coverage, and facilitating debug and yield learnings while minimizing design intrusions. The work is done collaboratively with a group of highly experienced engineers across various domains of the ASIC.

This role is hybrid, based out of Bangalore.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Responsibilities:

• Implementation of DFT features into RTL using verilog.
• Understanding of DFT Architectures and micro-architectures.
• ATPG and test coverage analysis using industry standard tools.
• JTAG, Scan Compression, and ASST implementation.
• Gate level simulation using Synopsys VCS and Verdi.
• Support silicon bring-up and debug.
• MBIST planning, implementation, and verification.
• Support Test Engineering on planning, patterns, and debug.
• Develop efficient DFx flows and methodology compatible with front end and physical design flows

Experience & Qualifications:

• BS/MS/PhD in EE/ECE/CE/CS with at least 5 years of industry experience in advanced DFx techniques.
• DFx experience implementing in finFET technologies.
• Experience with industry standard ATPG and DFx insertion CAD tools.
• Familiarity with SystemVerilog and UVM.
• Fluent in RTL coding for DFx logic including lock-up latches, clock gates, and scan anchors.
• Understanding of low-power design flows such as power gating, multi-Vt and voltage scaling.
• Good understanding of high-performance, low-power design fundamentals.
• Knowledge of fault models including Stuck-at, Transition, Gate-Exhaustive, Path Delay, IDDQ, and Cell Aware.
• Exposure to post-silicon testing and tester pattern debug are major assets.
• Experience with Fault Campaigns a plus.
• Strong problem solving and debug skills across various levels of design hierarchies.

Team Description:

The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-machine interface applications. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future. 

Job Responsibilities and Description: 

The Physical Design and Verification Engineer will be responsible for RTL to GDSII Physical Design Implementation, including Synthesis, Placement, Clock Tree Synthesis, Detailed Routing and Optimization, in addition to Physical Signoff Verification. 

Required Qualifications: 

• Bachelor of Science (B.S.) degree in Electrical Engineering and/or Computer Science or a related field, or equivalent experience.
• Minimum 5 years of experience in digital physical design and verification.
• Excellence in complete RTL to GDSII flow with strong experience in the usage of industry-standard Electronic Design Automation (EDA) tools for both physical design and timing signoff.
• Deep knowledge on industry standards and practices in physical design including physically-aware synthesis flow, floor-planning, and place & route, metal fill, chip finishing, signal integrity checks, and dynamic EMIR-Drop analysis, and formal ESD verification.
• Experience in Signoff ECO flow to fix timing, noise, IR-Drop and EMIR violations.
• Experience in physical design verification to debug LVS/DRC/PERC issues at the chip/block level using industry standard tools.
• Experience in developing automation flow and scripts using Python, Perl, Makefile, Tcl and UNIX shell.

Preferred Qualifications: 

• Master of Science (M.S.) degree in Electrical Engineering and/or Computer Science or a related field, or equivalent experience.
• Experience working on physical design and implementation of complex ASIC systems at advanced technology nodes, preferably 16nm and below. 
• Experience in DFT (Design For Test) flows and ATPG.
• Experience in I/O design flow in multi-voltage power domain.
• Experience in building chip floor-plan including pin placement, partitions and power grid.
• Experience in hierarchical synthesis, place-and-route and design closure to meet timing, area, and UPF-driven low power constraints.
• Experience with build tools such as CMake and Bazel.
• Experience with code coverage and regression setup.

Principal Embedded SW/FW Engineer (Bringup)

Salary $241,100 - $326,100 + Phantom Equity + Benefits 

Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption.  

As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Austin which will play a central role in Graphcore's work building the future of AI computing.  

We are looking to hire Post-Silicon Validation Engineers to join our collaborative, cross-functional development team validating cutting edge, high performance AI chips and platforms. You will play a critical role in supporting new product introductions and post-silicon validation. Working within the Post-Silicon Validation team, you will be involved with bringing first silicon to life, functionally validating it and working closely with many other teams to help it become a fully characterised and working product, reporting project status/progress to program management on a regular basis. You will have the opportunity to, and be responsible for, leading, mentoring, and providing technical guidance to other engineering team members. In this role, you can leverage your experience and industry knowledge to architect and drive implementation of continuous improvements to test infrastructure and processes. 

The Post-Silicon Validation team sits within the Architecture and Validation team, we are responsible for validation of new silicon when it returns from manufacture, enabling and supporting the production SW and FW teams to bring up their software and also supporting the Silicon Characterisation team.  

Responsibilities and Duties 

• Plan, design, develop and debug silicon validation tests in bare metal C/C++ on FPGA/Emulator prior to first silicon 
• Deploy silicon validation tests on first silicon and debugging them 
• Develop automated test framework and regression test suites in Python to optimize validation efficiency 
• Collaborate closely with engineers from many other disciplines on a variety of topics 
• Work with Validation and Production Test engineering peers to implement best practices and continuous improvements to test methodologies 
• Analyse test results, identify and debug failures/defects 
• Contribute to shared test and validation infrastructure 
• Provide feedback to architects 

Essential skills: 

• Strong experience in Bare metal / embedded C/C++ 
• Good knowledge of digital ASICs
• Be highly motivated, a self starter, and a team player  
• Ability to work across teams and programming languages to find root causes of deep and complex issues 
• Experience of the post-silicon validation process applied in digital ASIC environments 
• Python, Linux 
• Excellent communication skills and the ability to collaborate with others to solve problems
• Excellent problem-solving, analytical & diagnostic skills 

  Desirable skills: 

• Driver level experience with one or more of the following is highly desirable: 
  • PCIe 
  • Ethernet 
  • Memory technologies (LPDDR, DDR, HBM, …) 
  • Other peripherals such as I2C, I3C, SPI, … 
• Good knowledge of mixed-signal building blocks such as PLLs, high speed PHYs and IC control/communication protocols is highly desirable
• Experience of Arm CPUs, System IP and debug tools
• Experience of AMBA protocols
• Understanding of ML applications and their workloads
• Experience in Characterization, Failure Analysis, Test Development, Statistical analysis, and Customer Support 

Benefits:

In addition to a competitive salary, Graphcore offers a competitive benefits package. We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments. 

About Graphcore

At Graphcore, we’re building the future of AI compute.

We’re a team of semiconductor, software and AI experts, with deep experience in creating the complete AI compute stack - from silicon and software to infrastructure at datacenter scale.

As part of the SoftBank Group, backed by significant long-term investment, we are delivering key technology into the fast-growing SoftBank AI ecosystem.

To meet the vast and exciting AI opportunity, Graphcore is expanding its teams around the world.

We are bringing together the brightest minds to solve the toughest problems, in a place where everyone has the opportunity to make an impact on the company, our products and the future of artificial intelligence.

The Team:

The verification team sits within the Silicon design team and is responsible for ensuring that the RTL created by the logical design team and used by the physical design team matches the architecture specification for Graphcore silicon. The silicon verification engineer is responsible for verification activities within Graphcore, helping the team meet the company objectives for quality silicon delivery.

Responsibilities

• Verification planning, specification and closure of functional coverage
• Providing feedback to architects
• Test generation and failure diagnosis/triage
• Contributing to shared verification infrastructure
• Ensuring good communication between sites

Essential skills:
• Verification experience in relevant industry
• Proven leadership and planning skills
• Highly motivated, a self starter, and a team player
• Ability to work across teams and programming languages to find root causes of deep and complex issues
• Experience of the verification process applied in CPU and/or ASIC environments
• System Verilog, Python, C++, Linux

Desirable skills:
• UVM
• SVA
• Assembly languages
• LLVM, GCC
• DVCS e.g. Git
• SGE or other DRMS
• XML and XPath/XSLT
• Web programming – HTML/DOM, Javascript, SQL  

Benefits: 

In addition to a competitive salary, Graphcore offers flexible working, a generous annual leave policy, private medical insurance and health cash plan, a dental plan, pension (matched up to 5%), life assurance and income protection. We have a generous parental leave policy and an employee assistance programme (which includes health, mental wellbeing, and bereavement support). We offer a range of healthy food and snacks at our central Bristol office and have our own barista bar! We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments  

We welcome people of different backgrounds and experiences and are committed to building an inclusive work environment that makes Graphcore a great home for everyone. We are an equal opportunity employer and want to build a work environment where everyone is happy, productive and respectful so they can do their best work. If you have a disability or additional need that requires accommodation, just let us know. 

Principal Embedded SW/FW Engineer (Bringup) - Bengaluru, multiple vacancies 

Job Summary

We have an exciting opportunity to be part of a collaborative, cross-functional development team validating cutting-edge, high-performance AI chips and platforms.

 You will play a key role in supporting new product introductions and post-silicon validation.

Working within the Post-Silicon Validation team, you will be involved with bringing first silicon to life, functionally validating it and working closely with many other teams to help it become a fully characterised and working product, reporting project status/progress to program management on a regular basis. You will have the opportunity to provide technical guidance to other engineering team members. In this role, you can leverage our experience and industry knowledge to architect and drive implementation of continuous improvements to test infrastructure and processes.

The Team

The Post-Silicon Bringup team sits within the Architecture and Validation team, we are responsible for bringup and validation of new silicon when it returns from manufacture, enabling and supporting the production SW and FW teams to bring up their software and supporting the Silicon Characterisation team.

Responsibilities and Duties

• Plan, design, develop and debug silicon validation tests in bare metal C/C++ on FPGA/Emulator prior to first silicon
• Deploy silicon validation tests on first silicon and debugging them
• Develop automated test framework and regression test suites in Python to optimize validation efficiency
• Collaborate closely with engineers from many other disciplines on a variety of topics
• Work with Validation and Production Test engineering peers to implement best practices and continuous improvements to test methodologies
• Analyse test results, identify and debug failures/defects
• Contribute to shared test and validation infrastructure
• Provide feedback to architects

Candidate Profile 

Essential:

• Understanding of ML applications and their workloads
• A self-starter who can apply independent judgement
• A team player able to lead and support colleagues with difficult concepts
• Strong experience in Bare metal / embedded C/C++

• Excellent problem-solving, analytical & diagnostic skills

• Ability to work across teams and programming languages to find root causes of critical and complex issues

• Experience of the post-silicon validation process applied in digital ASIC environments

• Python, Linux

• Excellent communication skills and the ability to explain difficult concepts to resolve issues 

Desirable

• 10+ years  experience 
• Experience building and leading, multi-site teams
• Driver level experience with one or more of the following is highly desirable:

• PCIe
• Ethernet
• Memory technologies (LPDDR, DDR, HBM, …)
• Other peripherals such as I2C, I3C, SPI, …

• Good knowledge of mixed-signal building blocks such as PLLs, high speed PHYs and IC control/communication protocols is highly desirable.
• Experience of Arm CPUs, System IP and debug tools.
• Experience of AMBA protocols.
• Experience in Characterization, Failure Analysis, Test Development, Statistical analysis, 

Senior Post Silicon Validation Engineer (Bringup)

Salary $156,500 - $211,700 + Phantom Equity + Benefits 

Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption.  

As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Austin which will play a central role in Graphcore's work building the future of AI computing.  

We are looking to hire Post-Silicon Validation Engineers to join our collaborative, cross-functional development team validating cutting edge, high performance AI chips and platforms. You will play a critical role in supporting new product introductions and post-silicon validation. Working within the Post-Silicon Validation team, you will be involved with bringing first silicon to life, functionally validating it and working closely with many other teams to help it become a fully characterised and working product, reporting project status/progress to program management on a regular basis. You will have the opportunity to, and be responsible for, leading, mentoring, and providing technical guidance to other engineering team members. In this role, you can leverage your experience and industry knowledge to architect and drive implementation of continuous improvements to test infrastructure and processes. 

The Post-Silicon Validation team sits within the Architecture and Validation team, we are responsible for validation of new silicon when it returns from manufacture, enabling and supporting the production SW and FW teams to bring up their software and also supporting the Silicon Characterisation team.  

Responsibilities and Duties 

• Plan, design, develop and debug silicon validation tests in bare metal C/C++ on FPGA/Emulator prior to first silicon 
• Deploy silicon validation tests on first silicon and debugging them 
• Develop automated test framework and regression test suites in Python to optimize validation efficiency 
• Collaborate closely with engineers from many other disciplines on a variety of topics 
• Work with Validation and Production Test engineering peers to implement best practices and continuous improvements to test methodologies 
• Analyse test results, identify and debug failures/defects 
• Contribute to shared test and validation infrastructure 
• Provide feedback to architects 

Essential skills: 

• Strong experience in Bare metal / embedded C/C++ 
• Good knowledge of digital ASICs
• Be highly motivated, a self starter, and a team player  
• Ability to work across teams and programming languages to find root causes of deep and complex issues 
• Experience of the post-silicon validation process applied in digital ASIC environments 
• Python, Linux 
• Excellent communication skills and the ability to collaborate with others to solve problems
• Excellent problem-solving, analytical & diagnostic skills 

  Desirable skills: 

• Driver level experience with one or more of the following is highly desirable: 
  • PCIe 
  • Ethernet 
  • Memory technologies (LPDDR, DDR, HBM, …) 
  • Other peripherals such as I2C, I3C, SPI, … 
• Good knowledge of mixed-signal building blocks such as PLLs, high speed PHYs and IC control/communication protocols is highly desirable
• Experience of Arm CPUs, System IP and debug tools
• Experience of AMBA protocols
• Understanding of ML applications and their workloads
• Experience in Characterization, Failure Analysis, Test Development, Statistical analysis, and Customer Support 

Benefits:

In addition to a competitive salary, Graphcore offers a competitive benefits package. We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments. 

About Graphcore

At Graphcore, we’re building the future of AI compute. We’re a team of semiconductor, software and AI experts, with deep experience in creating the complete AI compute stack - from silicon and software to infrastructure at datacenter scale. As part of the SoftBank Group, backed by significant long-term investment, we are delivering key technology into the fast-growing SoftBank AI ecosystem.To meet the vast and exciting AI opportunity, Graphcore is expanding its teams around the world. We are bringing together the brightest minds to solve the toughest problems, in a place where everyone has the opportunity to make an impact on the company, our products and the future of artificial intelligence.

Job Summary

As a Technical Programme Manager, you will lead the planning and delivery of complex silicon chip design programmes, focusing on execution across design, implementation and tape-out. You will work across the full development lifecycle, from early product definition through to production readiness.

You will partner with engineering managers and cross-functional teams (ASIC/SoC design, physical design, verification, DFT, CAD, product and operations) to ensure programmes are delivered on time, within scope and to a high standard. This role requires strong technical understanding, programme leadership, and the ability to manage dependencies in a fast-paced semiconductor environment.

The Team

Our Engineering Programme Management team sits at the heart of silicon innovation, enabling delivery of advanced chip technologies. We work across architecture, design, implementation and operations to drive alignment, execution and continuous improvement throughout the silicon lifecycle.

Key Responsibilities

• Lead planning, execution and day-to-day management of silicon design programmes, ensuring milestones and dependencies are clearly defined and tracked.
• Build and maintain integrated schedules across architecture, RTL, verification, physical design, DFT, CAD and tape-out.
• Drive alignment across engineering, product and operations on scope, priorities, resourcing and delivery plans.
• Support execution through key phases including specification, design reviews, implementation, sign-off and tape-out readiness.
• Manage scope changes, assessing impact on schedule and resources while maintaining stakeholder alignment.
• Identify risks, dependencies and challenges early, with clear mitigation and escalation plans.
• Coordinate cross-functional readiness for major milestones such as IP integration, design closure and tape-out.
• Provide regular updates on programme status, risks and recovery plans.
• Drive structured decision-making and accountability across teams.
• Capture lessons learned to improve programme management practices and workflows.

Candidate Profile

Essential

• Bachelor’s degree (or higher) in Electrical/Electronic Engineering, Computer Engineering, Computer Science, or a related field.
• 3–5 years’ experience in programme/project management or technical delivery within semiconductor, ASIC, SoC or hardware environments.
• Experience supporting silicon design programmes across RTL, verification, physical design and tape-out.
• Good understanding of the silicon development lifecycle, including design, integration, implementation and tape-out milestones.
• Experience working with cross-functional engineering teams.
• Strong organisational and planning skills, with the ability to manage dependencies and competing priorities.
• Strong problem-solving skills with a proactive approach to risk and issue management.
• Excellent communication and stakeholder management skills across technical and non-technical audiences.
• Self-motivated, collaborative, and effective in fast-moving environments.

Desirable

• Experience with ASIC/SoC development flows, including design reviews, implementation, sign-off and tape-out.
• Familiarity with RTL, physical design, DFT, CAD or silicon platform teams.
• Understanding of system-level considerations influencing chip design.
• Experience in AI, accelerator, datacentre or high-performance compute silicon programmes.
• Knowledge of semiconductor product development from concept to manufacturing handoff.

Principal Post Silicon Validation Engineer (Bringup)

Salary $241,100 - $326,100 + Phantom Equity + Benefits 

Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption.  

As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Austin which will play a central role in Graphcore's work building the future of AI computing.  

We are looking to hire Post-Silicon Validation Engineers to join our collaborative, cross-functional development team validating cutting edge, high performance AI chips and platforms. You will play a critical role in supporting new product introductions and post-silicon validation. Working within the Post-Silicon Validation team, you will be involved with bringing first silicon to life, functionally validating it and working closely with many other teams to help it become a fully characterised and working product, reporting project status/progress to program management on a regular basis. You will have the opportunity to, and be responsible for, leading, mentoring, and providing technical guidance to other engineering team members. In this role, you can leverage your experience and industry knowledge to architect and drive implementation of continuous improvements to test infrastructure and processes. 

The Post-Silicon Validation team sits within the Architecture and Validation team, we are responsible for validation of new silicon when it returns from manufacture, enabling and supporting the production SW and FW teams to bring up their software and also supporting the Silicon Characterisation team.  

Responsibilities and Duties 

• Plan, design, develop and debug silicon validation tests in bare metal C/C++ on FPGA/Emulator prior to first silicon 
• Deploy silicon validation tests on first silicon and debugging them 
• Develop automated test framework and regression test suites in Python to optimize validation efficiency 
• Collaborate closely with engineers from many other disciplines on a variety of topics 
• Work with Validation and Production Test engineering peers to implement best practices and continuous improvements to test methodologies 
• Analyse test results, identify and debug failures/defects 
• Contribute to shared test and validation infrastructure 
• Provide feedback to architects 

Essential skills: 

• Strong experience in Bare metal / embedded C/C++ 
• Good knowledge of digital ASICs
• Be highly motivated, a self starter, and a team player  
• Ability to work across teams and programming languages to find root causes of deep and complex issues 
• Experience of the post-silicon validation process applied in digital ASIC environments 
• Python, Linux 
• Excellent communication skills and the ability to collaborate with others to solve problems
• Excellent problem-solving, analytical & diagnostic skills 

  Desirable skills: 

• Driver level experience with one or more of the following is highly desirable: 
  • PCIe 
  • Ethernet 
  • Memory technologies (LPDDR, DDR, HBM, …) 
  • Other peripherals such as I2C, I3C, SPI, … 
• Good knowledge of mixed-signal building blocks such as PLLs, high speed PHYs and IC control/communication protocols is highly desirable
• Experience of Arm CPUs, System IP and debug tools
• Experience of AMBA protocols
• Understanding of ML applications and their workloads
• Experience in Characterization, Failure Analysis, Test Development, Statistical analysis, and Customer Support 

Benefits:

In addition to a competitive salary, Graphcore offers a competitive benefits package. We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments. 

Silicon Verification Engineer

Multiple roles across different levels

Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. 

As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Bengaluru which will play a central role in Graphcore's work building the future of AI computing.  

The verification team sits within the Silicon design team and is responsible for ensuring that the RTL created by the logical design team and used by the physical design team matches the architecture specification for Graphcore silicon. The silicon verification engineer is responsible for verification activities within Graphcore, helping the team meet the company objectives for quality silicon delivery.

Responsibilities

• Verification planning, specification and closure of functional coverage
• Providing feedback to architects
• Test generation and failure diagnosis/triage
• Contributing to shared verification infrastructure
• Ensuring good communication between sites

Essential skills:

•8 to 12 Years of experience
•Verification experience in relevant industry
• Proven leadership and planning skills
• Highly motivated, a self starter, and a team player
• Ability to work across teams and programming languages to find root causes of deep and complex issues
• Experience of the verification process applied in CPU and/or ASIC environments
• System Verilog, Python, C++, Linux

Desirable skills:
• UVM
• SVA
• Assembly languages
• LLVM, GCC
• DVCS e.g. Git
• SGE or other DRMS
• XML and XPath/XSLT
• Web programming – HTML/DOM, Javascript, SQL  

Benefits:

In addition to a competitive salary, Graphcore offers a competitive benefits package. We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments. 

About Graphcore

At Graphcore, we’re building the future of AI compute.

We’re a team of semiconductor, software and AI experts, with deep experience in creating the complete AI compute stack - from silicon and software to infrastructure at datacenter scale.

As part of the SoftBank Group, backed by significant long-term investment, we are delivering key technology into the fast-growing SoftBank AI ecosystem.

To meet the vast and exciting AI opportunity, Graphcore is expanding its teams around the world.

We are bringing together the brightest minds to solve the toughest problems, in a place where everyone has the opportunity to make an impact on the company, our products and the future of artificial intelligence.

The Team:

The verification team sits within the Silicon design team and is responsible for ensuring that the RTL created by the logical design team and used by the physical design team matches the architecture specification for Graphcore silicon. The Silicon Verification Lead is responsible for verification activities within Graphcore, helping the team meet the company objectives for quality silicon delivery.

Responsibilities

• Verification planning, specification and closure of functional coverage
• Providing feedback to architects
• Test generation and failure diagnosis/triage
• Contributing to shared verification infrastructure
• Ensuring good communication between sites

Essential skills:
• Verification experience in relevant industry
• Proven leadership and planning skills
• Highly motivated, a self starter, and a team player
• Ability to work across teams and programming languages to find root causes of deep and complex issues
• Experience of the verification process applied in CPU and/or ASIC environments
• System Verilog, Python, C++, Linux

Desirable skills:
• UVM
• SVA
• Assembly languages
• LLVM, GCC
• DVCS e.g. Git
• SGE or other DRMS
• XML and XPath/XSLT
• Web programming – HTML/DOM, Javascript, SQL  

Benefits: 

In addition to a competitive salary, Graphcore offers flexible working, a generous annual leave policy, private medical insurance and health cash plan, a dental plan, pension (matched up to 5%), life assurance and income protection. We have a generous parental leave policy and an employee assistance programme (which includes health, mental wellbeing, and bereavement support). We offer a range of healthy food and snacks at our central Bristol office and have our own barista bar! We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments  

We welcome people of different backgrounds and experiences and are committed to building an inclusive work environment that makes Graphcore a great home for everyone. We are an equal opportunity employer and want to build a work environment where everyone is happy, productive and respectful so they can do their best work. If you have a disability or additional need that requires accommodation, just let us know. 

Senior Embedded SW/FW Engineer (Bringup)

Salary $156,500 - $211,700 + Phantom Equity + Benefits 

Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption.  

As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Austin which will play a central role in Graphcore's work building the future of AI computing.  

We are looking to hire Post-Silicon Validation Engineers to join our collaborative, cross-functional development team validating cutting edge, high performance AI chips and platforms. You will play a critical role in supporting new product introductions and post-silicon validation. Working within the Post-Silicon Validation team, you will be involved with bringing first silicon to life, functionally validating it and working closely with many other teams to help it become a fully characterised and working product, reporting project status/progress to program management on a regular basis. You will have the opportunity to, and be responsible for, leading, mentoring, and providing technical guidance to other engineering team members. In this role, you can leverage your experience and industry knowledge to architect and drive implementation of continuous improvements to test infrastructure and processes. 

The Post-Silicon Validation team sits within the Architecture and Validation team, we are responsible for validation of new silicon when it returns from manufacture, enabling and supporting the production SW and FW teams to bring up their software and also supporting the Silicon Characterisation team.  

Responsibilities and Duties 

• Plan, design, develop and debug silicon validation tests in bare metal C/C++ on FPGA/Emulator prior to first silicon 
• Deploy silicon validation tests on first silicon and debugging them 
• Develop automated test framework and regression test suites in Python to optimize validation efficiency 
• Collaborate closely with engineers from many other disciplines on a variety of topics 
• Work with Validation and Production Test engineering peers to implement best practices and continuous improvements to test methodologies 
• Analyse test results, identify and debug failures/defects 
• Contribute to shared test and validation infrastructure 
• Provide feedback to architects 

Essential skills: 

• Strong experience in Bare metal / embedded C/C++ 
• Good knowledge of digital ASICs
• Be highly motivated, a self starter, and a team player  
• Ability to work across teams and programming languages to find root causes of deep and complex issues 
• Experience of the post-silicon validation process applied in digital ASIC environments 
• Python, Linux 
• Excellent communication skills and the ability to collaborate with others to solve problems
• Excellent problem-solving, analytical & diagnostic skills 

  Desirable skills: 

• Driver level experience with one or more of the following is highly desirable: 
  • PCIe 
  • Ethernet 
  • Memory technologies (LPDDR, DDR, HBM, …) 
  • Other peripherals such as I2C, I3C, SPI, … 
• Good knowledge of mixed-signal building blocks such as PLLs, high speed PHYs and IC control/communication protocols is highly desirable
• Experience of Arm CPUs, System IP and debug tools
• Experience of AMBA protocols
• Understanding of ML applications and their workloads
• Experience in Characterization, Failure Analysis, Test Development, Statistical analysis, and Customer Support 

Benefits:

In addition to a competitive salary, Graphcore offers a competitive benefits package. We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments. 

Staff Embedded SW/FW Engineer (Bringup)

Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption.  

As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Bengaluru which will play a central role in Graphcore's work building the future of AI computing.

Job Summary

We have an exciting opportunity to be part of a collaborative, cross-functional development team developing C code used to validate cutting-edge, high-performance AI chips and platforms. You will play a critical role in supporting new product introductions and post-silicon validation.

Working within the Post-Silicon Bringup team, you will be involved with bringing first silicon to life, developing code primarily in C to configure and exercise systems and sub-systems on new silicon devices, and working closely with many other teams to help it become a fully characterised and working product, reporting project status/progress to program management on a regular basis. You will have the opportunity to, and be responsible for, leading, mentoring, and providing technical guidance to other engineering team members. In this role, you can leverage your experience and industry knowledge to architect and drive implementation of continuous improvements to test infrastructure and processes.

The Team

The Post-Silicon Bringup team sits within the Architecture and Validation team, we are responsible for bringup and validation of new silicon when it returns from manufacture, enabling and supporting the production SW and FW teams to bring up their software and supporting the Silicon Characterisation team. 

Responsibilities and Duties

• Plan, design, develop and debug silicon bringup sequences and test in bare metal C/C++ on FPGA/Emulator prior to first silicon
• Deploy configuration sequences and validation tests on first silicon and debug them
• Develop automated test framework and regression test suites in Python to optimize validation efficiency
• Collaborate closely with engineers from many other disciplines on a variety of topics
• Work with Validation and Production Test engineering peers to implement best practices and continuous improvements to test methodologies
• Analyse test results, identify and debug failures/defects
• Contribute to shared test and validation infrastructure
• Provide feedback to architects

Candidate Profile

Essential:

• Strong experience in Bare metal / embedded C/C++
• Good knowledge of digital ASICs.
• Be highly motivated, a self starter, and a team player 
• Ability to work across teams and programming languages to find root causes of deep and complex issues
• Experience of the post-silicon validation process applied in digital ASIC environments
• Python, Linux
• Excellent communication skills and the ability to collaborate with others to solve problems.
• Excellent problem-solving, analytical & diagnostic skills

Desirable:

• Driver level experience with one or more of the following is highly desirable:

• PCIe
• Ethernet
• Memory technologies (LPDDR, DDR, HBM, …)
• Other peripherals such as I2C, I3C, SPI, …

• Good knowledge of mixed-signal building blocks such as PLLs, high speed PHYs and IC control/communication protocols is highly desirable.
• Experience of Arm CPUs, System IP and debug tools.
• Experience of AMBA protocols.
• Understanding of ML applications and their workloads.
• Experience in Characterization, Failure Analysis, Test Development, Statistical analysis, and Customer Support

Benefits:

In addition to a competitive salary, Graphcore offers a competitive benefits package. We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments. 

Silicon Verification Engineer

Multiple roles across different levels

Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. 

As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Bengaluru which will play a central role in Graphcore's work building the future of AI computing.  

The verification team sits within the Silicon design team and is responsible for ensuring that the RTL created by the logical design team and used by the physical design team matches the architecture specification for Graphcore silicon. The silicon verification engineer is responsible for verification activities within Graphcore, helping the team meet the company objectives for quality silicon delivery.

Responsibilities

• Verification planning, specification and closure of functional coverage
• Providing feedback to architects
• Test generation and failure diagnosis/triage
• Contributing to shared verification infrastructure
• Ensuring good communication between sites

Essential skills:
• Verification experience in relevant industry
• Proven leadership and planning skills
• Highly motivated, a self starter, and a team player
• Ability to work across teams and programming languages to find root causes of deep and complex issues
• Experience of the verification process applied in CPU and/or ASIC environments
• System Verilog, Python, C++, Linux

Desirable skills:
• UVM
• SVA
• Assembly languages
• LLVM, GCC
• DVCS e.g. Git
• SGE or other DRMS
• XML and XPath/XSLT
• Web programming – HTML/DOM, Javascript, SQL  

Benefits:

In addition to a competitive salary, Graphcore offers a competitive benefits package. We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments. 

About Graphcore 

At Graphcore, we’re building the future of AI compute.

We’re a team of semiconductor, software and AI experts, with deep experience in creating the complete AI compute stack - from silicon and software to infrastructure at datacenter scale.

As part of the SoftBank Group, backed by significant long-term investment, we are delivering key technology into the fast-growing SoftBank AI ecosystem.

To meet the vast and exciting AI opportunity, Graphcore is expanding its teams around the world.

We are bringing together the brightest minds to solve the toughest problems, in a place where everyone has the opportunity to make an impact on the company, our products and the future of artificial intelligence.

 The Team 

The Verification team sits within the Silicon Design organisation. We ensure that the RTL delivered by Logical Design and used by Physical Design team implements Graphcore’s architectural needs and meets the company's quality standards.  As a Director of Silicon Verification, you will help lead this multi-site organisation, define verification strategies across multiple silicon programs, and drive best in class execution to ensure high-quality, high-performance silicon delivery. 

Role Summary 

We are seeking a proven leader to help direct Graphcore’s verification strategy and methodologies. This role sets direction for the verification lifecycle including - planning, infrastructure, execution, coverage closure, debug strategy and sign-off for Graphcore’s complex, high performance AI accelerators. 

Reporting to the Senior Director of Verification the Director will partner closely with other teams such as Architecture, Logical Design, Physical Design, DFT, Systems as well as Program Management teams to ensure accurate implementation, accelerated debug cycles, high coverage confidence and predictable silicon delivery. 

 
Responsibilities 

 Leadership & Strategy 

• Define the long-term vision, roadmap and strategy for silicon functional verification across all Graphcore silicon programs. 

• Build, lead, and develop a high performing, globally distributed verification organisation. 

• Establish scalable methodologies, leading edge verification techniques, and best practice processes. 

• Drive automation, tooling and infrastructure evolution to improve productivity and verification quality. 

• Evaluate emerging tools and technologies and drive adoption to deliver competitive advantage. 

 Technical Ownership 

• Own verification planning, execution and sign off for all RTL blocks and top-level SoCs. 

• Oversee definition of test plans including functional coverage targets. Drive close through prioritisation of test content and coverage signoff. Iterate plans to close verification gaps. 

• Direct debugging strategies, triage processes and root-cause analysis workflows to enhance team productivity. 
  
  
• Steer integration of verification technologies including formal methods, simulation acceleration/emulation and system level validation. 

Cross Functional Collaboration 

• Ensure high quality feedback to other functions within the Silicon Team.  

• Partner with Architecture to influence and refine specifications for verifiability and risk reduction. 

• Collaborate with Logical Design to align on design intent, architectural corner cases and test scenarios. 

• Work closely with Physical Design and DFT teams to ensure coherent verification of interfaces, timing assumptions and test structures. 

• Lead post-silicon debug alignment where needed, ensuring learning cycles feed back into RTL and verification methodology. 

 
Execution & Delivery 

• Deliver verification sign off on schedule across multiple parallel projects. 

• Guide program risk management, resource planning, milestone creation, and verification budgeting. 

• Drive consistent metrics-based verification management (structural and functional coverage, bug funnels, simulation performance, CI health, etc.). 

• Provide scheduled reports into program management on progress with associated metrics based collaterol. 

Essential Skills 

• Demonstrated ability to lead, scale and inspire high performing verification teams. 

• Extensive verification leadership experience within CPU, GPU, ASIC or SoC environments. 

• Deep understanding of modern verification methodologies, flows, and infrastructure. 

• Strong capability in SystemVerilog, Python, C++ and Linux-based workflows. 

• Expertise in diagnosing complex logic issues across RTL, testbench and system level domains. 

• Strong communication, collaboration and stakeholder management skills across global sites. 

Desirable Skills 

• UVM and advanced SystemVerilog Assertions (SVA). 

• Experience with assembly languages and compiler toolchains (LLVM, GCC). 

• Knowledge of DVCS tools (e.g., Git). 

• Familiarity with distributed compute systems (SGE or other DRMS). 

• Experience with XML, XPath/XSLT. 

• Web technologies such as HTML/DOM, JavaScript, SQL. 

• Exposure to emulation, FPGA prototyping, or formal verification tools. 

Benefits

In addition to a competitive salary, Graphcore offers flexible working, a generous annual leave policy, private medical insurance and health cash plan, a dental plan, pension (matched up to 5%), life assurance and income protection. We have a generous parental leave policy and an employee assistance programme (which includes health, mental wellbeing, and bereavement support). We offer a range of healthy food and snacks at our central Bristol office and have our own barista bar! We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments.

About Graphcore

At Graphcore, we’re building the future of AI compute.

We’re a team of semiconductor, software and AI experts, with deep experience in creating the complete AI compute stack - from silicon and software to infrastructure at datacenter scale.

As part of the SoftBank Group, backed by significant long-term investment, we are delivering key technology into the fast-growing SoftBank AI ecosystem.

To meet the vast and exciting AI opportunity, Graphcore is expanding its teams around the world.

We are bringing together the brightest minds to solve the toughest problems, in a place where everyone has the opportunity to make an impact on the company, our products and the future of artificial intelligence.

The Team:

The verification team sits within the Silicon design team and is responsible for ensuring that the RTL created by the logical design team and used by the physical design team matches the architecture specification for Graphcore silicon. The silicon verification engineer is responsible for verification activities within Graphcore, helping the team meet the company objectives for quality silicon delivery.

Responsibilities

• Verification planning, specification and closure of functional coverage
• Providing feedback to architects
• Test generation and failure diagnosis/triage
• Contributing to shared verification infrastructure
• Ensuring good communication between sites

Essential skills:
• Verification experience in relevant industry
• Proven leadership and planning skills
• Highly motivated, a self starter, and a team player
• Ability to work across teams and programming languages to find root causes of deep and complex issues
• Experience of the verification process applied in CPU and/or ASIC environments
• System Verilog, Python, C++, Linux

Desirable skills:
• UVM
• SVA
• Assembly languages
• LLVM, GCC
• DVCS e.g. Git
• SGE or other DRMS
• XML and XPath/XSLT
• Web programming – HTML/DOM, Javascript, SQL  

Benefits: 

In addition to a competitive salary, Graphcore offers flexible working, a generous annual leave policy, private medical insurance and health cash plan, a dental plan, pension (matched up to 5%), life assurance and income protection. We have a generous parental leave policy and an employee assistance programme (which includes health, mental wellbeing, and bereavement support). We offer a range of healthy food and snacks at our central Bristol office and have our own barista bar! We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments  

We welcome people of different backgrounds and experiences and are committed to building an inclusive work environment that makes Graphcore a great home for everyone. We are an equal opportunity employer and want to build a work environment where everyone is happy, productive and respectful so they can do their best work. If you have a disability or additional need that requires accommodation, just let us know. 

THE ROLE

Join the Systems Software team to architect and deliver the core software powering the industry's most innovative, high-availability storage platforms. You will lead the development of mission-critical system components, transforming complex hardware-software integration challenges into seamless, zero-downtime customer experiences. By collaborating with hardware and cross-functional software teams, you will define the future of enterprise data storage and ensure our platforms remain at the cutting edge of performance and reliability.

WHAT YOU'LL DO

• Architect High-Performance Networking: Drive the end-to-end design and debugging of C/C++ networking software to ensure next-generation switching and fabric platforms meet rigorous scalability and resiliency benchmarks.

• Own Core Protocol Development: Deliver critical Layer 2 and Layer 3 features—including forwarding behavior and control-plane protocols—that simplify operations for global enterprise customers.

• Lead Hardware-Software Integration: Partner with ASIC vendors and internal platform teams to implement switch SDK functionalities, ensuring robust hardware interfaces and successful in-service software upgrades (ISSU).

• Innovate with Open Networking: Design and customize SONiC-based solutions across the control and data planes to enhance our disaggregated network operating system capabilities.

• Drive Technical Excellence: Act as a technical mentor and lead for complex initiatives, setting the standard for code quality and architectural decisions across cross-functional networking efforts.

• We are primarily an in-office environment and therefore, you will be expected to work from the Santa Clara, CA office in compliance with Pure’s policies, unless you are on PTO, or work travel, or other approved leave.

WHAT YOU BRING

• Systems Programming Expertise: Advanced proficiency in C/C++ (C++11+) with a track record of building and debugging performance-sensitive systems software or networking applications.

• Deep Networking Domain Knowledge: Mastery of Layer 2 and Layer 3 protocols (Ethernet, VLANs, BGP, ECMP) and the ability to translate these complex behaviors into production-ready code.

• Hardware Interfacing Skills: Practical experience working with switch SDKs or Linux networking internals (kernel concepts, drivers, or packet processing) to interact directly with ASIC capabilities.

• Availability-Focused Engineering: Understanding of non-disruptive upgrade (NDU) technologies and the architectural discipline required to build systems that minimize customer impact during maintenance.

• Collaborative Technical Leadership: Ability to independently drive complex problem-solving and influence technical direction across multiple teams while mentoring junior engineers.

 #LI-ONSITE

Summary

We're a well-funded, stealth startup building a new computing platform based on a high-performance edge SoC on an advanced process node. Our V1 strategy is lean and aggressive: we license best-in-class IP from Arm and others, and partner with a tier-1 ASIC design service for backend execution and physical design.

We need a VP of Silicon who won't let external partners grade their own homework. Your immediate job is to build the team to own the development of a world-class SoC architecture, negotiate and integrate cutting-edge IP, and aggressively manage our ASIC partner to ensure they deliver top-tier PPA. Long-term, your mandate is to lay the groundwork for taking on more silicon design responsibilities in future iterations, gradually transitioning us from an IP integrator to a full-stack custom silicon company.

Responsibilities

• Build the Core Team. For V1, you will hire a lean, highly capable internal team of performance architects, low-power circuit experts, system-level DV engineers, and bring-up specialists to validate the architecture and keep the ASIC partner on the path of excellence. You will also lay the structural groundwork for bringing more front-end design in-house in future iterations.
  
  
• Drive System Architecture. You will own the overarching architectural strategy. You'll make the hard executive calls to balance strict power constraints with massive performance and memory bandwidth targets.
  
  
• Challenge the Defaults. Relying on an ASIC partner's defaults leads to missed opportunities. You and your team will actively push back on implementation choices, interrogate timing closure strategies, and force custom mitigation efforts rather than accepting sub-optimal work.
  
  
• Obsess Over Power and Performance. We have unyielding targets for performance and for both active efficiency and retention power. You will build a culture that models performance and runs traces early to ensure all bottlenecks are identified before RTL freeze and direct the evaluation of advanced low-power circuit techniques and adaptive voltage scaling (AVS) strategies.
  
  
• Own the Lifecycle. Your responsibility spans from early IP evaluation through product integration. You will drive post-silicon validation, silicon characterization, and hardware debug strategy, ensuring the chip meets all PPA targets and integrates seamlessly with the broader hardware and system software teams.

Requirements

• Deep Silicon Track Record. 15+ years of engineering experience with multiple tapeouts on advanced process nodes. You deeply understand the physical and electrical characteristics of bleeding-edge manufacturing.
  
  
• ASIC/Turnkey Experience. Proven track record of successfully driving complex SoCs through an ASIC design service. You know exactly where external partners cut corners and how to catch them.
  
  
• Mastery of the Arm Ecosystem. Deep, systemic expertise in Arm architectures, interconnect fabrics, and performance analysis tooling.
  
  
• Executive Leadership and Scaling. 5+ years directing silicon engineering organizations. You know how to start lean, recruit elite talent, and scale an organization as internal responsibilities expand.
  
  
• Vendor Management. You are comfortable holding partners accountable. You know how to extract the best possible support, IP deliverables, and custom implementations from large external organizations.

Salary & Benefits

• $375,000/year base salary + top-of-market equity
• Platinum medical/dental/vision (100% employee premium coverage, 70% dependents)
• 401(k) + FSA
• Take-what-you-need unmetered PTO

About The Role

As a member of our tight knit physical design team, you will be working on the design and analysis of 3D integrated products. This role involves a combination of traditional ASIC/SoC physical design skills, packaging, power, clock and cooling analysis. You will work closely with the architecture and RTL team to do R&D on novel concepts for 3D integration. 

Skills and Qualifications

Required 

•     10+ years of physical design/verification experience. 
•     Strong knowledge of block level and full-chip physical verification methodology. 
•     Expert at optimizing for the best power/performance and area.
•     Experience with the complete physical design flow. Knowledge of Synopsys tool suite is a plus. 
•     Expert with ICV or Calibre tools resolving block and full-chip DRC and LVS issues. 
•     Expert with IR/EM analysis and resolution.
•     Strong ability in scripting languages like Tcl and Python. Ability to make flow enhancements. 
•     Demonstrated ability to work with RTL teams to optimize for physical design.
•     Knowledge of 2.5D or 3D packaging solutions.
•     Must have experience with 3d physical design, 3d die stacking, 3d chip design, die-to-die or wafer-to-wafer.

Preferred    

•     Experience doing full chip floor planning and integration.   
•     Knowledge of clock distribution.
•     Knowledge of cooling analysis.

This job description may not be inclusive to the duties and responsibilities listed. Additional tasks may be assigned to the employee from time to time or the scope of the job may change as needed by business demands. 

Position Overview

We are seeking an ASIC Design Engineer to contribute to the design and implementation of complex silicon solutions used in AST’s space‑based communications systems.

The Silicon Team in Edinburgh is a small, highly focused group responsible for developing high‑value silicon that is core to AST’s mission of “Connecting the unconnected” - delivering the world’s first space‑based mobile broadband network.

The team works collaboratively to define and build next‑generation silicon, exploring advanced silicon technologies to continuously improve performance, capability, and efficiency. This is a hands‑on environment where silicon decisions directly impact AST’s ability to deliver a global communications network from space.

In this role, you will focus on high‑quality RTL development, micro‑architecture definition, and close collaboration across engineering disciplines. You will work alongside architecture, verification, and system teams—both internal and external—to deliver robust, high‑performance ASIC and SoC designs from concept through tape‑out.

Key Responsibilities:

• Create high‑quality micro‑architecture specifications and RTL code.
• Contribute to SoC integration and subsystem development.
• Work with internal and external stakeholders, including architecture, verification, and software teams.
• Participate in design reviews, providing technical input.
• Ensure alignment with requirements and design best practices.

Qualifications

Education:

BEng in Electrical Engineering, Computer Engineering, Computer Science, or a related discipline.

Experience:

• Deep knowledge of hardware and digital design fundamentals.
• Strong SystemVerilog knowledge.
• Experience with SoC integration.
• Prior experience on complex RTL designs such as high‑speed I/O, CPUs, accelerators, or complex network‑on‑chip implementations.
• Ability to write clear, high‑quality micro‑architecture specifications.
• Competency in Python scripting or programming.

Preferred Qualifications:

• Master’s or PhD degree in a relevant technical discipline.
• Experience on large SoC / ASIC designs.
• RF knowledge is a strong plus.
• Understanding of digital signal processing.
• Experience with MATLAB is a plus.
• Background in communications or mobile silicon system design.

Soft Skills:

• Ability to collaborate closely with architecture, verification, software, and system teams.
• Ability to work effectively with internal and external stakeholders.
• Ability to provide technical input during design reviews.

Technology Stack:

• SystemVerilog
• Python scripting or programming
• MATLAB

Physical Requirements

• Ability to work in a standard office environment and use a computer for extended periods.
• Occasional travel may be required to visit suppliers or other AST SpaceMobile design centers.

This job description may not be inclusive to the duties and responsibilities listed. Additional tasks may be assigned to the employee from time to time or the scope of the job may change as needed by business demands. 

At SK Hynix Memory Solution, we're at the forefront of semiconductor innovation, developing advanced memory solutions that power everything from smartphones to data centers. As a global leader in DRAM and NAND flash technologies, we drive the evolution of advancing mobile technology, empowering cloud computing, and pioneering future technologies. Our cutting-edge memory technologies are essential in today's most advanced electronic devices and IT infrastructure, enabling enhanced performance and user experiences across the digital landscape.

We're looking for innovative minds to join our mission of shaping the future of technology. At SK Hynix Memory, you'll be part of a team that's pioneering breakthrough memory solutions while maintaining a strong commitment to sustainability. We're not just adapting to technological change – we're driving it, with significant investments in artificial intelligence, machine learning, and eco-friendly solutions and operational practices. As we continue to expand our market presence and push the boundaries of what's possible in semiconductor technology, we invite you to be part of our journey to creating the next generation of memory solutions that will define the future of computing.

About the Role

As a Staff Security Firmware Test Developer, you’ll be the technical owner of security validation for enterprise SSD firmware — designing, building, and executing test strategies that ensure our drives meet the highest standards for data protection, compliance, and interoperability.

You’ll work at the intersection of firmware, hardware, and security protocols — validating features like Secure Boot, TCG OPAL, SPDM Firmware Attestation, Caliptra 2.1, and OCP NVMe Security Requirements across FPGA and ASIC platforms.

You’ll lead test automation, debug complex failures, and drive quality from design to production — ensuring our firmware is not just functional, but secure by design.

Responsibilities

• Lead end-to-end security validation for enterprise NVMe SSD firmware — from architecture review to production sign-off — ensuring compliance with Secure Boot, TCG OPAL, SPDM Firmware Attestation, Caliptra 2.1, and OCP NVMe Security Requirements.
• Design, build, and maintain automated test frameworks that validate security features across FPGA and ASIC platforms, enabling rapid regression and continuous integration.
• Debug and root-cause complex security failures — working closely with firmware, hardware, and security architects to resolve issues at the protocol or implementation level.
• Define and execute test strategies that prove “secure by design” — not just functional correctness, but cryptographic integrity, attestation, and tamper resistance.
• Own test coverage and quality gates for security-critical features — ensuring no release ships without passing validation against defined security specs.
• Stay ahead of evolving standards — actively track and implement upcoming TCG Storage Spec Requirements and other industry security mandates.
• Collaborate cross-functionally with firmware, hardware, and security teams — translating specs into testable requirements and driving alignment on security validation outcomes.

Minimum Qualifications

• Bachelor’s or Master’s degree in Computer Science, Electrical Engineering, or related field — or equivalent practical experience in firmware or embedded security.
• 5+ years of hands-on experience validating security features in firmware or embedded systems — specifically in NVMe SSDs, storage controllers, or similar hardware platforms.
• Proven experience validating at least 3 of the following:
• Secure Boot (UEFI/TPM/Bootloader)
• TCG OPAL (Self-Encrypting Drive)
• SPDM (Firmware Attestation)
• Caliptra 2.1 (or equivalent hardware root of trust)
• OCP NVMe Security Requirements
• TCG Storage Spec Requirements (upcoming or current)
• Strong experience building and maintaining automated test frameworks for firmware or hardware validation — with scripting (Python,Java, Bash, C) and CI/CD integration.
• Experience debugging low-level firmware/hardware issues — using tools like JTAG, logic analyzers, or firmware logs — with ability to trace failures across protocol layers.
• Working knowledge of NVMe protocol, PCIe, and storage security standards — with ability to read and implement test cases from specs.
• Experience working with FPGA or ASIC platforms — validating firmware behavior in pre-silicon or post-silicon environments.
• Strong ownership mindset — able to define test strategy, drive quality gates, and ensure security validation is not an afterthought, but built into the design.

Preferred Qualifications

• Experience with formal security certification processes (e.g., FIPS 140-3, Common Criteria, ISO 27001, or similar).
• Hands-on experience with Caliptra 2.1 or similar RISC-V-based hardware root of trust architectures.
• Experience with SPDM or similar attestation protocols in production firmware.
• Contributions to open-source security test frameworks or industry standards (e.g., TCG, OCP, NVM Express).
• Experience with security validation in cloud-scale storage environments (e.g., hyperscale data centers, enterprise storage arrays).
• Strong communication skills — able to present technical findings to engineering leadership and security compliance teams.

COMPENSATION: $110,000-$160,000

REGARDING COMPENSATION:

SK hynix memory solutions America Inc. offers you the opportunity to apply your skills to exciting projects while working with innovative teams. Our compensation package is complimented by a generous benefits package including medical, dental, vision, life insurance and a company 401(k) match, as well as cafeteria, onsite gym and much more. If you are motivated by technical challenges, we offer a collaborative work environment that encourages career growth.

The salary offered to a selected candidate will be tailored based on several factors, including the location, job grade, relevant knowledge, skills, and experience. We also take into account the internal equity among our current team members to ensure fairness and competitiveness

The Role 

We are looking for a Principal ASIC Synthesis and Timing Engineer to lead the implementation of complex SoCs for next-generation satellite and space systems. You will own the constraints development and validation—from RTL handoff to synthesis —and collaborate closely with architecture, RTL design, DFT, and physical design team. This role also involves managing external physical design partners, driving convergence of schedule and ensuring first-pass silicon success in advanced FinFET technologies. You’ll be a key contributor in achieving timing closure, optimizing PPA, and supporting design integration with external partners. You will be part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the largest, most powerful, rapidly designed and rapidly manufactured satellites ever deployed in space. In your first 6 months, you will develop and implement new SoC sub-systems for satellite communications and beyond. In your first two years, you will have contributed to developing cutting-edge SoCs that will fly in space. 

Responsibilities 

• Own the complete RTL-to-Synthesis flow: Do synthesis at block and top level, Work with physical design team to integrate the floorplanning information for physical synthesis. 
• Develop and maintain design methodologies, scripts, and automation to optimize performance, power, and area (PPA).
• Collaborate with front-end and verification teams to ensure clean handoffs, timing closure, and efficient design iteration.
• Drive timing closure across multiple voltage and process corners, including sign-off with foundry-qualified tools.
• Own Lint, CDC and UPF checks and drive collaboration to close out issues. 
• Develop an end to end formal verification methodology without any gap to deliver on full confidence functionality between the RTL and the  post layout netlist.
• Manage and technically guide external physical design partners and service vendors, ensuring alignment on milestones, deliverables, and quality standards.
• Work with EDA vendors to debug and optimize tool flows, and evaluate new methodologies.
• Support chip bring-up and debug through close collaboration with post-silicon and test teams.
• Support your product through production and spaceflight.  

Qualifications 

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field
• 10+ years of experience in ASIC design for high-performance SoCs.
• Proven end-to-end expertise in RTL-to-GDSII flows using industry tools (Synopsys, Cadence, or Siemens).
• Strong hands-on experience with timing closure, IR drop analysis, low power implementation and ECO implementation.
• Deep understanding of physical design constraints for multi-clock, multi-voltage, and hierarchical SoCs.
• Experience with advanced FinFET process nodes.
• Prior experience in design convergence with offshore/outsourced PD teams or vendors.
• Able to resolve formal verification issues. 
• Able to analyze and fix VCLP issues regarding UPF.
• Experience with Logic equivalence check debug, Functional ECO development and implementation with minimal database disruption, Low power checker to validate UPF;
• Familiarity with DFT integration, STA sign-off with functional ECO implementation.
• Excellent communication, leadership, and cross-functional collaboration skills.
• Act as technical leader and subject-matter expert helping to teach, grow, and mentor others in the team. 

Nice to Have 

• Exposure to radiation-hardened or space-qualified ASICs.
• Familiarity with physical design service vendor management or offshore collaboration.
• Experience driving tapeouts through TSMC.
• Experience with Gate-All-Around technologies.  
• Experience working in cross-functional, geographically distributed teams.

Compensation and Benefits:

• Base salary range for this role is $190,000 – $280,000 + equity in the company
• Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
• Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks

The Role

We are seeking a Senior Embedded Firmware Engineer to develop and enhance low‑level embedded firmware for high‑performance mixed‑signal and digital SoCs. In this role, you will contribute to the bring‑up, validation, and production readiness of custom silicon by working closely with digital ASIC, mixed‑signal, RF, verification, and system engineering teams. You will help implement core firmware components, validate hardware functionality, and ensure reliable, scalable firmware foundations for next‑generation products.

Responsibilities

• Contribute to the design and implementation of embedded firmware architecture, including boot flows, HAL components, drivers, and system services.
• Develop low‑level firmware in C/C++ (and assembly when required) for CPUs, DSPs, and microcontrollers within custom SoCs.
• Implement and maintain bootloaders, secure boot flows, and early hardware initialization sequences.
• Develop device drivers for on‑chip peripherals such as DMA engines, memory controllers, interconnects, SerDes, ADC/DAC interfaces, timers, and GPIO.
• Participate in pre‑silicon firmware development and validation activities.
• Support post‑silicon bring‑up, including power‑on sequencing, clock/reset initialization, memory bring‑up, and peripheral testing.
• Debug hardware/firmware interactions using JTAG, logic analyzers, oscilloscopes, trace tools, and custom debug instrumentation.
• Collaborate with SoC architects and designers to refine register maps, memory maps, interrupt structures, DMA flows, and debug infrastructure.
• Provide firmware input during design reviews and silicon development milestones.
• Bring up and integrate RTOS or bare‑metal environments.
• Support integration with higher‑level system software or application processors.
• Implement robust error handling, logging, and recovery mechanisms.
• Contribute to manufacturing test firmware, production firmware, and field diagnostics.
• Help ensure long‑term maintainability and scalability of firmware across multiple SoC generations.

Qualifications

• 5+ years of experience in embedded firmware development for SoCs or complex embedded systems.
• Strong proficiency in C/C++ for embedded systems and a solid understanding of low‑level hardware interactions.
• Hands‑on experience with SoC bring‑up or board‑level bring‑up.
• Strong understanding of CPU architectures (ARM, RISC‑V, or similar), memory systems (SRAM, DRAM, DDR, caches), interrupts, DMA, and low‑power states.
• Experience collaborating with ASIC/SoC design or hardware engineering teams.
• Demonstrated ability to debug complex hardware/firmware issues.

Nice to Have

• Experience with secure boot, hardware security modules, or cryptographic accelerators.
• Familiarity with pre‑silicon environments such as RTL simulation, emulation, or FPGA prototyping.
• Experience with high‑speed interfaces (PCIe, Ethernet, JESD, SerDes).
• Background in satellite communication, networking, compute, automotive, or other high‑reliability systems.
• Experience developing firmware for radiation‑tolerant or mission‑critical systems.

Compensation and Benefits:

• Base salary range for this role is $160,000 – $220,000 + equity in the company
• Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
• Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks