Senior FPGA Engineer - Quantum Computing Control Systems

Company Overview

Join QuEra Computing's engineering team to develop cutting-edge FPGA systems for neutral atom quantum computers. You'll work on real-time control systems that manipulate individual atoms with microsecond precision, enabling breakthrough quantum algorithms and applications.

Role Summary

We're seeking a Senior FPGA Engineer to design, implement, and optimize high-performance FPGA systems for quantum computing applications. You'll work on complex real-time control systems, high-speed data acquisition, and precision timing systems that are critical to our quantum computer's operation.

Key Responsibilities

Core FPGA Development

• Design and implement System Verilog modules for quantum control systems including:
• Scheduled multitone generators for RF/microwave quantum gates
• Real-time pulse sequencers for laser control
• High-speed ADC/DAC interfaces (16-bit, 4 samples/clock)
• Hardware-accelerated image processing for atom detection
• Develop and maintain Ulti-board FPGA designs (Xilinx Zynq UltraScale+ RFSoC)
• Implement high-speed serial interfaces (CoaXPress, Aurora, AXI4-Stream)
• Design clock domain crossing logic with proper CDC verification
• Optimize resource utilization and timing closure for complex designs

System Integration & Verification

• Create comprehensive testbenches using System Verilog and Python (cocotb)
• Develop simulation models for quantum control peripherals
• Implement formal verification for critical timing constraints
• Design and validate real-time trigger and synchronization systems
• Troubleshoot hardware-software integration issues

Performance & Reliability

• Optimize data through put for high-bandwidth quantum control signals
• Implement error detection and recovery mechanisms
• Design robust clocking architectures for multi-domain systems
• Develop monitoring and diagnostics for system health
• Ensure deterministic timing for quantum gate operations

Technical Requirements

Essential Skills

• 5+ years FPGA development experience with Xilinx UltraScale+ devices
• Expert-level System Verilog with modern verification methodologies
• Experience with high-speed serial protocols (Aurora, AXI4, PCIe, Ethernet)
• Real-time systems design with microsecond timing requirements
• Digital signal processing implementation in FPGAs
• Clock domain crossing design and verification
• Python programming for test automation and data analysis

Preferred Qualifications

• RF/microwave systems experience (frequency synthesis, phase-locked loops)
• High-speed ADC/DAC interfaces (JESD204B/C, RFSoC experience)
• Image processing algorithms (centroid detection, pattern recognition)
• Formal verification using System Verilog assertions
• CoaXPress or camera interface experience
• AWS/cloud development environments
• Familiar with High Level Synthesis and Vivado block design

Technical Stack

• FPGA Tools: Vivado 2022.2+, Vitis, PetaLinux
• Languages: SystemVerilog, Verilog, Python, TCL
• Verification: UVM, cocotb, pytest, formal verification
• Protocols: AXI4, AXI4-Stream, Aurora, CoaXPress, SPI, I2C
• Boards: Xilinx ZCU102/111/216, RFSoC platforms
• Development: Git, CI/CD, AWS EC2, Linux

Project Examples

You'll work on systems like:

• Quantum Gate Control: 8-channel RF tone generators with 0.1 Hz frequency resolution
• Atom Detection: Real-time image processing at 1+ Gbps data rates
• Precision Timing: Synchronized control sequences with <1 μs jitter
• Data Acquisition: High-speed capture of quantum measurement results
• System Integration: Multi-board coordination for scalable quantum computers

What We Offer

• Cutting-edge technology: Work on the forefront of quantum computing
• High-impact projects: Your code directly enables quantum algorithms
• Technical growth: Learn quantum physics while advancing FPGA skills
• Collaborative environment: Work with physicists, software engineers, and system architects

Success Metrics

• Design Quality: Clean, well-documented, and maintainable SystemVerilog code
• Performance: Meeting timing requirements for real-time quantum control
• Reliability: Robust error handling and system monitoring
• Innovation: Proposing and implementing improvements to quantum control systems
• Collaboration: Effective communication with cross-functional teams

Education & Experience

• Bachelor's/master’s in electrical engineering, Computer Engineering, or Physics
• 5+ years FPGA development with complex, real-time systems
• Experience with quantum computing, RF systems, or precision instrumentation preferred
• Strong problem-solving skills and attention to detail
• Excellent communication skills for technical documentation and team collaboration

Why This Role Matters

Quantum computers represent the next frontier in computing, with potential to revolutionize cryptography, optimization, and scientific simulation. As an FPGA engineer on our team, you'll build the hardware foundation that makes quantum algorithms possible - controlling individual atoms with unprecedented precision to create the quantum states that power breakthrough applications. Your work will directly impact our ability to scale quantum computers and bring quantum advantage to real-world problems. This is an opportunity to shape the future of computing while advancing your technical expertise in cutting-edge FPGA development.

This role offers the unique opportunity to combine advanced FPGA engineering with quantum physics, working on systems that operate at the fundamental limits of precision and timing. If you're passionate about both hardware engineering and quantum computing, this is the perfect role to advance both your technical skills and career.

Salary is 140,000 to 190,000 We consistently monitor external market data and update base salary ranges accordingly.  We determine base compensation decisions on several factors, including as geographic placement, role-specific knowledge, skills, and/or experience.  In addition to our base salary offerings, we also provide equity grants for all new hires.

#LI-DA1

QuEra is committed to cultivating a diverse work environment and is proud to be an equal opportunity employer. We highly value diversity in our current and future employees and do not discriminate (including in our hiring and promotion practices) based on race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status, or any other characteristic protected by law.

At Tenstorrent, we believe the future of computing must be open, which is why our interns don’t just watch from the sidelines – they help build the core of it. We provide a "code-to-career" pipeline where students collaborate with industry experts to solve high-stakes problems in RISC-V and AI hardware-software co-design. By joining us, you are taking an internship to democratize high-performance computers that are accessible to everyone.

As a Design Verification Engineer Intern on the SoC Digital Verification team, you will help ensure the functional correctness and robustness of Tenstorrent’s next-generation RISC‑V and AI accelerator SoCs. You will work on building and improving modern verification environments, developing tests and checkers, and analyzing coverage to sign off complex digital IP and subsystems. Your work directly contributes to the reliability of the chips that power our AI and high‑performance computing roadmap.

We are looking for a minimum of 3 months for this role with the potential for extension to 6 months.

This role is hybrid, based in our Boston, MA office.

Who you are

• Pursuing a B.S. , M.S. or PhD. in Electrical Engineering, Computer Engineering, Computer Science, or a related field with a focus on digital design and verification.
• Strong understanding of digital logic design and computer architecture (pipelines, caches, interconnects, memory systems).
• Familiar with HDLs such as Verilog/SystemVerilog, and interested in learning Formal verification, Cocotb, and UVM‑based verification methodologies.
• Comfortable working in Linux-based development environments and using scripting languages (e.g., Python, Shell, Perl) to automate tasks.
• Detail-oriented problem solver who enjoys debugging complex issues, reasoning about corner cases, and working from specifications.
• Collaborative team member with clear communication skills, able to document work and discuss trade‑offs with RTL, architecture, and validation teams.

What We Need

• Help develop and maintain SystemVerilog/UVM testbenches for SoC IP blocks and subsystems, including stimulus, checkers, and scoreboards.
• Write and refine verification test plans from architectural and micro‑architectural specifications, with a strong focus on corner cases and coverage.
• Develop constrained‑random and directed tests, run regressions, and triage failures by working closely with RTL designers to root-cause issues.
• Analyze functional and code coverage results, identify gaps, and propose additional tests or checks to drive coverage closure.
• Contribute to automation and infrastructure (scripts, Makefiles, CI hooks, dashboards) that improve verification productivity and debug turnaround time.
• Partner with cross‑functional teams (architecture, design, performance, validation) to align on expected behavior and sign‑off criteria for silicon.
• Have impact measured through coverage metrics achieved, quality and reproducibility of bugs found, and robustness of the verification environment you help build.

What You Will Learn

• End‑to‑end SoC design and verification flow for cutting‑edge RISC‑V and AI accelerator architectures.
• Industry‑standard verification methodologies (SystemVerilog/UVM), including testbench architecture, stimulus generation, and scoreboard/checker design.
• Hands-on experience with simulation, regression, and coverage tools used in large‑scale industrial verification environments.
• How to read and interpret hardware specifications, micro‑architecture documents, and timing diagrams, and translate them into actionable tests and assertions.
• Exposure to high‑performance interconnects, memory controllers, and accelerators, and how they are verified at IP, subsystem, and SoC levels.
• Best practices for collaborating in a silicon development team, including code review, documentation, and cross‑site communication.

USA Hiring Timelines

This internship opportunity is available throughout our 3 terms with the following corresponding recruitment cycles:

• Winter Term: Jan–Apr work term, Sept–Dec recruit.
• Summer Term: May–Aug work term, Oct–Apr recruit.
• Fall Term: Sept–Dec work term, Jan–Aug recruit.

Please note these timelines are for reference only. Actual timelines may vary.

We are looking for a Staff Digital Design Engineer to help define, build, and optimize high-performance IP and SoC architectures for next-gen AI and compute workloads. This role is ideal for engineers who thrive at the intersection of microarchitecture, RTL implementation, and performance-aware design.

This role is hybrid, based out of Toronto, Ottawa, Boston, or Austin. 

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A digital design expert with a deep understanding of computer architecture and IP microarchitecture.
• Skilled in RTL development (Verilog/VHDL) and familiar with full ASIC flows.
• Comfortable optimizing for power, performance, and area (PPA) under aggressive design goals.
• A naturally collaborative and technical engineer — you thrive in spec definition, peer reviews, and team-wide planning.

What We Need

• Architecture and RTL implementation of Tenstorrent’s custom IP blocks and SoC components.
• Performance-aware design decisions for compute, interconnect, or memory-heavy blocks.
• Occasional contributions to validation using emulation, FPGA prototyping, or UVM flows.
• Strong synthesis and timing closure awareness to support backend teams.
• Prior experience in on-chip fabric and interconnect designs is an asset.

What You Will Learn

• How cutting-edge AI chips are built, from spec to silicon.
• What it takes to collaborate with teams designing novel processor and memory architectures.
• How to blend custom logic with standard SoC elements for power and scale.
• How cross-functional workflows come together across design, DV, physical, and firmware teams.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

As an Analog Architect, you will spearhead pathfinding efforts and work on early prototypes of innovative analog and mixed-signal solutions for Lighmatter’s next-generation optical-engine products. You will then work closely with the engineering team to take your ideas to high-volume production. This role requires a deep understanding of high-frequency systems-on-chip (SoCs), high-speed (100+ Gbaud) serial and electro-optic interfaces. The role also requires creativity, analytical skills, and clear communication skills. You may represent the company at technical conferences as an example of our technical leadership. 

Join a tight-knit team where each individual’s contributions directly influence the success of the company and product. You'll have the opportunity to build a new kind of computer from the ground up and to solve groundbreaking challenges along the way. Work with people who love to build and who thrive in technically diverse environments where great ideas are prioritized.

Responsibilities

• Architect high-speed (200Gbaud and beyond) electro-optical interfaces for Lightmatter’s next-generation co-packaged optics (CPO) solutions.
• Design next-generation high-speed DACs, linear drivers and TIAs in the latest FinFET process nodes.
• Actively collaborate across disciplines—with electronics, photonics, and mechanical engineering teams—to specify the requirements and solutions for circuit blocks, SoCs, debug, and validation.
• Collaborate with the product team to develop our future technological and product roadmap in the context of industry trends.
• Work closely with test and validation engineers to validate hardware against simulation prediction to ensure high performance and high yield.
• Publish and present novel ideas and participate in premier technical conferences.
  
  

Qualifications

• A Ph.D. degree in Electrical Engineering or similar discipline with at least 5+ years of experience of designing high-speed analog circuits in TSMC N3/N5/N7.
• Hands-on experience in high-speed SERDES design in advanced process nodes (7nm and below).
• Deep technical background and a proven track record of innovation in their area of expertise.
• Strong understanding of how the layout impacts the SERDES performance.
• Familiarity with analyzing the impact of package and PCB on SERDES performance.
• Familiarity with UCIe, PAM4, and other high-speed SerDes.
• Strong background with using circuit and electromagnetic simulation tools needed for high-speed mixed-signal circuit design: Cadence virtuoso, Verilog-A, EMX or equivalent tools.

#LI-FM1

As an Analog Architect, you will spearhead pathfinding efforts and work on early prototypes of innovative analog and mixed-signal solutions for Lighmatter’s next-generation optical-engine products. You will then work closely with the engineering team to take your ideas to high-volume production. This role requires a deep understanding of high-frequency systems-on-chip (SoCs), high-speed (100+ Gbaud) serial and electro-optic interfaces. The role also requires creativity, analytical skills, and clear communication skills. You may represent the company at technical conferences as an example of our technical leadership. 

Join a tight-knit team where each individual’s contributions directly influence the success of the company and product. You'll have the opportunity to build a new kind of computer from the ground up and to solve groundbreaking challenges along the way. Work with people who love to build and who thrive in technically diverse environments where great ideas are prioritized.

Responsibilities

• Architect high-speed (200Gbaud and beyond) electro-optical interfaces for Lightmatter’s next-generation co-packaged optics (CPO) solutions.
• Design next-generation high-speed DACs, linear drivers and TIAs in the latest FinFET process nodes.
• Actively collaborate across disciplines—with electronics, photonics, and mechanical engineering teams—to specify the requirements and solutions for circuit blocks, SoCs, debug, and validation.
• Collaborate with the product team to develop our future technological and product roadmap in the context of industry trends.
• Work closely with test and validation engineers to validate hardware against simulation prediction to ensure high performance and high yield.
• Publish and present novel ideas and participate in premier technical conferences.
  
  

Qualifications

• A Ph.D. degree in Electrical Engineering or similar discipline with at least 5+ years of experience of designing high-speed analog circuits in TSMC N3/N5/N7.
• Hands-on experience in high-speed SERDES design in advanced process nodes (7nm and below).
• Deep technical background and a proven track record of innovation in their area of expertise.
• Strong understanding of how the layout impacts the SERDES performance.
• Familiarity with analyzing the impact of package and PCB on SERDES performance.
• Familiarity with UCIe, PAM4, and other high-speed SerDes.
• Strong background with using circuit and electromagnetic simulation tools needed for high-speed mixed-signal circuit design: Cadence virtuoso, Verilog-A, EMX or equivalent tools.

#LI-FM1