We are looking for an ASIC Design Methodology Engineer to advance our design infrastructure and flows across RTL development, verification, and physical implementation. This role is ideal for engineers who thrive on improving design quality, enabling scalability, and automating methodologies that accelerate silicon success.

This role is hybrid, based out of Toronto, Ottawa, Austin, or Boston.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A strong advocate for design quality and productivity, with expertise in ASIC design flows.
• Skilled in RTL design and familiar with static and dynamic analysis tools.
• Comfortable automating design checks and improving methodology for scalability and reuse.
• A collaborative engineer who partners effectively across RTL, verification, and backend teams.

What We Need

• Develop and maintain ASIC design methodologies and infrastructure for RTL development and integration.
• Own and evolve static code analysis (Lint, CDC, RDC, DFT) and RTL-netlist logic equivalency design methodologies
• Develop synthesis timing constraints (SDC) and low power design specifications (UPF)
• Support RTL-to-GDS flow enablement, ensuring clean handoffs and sign-off readiness.
• Collaborate with EDA vendors and internal tool owners to optimize performance, quality, and runtime.

What You Will Learn

• How large-scale AI SoCs are architected, integrated, and brought to silicon.
• How methodology choices directly impact design performance, power, and verification closure.
• How to build and scale ASIC design flows supporting cutting-edge compute architectures.
• How to integrate cross-functional workflows across design, DFT, DV, physical, and firmware teams.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

We are looking for a Staff Digital Design Engineer to help define, build, and optimize high-performance IP and SoC architectures for next-gen AI and compute workloads. This role is ideal for engineers who thrive at the intersection of microarchitecture, RTL implementation, and performance-aware design.

This role is hybrid, based out of Toronto, Ottawa, Boston, or Austin. 

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A digital design expert with a deep understanding of computer architecture and IP microarchitecture.
• Skilled in RTL development (Verilog/VHDL) and familiar with full ASIC flows.
• Comfortable optimizing for power, performance, and area (PPA) under aggressive design goals.
• A naturally collaborative and technical engineer — you thrive in spec definition, peer reviews, and team-wide planning.

What We Need

• Architecture and RTL implementation of Tenstorrent’s custom IP blocks and SoC components.
• Performance-aware design decisions for compute, interconnect, or memory-heavy blocks.
• Occasional contributions to validation using emulation, FPGA prototyping, or UVM flows.
• Strong synthesis and timing closure awareness to support backend teams.
• Prior experience in on-chip fabric and interconnect designs is an asset.

What You Will Learn

• How cutting-edge AI chips are built, from spec to silicon.
• What it takes to collaborate with teams designing novel processor and memory architectures.
• How to blend custom logic with standard SoC elements for power and scale.
• How cross-functional workflows come together across design, DV, physical, and firmware teams.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

We are hiring a Digital Design Engineer to help develop an ASIC for the next-generation artificial intelligence computing architecture alongside a team of world-class scientists and engineers. If your passion is innovation, solving challenging technical problems, and doing impactful work, you should join our team and help build the world's first optical computers!

In this job, you will work in close collaboration with computer architects, software engineers, verification engineers, and physical design engineers to design innovative compute accelerators that work with photonic technology to power the growing AI/ML workloads that customers want while keeping power low. This will be a great opportunity to define the next advance in computer architecture!

Responsibilities

• Develop microarchitecture design and RTL for advanced ML/AI accelerator ASICs/SoCs including advanced memory system and high-performance NoC.
• Understand and integrate silicon photonic communication and compute technology into digital accelerator design.
• Actively work with Architecture, Design Verification, Implementation, Photonic, Analog and Software teams to realize high performance, low power designs in advanced technology nodes.
• Create design specifications and documentation to facilitate collaboration with partner teams.
• Manage RTL implementation to achieve functionally correct, performant designs within project schedules by identifying, communicating and mitigating risks.

Qualifications

• 8 years of related experience with a Bachelor’s degree; or 6 years and a Master’s degree in Electrical or Computer Engineering (or related fields)
• Experience in ASIC design with multiple successful tape outs
• Expertise with high-speed digital design techniques
• Expertise with power-efficient digital design techniques

Preferred Qualifications

• Experience in communication protocols (e.g. PCIe)
• Experience interfacing with memory systems (e.g. HBM/DDR5)
• Knowledge of processor design, accelerators, and/or memory hierarchies
• Knowledge of machine learning algorithms

We are hiring a Digital Design Engineer to help develop an ASIC for the next-generation artificial intelligence computing architecture alongside a team of world-class scientists and engineers. If your passion is innovation, solving challenging technical problems, and doing impactful work, you should join our team and help build the world's first optical computers!

In this job, you will work in close collaboration with computer architects, software engineers, verification engineers, and physical design engineers to design innovative compute accelerators that work with photonic technology to power the growing AI/ML workloads that customers want while keeping power low. This will be a great opportunity to define the next advance in computer architecture!

Responsibilities

• Develop microarchitecture design and RTL for advanced ML/AI accelerator ASICs/SoCs including advanced memory system and high-performance NoC.
• Understand and integrate silicon photonic communication and compute technology into digital accelerator design.
• Actively work with Architecture, Design Verification, Implementation, Photonic, Analog and Software teams to realize high performance, low power designs in advanced technology nodes.
• Create design specifications and documentation to facilitate collaboration with partner teams.
• Manage RTL implementation to achieve functionally correct, performant designs within project schedules by identifying, communicating and mitigating risks.

Qualifications

• 8 years of related experience with a Bachelor’s degree; or 6 years and a Master’s degree in Electrical or Computer Engineering (or related fields)
• Expertise with high-speed digital design techniques
• Expertise with power-efficient digital design techniques
• Experience in ASIC design with multiple successful tape outs

Preferred Qualifications

• Experience in communication protocols (e.g. PCIe)
• Experience interfacing with memory systems (e.g. HBM/DDR5)
• Knowledge of processor design, accelerators, and/or memory hierarchies
• Knowledge of machine learning algorithms

We are hiring a Digital Design Engineer to help develop an ASIC for the next-generation artificial intelligence computing architecture alongside a team of world-class scientists and engineers. If your passion is innovation, solving challenging technical problems, and doing impactful work, you should join our team and help build the world's first optical computers!

In this job, you will work in close collaboration with computer architects, software engineers, verification engineers, and physical design engineers to design innovative compute accelerators that work with photonic technology to power the growing AI/ML workloads that customers want while keeping power low. This will be a great opportunity to define the next advance in computer architecture!

Responsibilities

• Develop microarchitecture design and RTL for advanced ML/AI accelerator ASICs/SoCs including advanced memory system and high-performance NoC.
• Understand and integrate silicon photonic communication and compute technology into digital accelerator design.
• Actively work with Architecture, Design Verification, Implementation, Photonic, Analog and Software teams to realize high performance, low power designs in advanced technology nodes.
• Create design specifications and documentation to facilitate collaboration with partner teams.
• Manage RTL implementation to achieve functionally correct, performant designs within project schedules by identifying, communicating and mitigating risks.

Qualifications

• 8 years of related experience with a Bachelor’s degree; or 6 years and a Master’s degree in Electrical or Computer Engineering (or related fields)
• Expertise with high-speed digital design techniques
• Expertise with power-efficient digital design techniques
• Experience in ASIC design with multiple successful tape outs

Preferred Qualifications

• Experience in communication protocols (e.g. PCIe)
• Experience interfacing with memory systems (e.g. HBM/DDR5)
• Knowledge of processor design, accelerators, and/or memory hierarchies
• Knowledge of machine learning algorithms