The Role 

We are seeking a Senior ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ownership, deep technical engagement, and the opportunity to shape first-generation silicon. 

Responsibilities 

• Develop and execute verification plans for block-level, subsystem-level, and full-chip environments. Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models.
• Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate.
• Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios.
• Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues.
• Implement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off.
• Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug iterations.
• Participate in design reviews, microarchitecture discussions, and influence design-for-verification (DFV) best practices.
• Work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers to ensure end-to-end coverage and test.
• Support silicon bring-up and post-silicon validation through test reuse, diagnostics, and debug analysis.
• Participate in ASIC team interviews.
• Contribute to advancement of DV methodologies and improvements.
• Engage external IP providers and verification partners when needed. 

Qualifications 

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
• 5+ years of experience in ASIC/SoC verification.
• Solid understanding of SystemVerilog, digital logic, RTL design, and hardware verification flows.
• Proficiency with a simulation (VCS, Xcelium, Questa), waveform debug (Verdi, SimVision), coverage tool, and scripting languages (ex: Python, Perl, TCL).
• Experience with testplanning, UVM-based testbench development, constrained-random testing, functional coverage, and SystemVerilog assertions.
• Experience with regression management, coverage analysis, revision control (Git), and CI/CD automation.
• Understanding of several industry-standard interfaces (ex: APB/AHB/AXI).
• Familiarity with embedded processor-based designs and firmware/bare metal coding (ex: C, C++). 

Nice to Have

• Experience with developing and integrating reference models.
• Understanding of low power verification.
• Familiarity with gate-level simulation and analog behavioral models.
• Involvement in post-silicon validation planning and execution.
• Experience working in cross-functional, geographically distributed teams.
• Experience in space, telecom, or RF/digital mixed systems is a plus. 
  

Compensation and Benefits:

• Base salary range for this role is $170,000 – $250,000 + equity in the company
• Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
• Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks

The Role 

We are seeking a Principal ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ownership, deep technical engagement, and the opportunity to shape first-generation silicon. 

Responsibilities 

• Develop and execute verification plans for block-level, subsystem-level, and full-chip environments.
• Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models.
• Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate.
• Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios.
• Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues.
• Implement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off.
• Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug iterations.
• Participate in design reviews, microarchitecture discussions, and influence design-for-verification (DFV) best practices.
• Work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers to ensure end-to-end coverage and test.
• Support silicon bring-up and post-silicon validation through test reuse, diagnostics, and debug analysis.
• Participate in ASIC team interviews.
• Drive advancement of DV methodologies and improvements.
• Manage external IP providers and verification partners when needed.
• Take lead on large and/or complex systems. 

Qualifications 

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
• 10+ years of experience in ASIC/SoC verification.
• Solid understanding of SystemVerilog, digital logic, RTL design, DFT, and hardware design and verification flows.
• Proficiency with several simulation (VCS, Xcelium, Questa), waveform debug (Verdi, SimVision), coverage tools, and scripting languages (ex: Python, Perl, TCL).
• Experience with test planning, UVM-based testbench development, constrained-random testing, functional coverage, and SystemVerilog assertions.
• Experience with regression management, coverage analysis, revision control (ex: Git), CI/CD automation, and gate-level simulation.
• Experience with developing and integrating reference models.
• Experience with embedded processor-based designs and firmware/bare metal coding (ex: C, C++).
• Understanding of many industry-standard interfaces (ex: APB/AHB/AXI).
• Involvement in post-silicon validation planning and execution. 

Nice to Have

• Experience with low power verification.
• Experience with analog behavioral models.
• Familiarity with physical design flows.
• Experience working in cross-functional, geographically distributed teams.
• Experience in space, telecom, or RF/digital mixed systems is a plus. 

Compensation and Benefits:

• Base salary range for this role is $190,000 – $285,000 + equity in the company
• Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
• Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks

The Role

We are seeking a Principal ASIC Package Design Engineer to lead advanced ASIC package architecture and execution, with a strong focus on flip-chip BGA (FC-BGA) and multi-chip module (MCM) solutions. This role owns the end-to-end package strategy for high-performance mixed-signal and digital SoCs from early architecture and trade studies through vendor engagement, qualification, and production ramp. You will operate as the technical authority for package design, defining standards, influencing silicon and system architecture, and ensuring first-pass success for complex, high-speed, power-dense ASICs.

Responsibilities

• Own ASIC package architecture for FC-BGA and MCM solutions, including substrate stack-up, ball-map strategy, power delivery, signal breakout, and mechanical constraints.
• Lead package-level trade studies across cost, performance, power integrity (PI), signal integrity (SI), thermal, manufacturability, and reliability.
• Define long-term packaging roadmap aligned with future ASIC nodes, bandwidth scaling, and multi-die integration.
• Establish organizational package design standards, methodologies, and best practices.
• Drive detailed design of FC-BGA packages for high-pin-count ASICs with high-speed SerDes, dense power grids, and RF signal content.
• Define and review substrate stack-ups, via strategies, impedance control, escape routing, and reference plane planning.
• Partner with silicon, RF, and systems teams to co-optimize die floorplans and package interfaces.
• Own package-level SI/PI strategy, including high-speed digital interfaces (e.g., SerDes, JESD, Interlaken), power delivery network (PDN) design, and decoupling strategy
• Lead thermal architecture at the package level, including lid selection, TIMs, heat-spreaders, and mechanical interfaces to system cooling.
• Serve as the primary technical interface to substrate vendors, assembly houses, and OSATs.
• Drive material selection, substrate technology choices, and assembly process optimization.

Qualifications 

• Bachelor’s degree in Packaging Engineering, Mechanical Engineering, Electrical Engineering, or a related field.
• 10+ years of experience in ASIC package design, with deep expertise in FC-BGA.
• Proven experience delivering high-pin-count, high-performance ASIC packages into production.
• Strong understanding of substrate technologies and materials, SI/PI fundamentals at the package level, and thermal management for power-dense ASICs.
• Fluent in SI/PI and EM simulation tools such as SIWave, HFSS, and ADS.
• Experience working directly with OSATs and substrate vendors.
• Knowledge of packaging qualification and test methodologies.

Nice to Have

• Experience with MCM or heterogeneous integration (chiplets, interposers, advanced laminates).
• Background in high-speed digital or mixed-signal SoCs.
• Familiarity with aerospace, space, or high-reliability electronics.
• Experience defining packaging strategy from early architecture through first silicon and volume ramp.
• Demonstrated history of building or scaling package design methodology within an organization.

Compensation and Benefits:

• Base salary range for this role is $200,000 – $280,000 + equity in the company
• Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
• Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks

The Role 

We are seeking an ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ownership, deep technical engagement, and the opportunity to shape first-generation silicon. 

Responsibilities 

• Develop and execute verification plans for block-level, subsystem-level, and full-chip environments.
• Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models.
• Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate.
• Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios.
• Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues.
• Implement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off.
• Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug iterations.
• Participate in design reviews and microarchitecture discussions. 

Qualifications 

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
• 3+ years of experience in ASIC/SoC verification.
• Solid understanding of SystemVerilog, digital logic, and hardware verification flows.
• Proficiency with a simulation (VCS, Xcelium, Questa), waveform debug (Verdi, SimVision) and coverage tool.
• Experience with test planning, testbench development, constrained-random testing, and coverage analysis.
• Familiarity with a scripting language (ex: Python, Perl, TCL) and revision control system (ex: Git). 

Nice to Have

• Experience with UVM-based testbench development, functional coverage, SystemVerilog assertions, and regression management.
• Familiarity with developing and integrating reference models.
• Understanding of RTL design flows and some industry standard interfaces (ex: APB/AHB/AXI).
• Experience working in cross-functional, geographically distributed teams.
• Experience in space, telecom, or RF/digital mixed systems is a plus. 

Compensation and Benefits:

• Base salary range for this role is $130,000 – $200,000 + equity in the company
• Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
• Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks

The Role 

We are seeking a Senior ASIC Package Design Engineer to implement advanced ASIC package architecture, with a strong focus on flip-chip BGA (FC-BGA) and multi-chip module (MCM) solutions. This role supports the end-to-end package strategy for high-performance mixed-signal and digital SoCs from early architecture and trade studies through vendor engagement, qualification, and production ramp. You will collaborate with internal teams for package design, defining standards, influencing silicon and system architecture, and ensuring first-pass success for complex, high-speed, power-dense ASICs.  

Responsibilities 

• Define ASIC package architecture for FC-BGA and MCM solutions, including substrate stack-up, ball-map strategy, power delivery, signal breakout, and mechanical constraints.
• Lead package-level trade studies across cost, performance, power integrity (PI), signal integrity (SI), thermal, manufacturability, and reliability.
• Establish package design standards, methodologies, and best practices.  
• Drive detailed design of FC-BGA packages for high-pin-count ASICs with high-speed SerDes, dense power grids, and RF signal content.
• Define and review substrate stack-ups, via strategies, impedance control, escape routing, and reference plane planning.
• Partner with silicon, RF, and systems teams to co-optimize die floorplans and package interfaces. 
• Support package-level SI/PI strategy, including high-speed digital interfaces, power delivery network (PDN) design, and decoupling strategy
• Lead thermal architecture at the package level, including lid selection, TIMs, heat-spreaders, and mechanical interfaces to system cooling. 
• Drive material selection, substrate technology choices, and assembly process optimization.  

Qualifications 

• Bachelor’s degree in Packaging Engineering, Mechanical Engineering, Electrical Engineering, or a related field.
• 5+ years of experience in ASIC package design, with deep expertise in FC-BGA.
• Proven experience delivering high-pin-count, high-performance ASIC packages into production.
• Strong understanding of substrate technologies and materials, SI/PI fundamentals at the package level, and thermal management for power-dense ASICs.
• Fluent in SI/PI and EM simulation tools such as SIWave, HFSS, and ADS.
• Experience working directly with OSATs and substrate vendors.
• Knowledge of packaging qualification and test methodologies. 

Nice to Have

• Experience with MCM or heterogeneous integration (chiplets, interposers, advanced laminates). 
• Background in high-speed digital or mixed-signal SoCs. 
• Familiarity with aerospace, space, or high-reliability electronics. 
  

Compensation and Benefits:

• Base salary range for this role is $180,000 – $260,000 + equity in the company
• Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
• Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks

THE OPPORTUNITY

Silvus is seeking a Senior FPGA Design Engineer- Signal Processing reporting to the Director of FPGA Engineering on the FPGA Engineering team. The successful individual in this role will participate in all aspects of the research and development process from concept to field deployment.  FPGA Design Engineers are responsible for the efficient implementation of novel signal processing algorithms for Silvus' MIMO wireless networking products. In addition, they participate in the support and development of FPGA-based designs for our advanced wireless systems R&D.  These are exciting projects targeted to address challenging real-world communication needs. 

This position is based at Silvus Technologies’ headquarters in the heart of vibrant West Los Angeles, CA, and is on a hybrid schedule.  A minimum of 3 days onsite per week is expected. On-site days are Mondays, Wednesdays, and Thursdays.

The following is a list of at least some of the current essential job functions of the position. Management may assign or reassign duties and responsibilities at any time at its discretion.

ROLE AND RESPONSIBILITIES

• Digital design architecting for wireless communication projects.
• Fixed point design of signal processing blocks while working with systems engineers.
• RTL coding, simulation, and test bench development.
• FPGA synthesis and timing closure.
• Hardware verification and troubleshooting; familiarity with logic analyzers.
• Provide support to the RF and Software Engineering teams.
• Perform other related duties of which the above are representative.

REQUIRED QUALIFICATIONS

• Bachelor of Science degree in Electrical Engineering, Computer Science, or related fields.
• Minimum 6 years of demonstrated experience in FPGA design; OR 4 years of FPGA design experience with a Master of Science degree; OR 2 years of FPGA design experience with a PhD degree.
• Demonstrated experience with fixed point binary arithmetic and digital signal processing designs.
• Proven expertise working with multiple clock-domain, high-utilization FPGA designs.
• Experience with Xilinx FPGAs, SoCs, and the Vivado IDE.
• Must be U.S. Person (U.S. Citizen, or Permanent Resident) due to clients under U.S. federal contracts.
• All employment is contingent upon the successful clearance of a background check and drug test.

PREFERRED KNOWLEDGE, SKILLS, AND ABILITIES

• Master of Science degree in Electrical Engineering (MSEE).
• Experience using MATLAB.
• Experience with communication systems on FPGA or ASIC designs.

WORKING CONDITIONS AND PHYSICAL REQUIREMENTS

• Office environment.
• Occasional exposure to heat, cold, and allergens while performing tests or demonstrations in the field.
• While performing the duties of this job, the employee is required to do the following:
  • Lift equipment up to 20 lbs. for the set-up of demonstrations and testing.
  • Perform bending and reaching movements to place items on lower and higher shelves.
  • Kneeling or squatting to access lower shelves.
  • Walking/Moving in the labs.

THE OPPORTUNITY

Silvus is seeking a Principal FPGA / RTL Design Engineer- Signal Processing who will report to the Director of FPGA Engineering on the FPGA Engineering team. The successful individual in this role will participate in all aspects of the research and development process from concept to field deployment.  FPGA Design Engineers are responsible for the efficient implementation of novel signal processing algorithms for Silvus' MIMO wireless networking products. In addition, they participate in the support and development of FPGA-based designs for our advanced wireless systems R&D.  These are exciting projects aimed at addressing challenging real-world communication needs. 

This Principal FPGA / RTL Design Engineer position is based at Silvus headquarters in the heart of vibrant West Los Angeles, CA and is on a hybrid schedule.  A minimum of 3 days onsite per week is expected. On-site days are Mondays, Wednesdays, and Thursdays.

The following is a list of at least some of the current essential job functions of the position. Management may assign or reassign duties and responsibilities at any time at its discretion.

ROLE AND RESPONSIBILITIES

• Working with system engineers and digital design architecting for wireless communication projects, including fixed point design of signal processing blocks.
• RTL coding, simulation, and test bench development.
• FPGA synthesis and timing closure.
• Hardware verification and troubleshooting; familiarity with logic analyzers.
• Provide support to the RF and Software Engineering Teams.

REQUIRED QUALIFICATIONS

• Bachelor of Science degree in Electrical Engineering, Computer Science, or related fields.
• Minimum 10 years of demonstrated experience in RTL design and FPGA implementation; 8 years of experience in RTL design and FPGA implementation with an advanced degree (MS or PhD) in Electrical Engineering, Computer Science, or related fields.
• Demonstrated experience with fixed point binary arithmetic and digital signal processing (DSP) designs.
• Deep knowledge of RTL design fundamentals using Verilog and System-Verilog.
• Proven expertise working with front-end RTL design tools, FPGA synthesis, timing closure, multiple clock-domain and/or high-utilization FPGA designs.
• Experience with Xilinx FPGAs, SoCs, and the Vivado IDE
• Must be U.S. Person (U.S. Citizen, or Permanent Resident) due to clients under U.S. federal contracts
• All employment is contingent upon the successful clearance of a background check.

PREFERRED KNOWLEDGE, SKILLS, AND ABILITIES

• MS. or Ph.D. degree in Electrical Engineering, Computer Science, or relevant fields.
• Basic MATLAB skills.
• Solid knowledge and understanding of scripting languages such as Perl and Python.
• Strong communication and presentation skills.
• Experience with wireless communication systems on FPGA or ASIC designs.

WORKING CONDITIONS & PHYSICAL REQUIREMENTS

• Office environment.
• Occasional exposure to heat, cold, and allergens while performing tests or demonstrations in the field.
• While performing the duties of this job, the employee is required to do the following:
  • Lift equipment up to 20 lbs. for the set-up of demonstrations and testing.
  • Perform bending and reaching movements to place items on lower and higher shelves.
  • Kneeling or squatting to access lower shelves.
  • Walking/Moving in the labs