Tenstorrent is looking  for a STA methodology engineer who owns timing across advanced-node, high-performance, low-power designs, bringing deep expertise with PrimeTime, noise/crosstalk/OCV analysis, and strong scripting skills. They will lead the development and optimization of end-to-end STA methodologies and flows, drive data- and ML-assisted timing automation, and partner closely with logic, physical design, DFT, and EDA vendors to solve complex timing challenges across multiple IPs and products. 

This role is hybrid, based out of Santa Clara, CA, Austin, TX, or Fort Collins, CO.

We welcome candidates at various experience levels. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting

Who you are

• An experienced Static Timing Analysis (STA) / timing methodology engineer with a BS/M in Electrical or Computer Engineering (or equivalent experience) 5+ years in industry, focused on high-performance and low-power designs at advanced technology nodes. As well as a deep knowledge of STA tools and techniques, including noise, crosstalk, and OCV analysis.
• You are fluent with PrimeTime and related signoff tools (e.g., PT-SI, PTPX, PT-ECO) and have extensive hands-on experience driving signoff correlation, advanced static timing analysis, and signoff closure.
• You are strong at debugging timing constraints, resolving timing correlation issues, and developing effective timing closure strategies.
• You write robust, production-quality scripts in Tcl, Python, and/or Perl and are comfortable building and maintaining CAD utilities and flow components.

What we need

• A senior methodology owner to lead cross-functional efforts to solve complex timing challenges across multiple IPs, projects, and technology nodes. Experience developing and enhancing STA methodologies across the full RTL-to-GDS flow, including: Early timing estimation and timing feasibility checks. Timing optimization techniques in synthesis and place-and-route. Timing signoff methodologies and criteria. Post-route timing ECO strategies and execution.
• A technical leader to architect, optimize, and maintain production STA flows using industry-standard EDA tools, continuously improving PPA (Power, Performance, Area) and runtime efficiency.
• A methodology engineer who can explore and deploy data-driven and ML-assisted techniques to: Improve STA automation. Predict and prioritize timing risk. Guide optimization strategies across blocks and full-chip. Design, implement, and maintain scalable CAD utilities and STA flow components that improve PPA, robustness, and team productivity.
• A methodology owner who continuously refines workflows and introduces new technologies to ensure robust, PPA-optimized timing solutions across all product lines.

What you will learn

• How to scale STA methodologies across a diverse portfolio of IP and SoC programs, balancing aggressive performance targets with strict power and area constraints.
• Best practices for integrating data-driven and ML-assisted approaches into timing flows to improve automation, predictability, and decision-making.
• How to influence tool roadmaps by partnering closely with leading EDA vendors on advanced-node timing, noise, and variability challenges.
• How to operate within and help shape a rapidly evolving startup design environment, including tradeoffs between quick solutions and long-term methodology investments.
• Deeper cross-functional insight into how logic design, physical design, and DFT interact with STA methodology, and how to build flows that serve all of these stakeholders effectively.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This position requires access to technology that requires a U.S. export license for persons whose most recent country of citizenship or permanent residence is a U.S. EAR Country Groups D:1, E1, or E2 country. 

About us 

Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. 

As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. 

Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation. 

Job Summary 

We are seeking an experienced Staff UEFI Engineer to design, develop, and deploy UEFI-based firmware for Graphcore’s hyperscale AI server platforms. 

This role focuses on developing system firmware responsible for platform initialization, hardware configuration, and reliability features across large-scale data center deployments. 

The Team 

Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. 

The Firmware Engineering team develops the foundational firmware responsible for platform initialization, hardware configuration, and system reliability across Graphcore’s AI compute infrastructure. 

The team collaborates with silicon engineering, hardware design teams, BMC firmware teams, validation engineers, and platform architects to enable reliable server platform bring-up and operation. 

Responsibilities and Duties 

• Design, develop, and deploy UEFI-based firmware for hyperscale server platforms. 

• Collaborate with ODM partners throughout the design lifecycle from concept to mass production. 

• Integrate UEFI firmware into CI/CD pipelines enabling automated builds, regression testing, and static analysis. 

• Develop firmware functionality supporting platform initialization including CPU, memory, PCIe, and system interconnects. 

• Implement system firmware security features including root of trust, secure boot chains, and signed firmware updates. 

• Develop platform firmware features supporting server reliability, availability, and serviceability (RAS). 

• Build firmware interfaces supporting telemetry, firmware updates, and system management capabilities. 

• Collaborate with hardware, BMC, security, and validation teams to ensure full platform integration. 

• Debug and perform root cause analysis for firmware and hardware issues across lab and production environments. 

Candidate Profile 

Essential 

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related discipline. 

• 10+ years of experience developing UEFI or BIOS firmware for server platforms. 

• Strong expertise with UEFI, TianoCore, and firmware architecture design. 

• Experience developing firmware solutions for hyperscale or cloud data center environments. 

• Strong programming skills in C/C++. 

• Deep understanding of DDR memory training, cache coherency protocols, and PCIe subsystems. 

• Strong knowledge of server platform architecture including power delivery, thermal management, sensors, and FRUs. 

• Experience implementing CI/CD pipelines for firmware development. 

• Experience debugging system firmware using logic analyzers, JTAG, GDB, and similar tools. 

Desirable 

• Experience developing UEFI firmware for ARM-based server platforms. 

• Experience with EDK II codebase development and upstream contribution. 

• Experience working with ODM/JDM partners on server platform development programs. 

• Experience delivering firmware for hyperscale cloud deployments and production environments. 

Benefits:

In addition to a competitive salary, Graphcore offers a competitive benefits package. We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments. 

Do you want to be a part of the clean energy movement? Are you passionate about improving our environment for this generation and those to follow? Are you ready to take on new challenges and collaborate with a future-focused team leading the way into new markets? Join Nexamp! 

This is where you can learn from industry leaders and become one yourself. It's fast-paced, mission-based work that challenges the status quo. Be on the team that's changing the world. 

What we’re looking for: 

The Transmission & Power Markets Engineer supports Nexamp’s Utility-Scale Solar + Storage Business Development team by leading the analytical work needed to understand transmission and interconnection opportunities, risks, and costs across target ISO/ RTOs. This role evaluates transmission constraints, pricing, congestion, and curtailment risk to inform site selection, queue strategy, project sizing, and investment decisions for utility-scale solar and storage projects. It is well-suited to candidates with a power systems background or technical project/program management experience in the power sector who are comfortable owning analytical workstreams while coordinating cross-functional stakeholders.

We are accepting candidates across our offices of Boston, MA, Chicago, IL, Austin, TX, etc. where you will be hybrid. You will report to the Manager, Transmission & Market Analytics. 

What you’ll do: 

• Lead transmission and interconnection analysis for utility-scale solar and storage projects across target ISO/RTOs (e.g., MISO, PJM, NYISO, ERCOT, etc.), including assessment of headroom, constraints, congestion, and curtailment risk.
• Plan and execute analytical workstreams (including 3rdparty studies) for each project including defining scope and assumptions, coordinating timelines with interconnection and development milestones, and tracking study status, risks, and decisions.
• Perform and/or direct power system analyses (e.g., load flow, contingency, transfer capability, hosting capacity) and market analytics, translating results into clear commercial metrics and recommendations (e.g., POI choice, queue vintage, hybrid vs. solar only, storage sizing).
• Manage and coordinate external consultants performing technical and economic evaluations (e.g., PSS/E, TARA/PSLF studies, congestion/capacity market analytics), ensuring high quality deliverables, alignment with Nexamp’s objectives, and effective handoff to internal stakeholders.
• Synthesize complex analysis into decision ready materials (slides, memos, dashboards) that clearly articulate options, risks, and tradeoffs for Business Development, Finance, and senior leadership.
• Track and communicate market and policy changes (e.g., LRTP/RTEP, queue reforms, cost allocation, major network upgrades) and maintain trackers of key network projects and neighboring generators that affect project headroom, congestion, and strategy.
• Support interconnection and commercial strategy by contributing to cluster applications, reapplications, material modification decisions, and transaction diligence, and by providing ad hoc analytics to greenfield development, M&A, regulatory, and finance teams as needed.

What you’ll bring:

• Bachelor’s degree in electrical engineering or a closely related engineering/quantitative field (e.g., power systems, energy systems, physics with environmental science focus) with strong exposure to power systems or electricity markets.
• 2+ years of relevant experience in power systems, transmission planning, interconnection, market analytics, or technical project/program management in the power sector (utility, ISO/RTO, IPP, or consulting).
• Solid understanding of the electric transmission system, including concepts such as thermal limits, voltage performance, contingency analysis, transfer capability, and congestion.
• Experience working with Microsoft Excel and other data tools (e.g., SQL, Python, Power BI, or similar) to organize, analyze, and visualize data.
• Proven experience managing complex technical projects or study workstreams, including scoping, timeline management, coordination of contributors, and clear communication of status, risks, and decisions.
• Ability to synthesize complex technical and commercial topics into clear, concise outputs for nontechnical stakeholders.
• Hands on use of power system analysis tools such as Siemens PSS/E, PowerGEM TARA, PSLF, or similar is a plus.
• Experience as a technical project manager/engineer or program manager supporting grid, interconnection, or market analytics initiatives is a plus.
• Prior experience with MISO, PJM, ERCOT, NYISO, CAISO, or other ISO/RTO interconnection processes, including cluster studies, milestone structures, and upgrade cost allocation is a plus.
• Commitment to Nexamp's mission and have a passion for solving tomorrow's climate crisis today.
• Demonstrated experience in effectively communicating information, ideas, and perspectives with people inside and beyond your organization.   
• Experience in showcasing initiative to make improvements to current work, processes, products, and services across the organization. We value accountability and an ownership mentality. 
• Ability to ask appropriate questions, analyze data, identify the root causes of problems, and present creative solutions. 
• Expertise in building strong internal and external relationships with customers and stakeholders, instilling trust and loyalty across the industry. 
• Eagerness to develop a fundamental understanding of how Nexamp operates and then apply that knowledge effectively to inform business decisions.

If you don’t meet 100% of the above qualifications, but see yourself contributing, please apply.

 At Nexamp, our mission is to build the future of energy so it is clean, simple, and accessible for all. We are committed to providing a work environment free from discrimination. We are proud to be an equal opportunity employer. We do not discriminate against applicants on the basis of race, ethnicity, religion, sex, gender, sexual orientation, gender identity, disability status, veteran status, or any other basis protected by law. By encouraging a culture where ideas and decisions come from all people, we believe it will help us grow, innovate, and be a part of environmental and social change.

You’ll love working here because:  

Not only will you get to take part in meaningful work and have the chance to change the world alongside innovative, dedicated, and motivated peers, but you will also have access to all the benefits that Nexamp offers! This includes our competitive compensation package; a 401(k) employer-match; health, dental, and vision insurance starting day one; flexible paid time off and holiday PTO; commuter benefits, and cell phone reimbursement. We have headquarters in Boston, MA and Chicago, IL, in addition to growing offices nationwide. We provide healthy snacks, coffee, service days and other volunteer opportunities, company outings, and more!  

The reasonably estimated salary for this role at Nexamp ranges from $88K-$100K. In addition to base salary, the competitive compensation package may include, depending on the role, participation in an incentive program linked to performance (for example, annual bonus programs based on individual and company performance, non-annual sales incentive plans, or other non-annual incentive plans). Additionally, you may be eligible to participate in the Company’s stock option plan. Actual base salary may vary based upon, but is not limited to, skills and qualifications, internal equity, performance, and geographic location. 

Nexamp's People team manages all aspects of recruitment and hiring within our organization. We want to inform third-party recruiters, staffing firms, and related agencies that Nexamp does not accept unsolicited resumes. Resumes will only be considered from these entities if a signed agreement is in place and the People team explicitly authorizes external recruiting assistance for a specific position. Any unsolicited resumes received will be deemed the property of Nexamp. We want to emphasize that Nexamp is not liable for any fees associated with unsolicited resumes.

Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption.   

As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Austin, which will play a central role in Graphcore's work building the future of AI computing. 

The Electrical Engineer will play a pivotal role in designing innovative hardware systems for AI/ML applications. We are seeking a motivated Electrical Engineer with 2–4 years of experience in schematic capture, PCB design, and server hardware development. This role includes close collaboration with multiple partners to drive designs from concept through mass production. The ideal candidate is comfortable working across organizational boundaries, ensuring design quality, manufacturability, and on-time delivery in a fast-paced environment.

Responsibilities:

• Develop and maintain electrical schematics for various printed circuit assemblies
• Design and layout multilayer PCBs
• Work closely with partners to review designs, provide technical guidance, and ensure alignment with system requirements
• Drive design for manufacturability (DFM), design for assembly (DFA), and design for testability (DFT)
• Support server subsystem integration
• Participate in design reviews
• Support prototype builds, board bring-up, debugging, and validation
• Track and resolve design issues, including root cause analysis and corrective actions
• Ensure proper documentation, revision control, and engineering change management (ECO/ECN processes)

Requirements:

• Bachelor’s degree in electrical engineering
• 2–4 years of experience in schematic capture and PCB design
• Proficiency with PCB design and schematic tools
• Strong understanding of analog and digital circuit design fundamentals
• Experience with multilayer PCB layout
• Experience with lab equipment (oscilloscope, multimeter, logic analyzer)

Differentiators:

• Experience with server platforms or data center hardware
• Knowledge of power delivery network (PDN) design for high-power systems
• Familiarity with signal integrity and power integrity analysis tools
• Experience with compliance and validation (EMI/EMC, safety, regulatory)
• Exposure to global manufacturing environments and supply chain coordination
• Familiarity with PLM systems and change management workflows

We welcome people of different backgrounds and experiences and are committed to building an inclusive work environment that makes Graphcore a great home for everyone. We are an equal opportunity employer and want to build a work environment where everyone is happy, productive and respectful so they can do their best work. If you have a disability or additional need that requires accommodation, just let us know.

Team Description:

The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-machine interface applications. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future. 

Job Responsibilities and Description: 

The Physical Design and Verification Engineer will be responsible for RTL to GDSII Physical Design Implementation, including Synthesis, Placement, Clock Tree Synthesis, Detailed Routing and Optimization, in addition to Physical Signoff Verification. 

Required Qualifications: 

• Bachelor of Science (B.S.) degree in Electrical Engineering and/or Computer Science or a related field, or equivalent experience.
• Minimum 5 years of experience in digital physical design and verification.
• Excellence in complete RTL to GDSII flow with strong experience in the usage of industry-standard Electronic Design Automation (EDA) tools for both physical design and timing signoff.
• Deep knowledge on industry standards and practices in physical design including physically-aware synthesis flow, floor-planning, and place & route, metal fill, chip finishing, signal integrity checks, and dynamic EMIR-Drop analysis, and formal ESD verification.
• Experience in Signoff ECO flow to fix timing, noise, IR-Drop and EMIR violations.
• Experience in physical design verification to debug LVS/DRC/PERC issues at the chip/block level using industry standard tools.
• Experience in developing automation flow and scripts using Python, Perl, Makefile, Tcl and UNIX shell.

Preferred Qualifications: 

• Master of Science (M.S.) degree in Electrical Engineering and/or Computer Science or a related field, or equivalent experience.
• Experience working on physical design and implementation of complex ASIC systems at advanced technology nodes, preferably 16nm and below. 
• Experience in DFT (Design For Test) flows and ATPG.
• Experience in I/O design flow in multi-voltage power domain.
• Experience in building chip floor-plan including pin placement, partitions and power grid.
• Experience in hierarchical synthesis, place-and-route and design closure to meet timing, area, and UPF-driven low power constraints.
• Experience with build tools such as CMake and Bazel.
• Experience with code coverage and regression setup.

Team Description:

Join the Quality Systems Team, where our mission is to ensure compliance with applicable regulatory standards by designing scalable, efficient, and automation-driven systems. We focus on embedding compliance directly into engineering workflows rather than treating it as a manual or reactive function.

We are a team of industry-experienced professionals who apply systems thinking and creative problem-solving to build a durable compliance infrastructure that supports rapid development. Our vision is to establish internal design and quality systems that exceed FDA expectations while enabling fast iteration and deployment of complex, safety-critical software products.

Job Description and Responsibilities:

As a Quality Systems Engineer (dedicated towards Design Controls), your primary responsibility will be to design, implement, and continuously improve software-focused design control systems with regulatory compliance embedded into their architecture.

You will build systems that eliminate ambiguity, reduce manual effort, and enable rapid and reliable development of regulated medical device software. These systems will support the full software lifecycle, from requirements definition through verification, validation, risk management, and release.

You will continuously optimize these systems to improve speed, traceability, and audit readiness while supporting aggressive development timelines and frequent design changes. Your responsibilities include, but are not limited to:

• Design and implement scalable software design controls systems aligned with IEC 62304 and FDA design control requirements (21 CFR 820.30)
• Develop and maintain end-to-end traceability frameworks linking:
• User needs
• Software requirements
• Risk controls
• Design outputs (code, architecture)
• Verification and validation evidence
• Integrate software risk management into design controls, ensuring alignment with ISO 14971 principles
• Build change control mechanisms capable of supporting:
• Rapid iteration
• Parallel development
• Same-day deployment
• Partner closely with software engineering teams to embed:
• Compliance with CI/CD pipelines
• Automated evidence generation
• Controlled release processes
• Own subsets of the Quality System related to software design controls, including but not limited to:
• Software Design Control processes
• Software Risk Management
• Software Change Control
• Software Verification & Validation traceability

Required Qualifications: 

• Bachelor’s degree in Electrical Engineering, Computer Science, or a related technical field
• Demonstrated experience designing or maintaining structured engineering or compliance systems
• Familiarity with software development lifecycles in regulated or safety-critical environments
• Working knowledge of:
• Design Controls
• Software requirements management
• Proficiency in basic scripting, automation, or querying (e.g., Python, SQL, or equivalent)
• Excellent written and verbal communication skills
• Strong problem-solving mindset with the ability to think in systems rather than silos

Preferred Qualifications:

• Familiarity with IEC 62304 (Medical Device Software Lifecycle Processes)
• Familiarity with FDA Design Controls (21 CFR 820.30)
• Familiarity with Design Risk Management (ISO 14971 principles)
• 1–3 years of experience in:
  • Design Controls
  • Software Quality
  • Regulated software development

Team Description:

The Robot Optics Team is seeking Optical Engineers passionate about shaping the future of operating rooms. We are responsible for all optical engineering aspects of Neuralink surgeries, which includes working on our surgical robotics, supporting operating room equipment, and manufacturing custom consumables. The core device we work on is the robotic system that performs implant insertions. Key subsystems include 2D and 3D machine vision cameras, optical coherence tomography, and surgical site illuminators.

Our team oversees the entire product lifecycle of all optical subsystems across multiple robot versions, from ideation and design through production, testing, and maintenance. We also design hardware for producing and inspecting consumables, such as laser-machined needle cartridges. As we manufacture a significant portion of our hardware in-house, our core activities include bring-up testing, designing hardware acceptance testers, and overseeing manufacturing processes. 

Job Description and Responsibilities:

As an Optical Engineer at Neuralink, you will develop custom optics and imaging systems used directly in our surgical robot and associated consumables-manufacturing systems. These systems impact everything from sub-micron conventional imaging and laser scanning imaging to non-imaging optical power delivery. You will have the opportunity to work closely with mechanical, electrical, and software engineers on the Robotics Team and collaborate with neuroscientists and biologists in the rest of the company. You will be responsible for designs from conception through to implementation as well as prototyping and building these optical systems quickly with the rest of the team. Other job responsibilities will include:

• Designing and simulating optical imaging systems
• Testing, verification, and maintenance of robot vision systems
• Designing and developing custom laser interferometry systems and manufacturing systems
• Testing and verification of optics consumables
• Building and testing of beam-scanning instruments
• Developing image acquisition and processing software
• Researching and developing new imaging technologies for robotic surgeries
• Preparing relevant documentation and SOPs for robot optics

Required Qualifications:

• Evidence of exceptional ability in optical engineering or a related field
• Bachelor of Science or higher-level degree in Physics, Optical Engineering, or Mechanical Engineering
• 3+ years of optical engineering experience
• 2+ years of experience simulating and designing optics in Zemax or equivalent software
• Practical experience in designing, testing, and reliability hardening optical systems
• Basic computer skills and proficiency in Google Docs, Google Drive, and Gmail

Preferred Qualifications:

• Experience in designing and testing of in-vivo imaging systems
• Experience in handling high power laser instruments
• Basic understanding in laser interferometry or optical coherence tomography
• Hands-on experience in fabricating, terminating, and splicing optical fibers
• Software engineering experience in developing scripts for instrument testing

Team Description:

The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-computer interfaces. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future.

Job Description and Responsibilities:

We are looking for experienced and hands-on engineers with a creative and initiative mindset, who are interested in exploring the next-generation chip design with advanced architectures and hardware accelerators with a goal of enhancing the energy efficiency, information entropy, and scalability of our wireless brain-computer interfaces towards the physical limit of silicon technology. The ideal candidates are energetic people who get excited about building things, are highly analytical, and enjoy tackling new problems. You will have the opportunity to collaborate closely with chip designers, electrical engineers, algorithms engineers, and software engineers on a small, agile team. As a Digital IC Design Engineer Intern, your responsibilities will include:

• Micro-architecture design and RTL implementation of: 
• Low-power digital signal processors
• Low-power general-purpose hardware accelerators
• Low-power graphics processing units
• Low-power radio MAC/PHY
• Low-power serial link MAC/PHY
• Design and implementation of hardware/software interface with firmware engineers
• Application-specific architecture optimization including:
• Complex system modeling for energy and performance benchmarks
• Workload analysis and modeling
• Leveraging architecture-level design trade-offs with process technology and workload type
• Balancing energy efficiency and performance under manufacturing process variation 
• Complex system-on-chip verification
• Behavioral level modeling and model equivalence check
• FPGA emulation
• Analog mixed-signal co-simulation
• Design for testability 
• Collaboration on silicon bring-up tests with silicon validation engineers 

Required Qualifications:

• Evidence of exceptional ability in electrical engineering, computer science, or computer engineering
• 2+ years of experience in digital design
• Proficient in SystemVerilog, C/C++, Python
• Experience working on complex digital systems from architecture, microarchitecture, and RTL, using industry standard tools
• Experience in designing digital signal processing pipelines, from algorithm to RTL

Preferred Qualifications:

• Experience in architecture optimization with process technology customization
• Experience in the verification of complex digital systems, using industry standard tools
• Experience in the physical design of complex digital systems, using industry standard tools
• Experience testing and debugging digital system-on-a-chips
• Functional modeling experience and logic verification with SystemVerilog, SystemC/C++, or UVM 
• Experience automating tool flows
• Experience with embedded design
• Experience in processor instruction set architecture design
• Experience in compiler back-end design and customization
• Experience designing PCBs or writing firmware.

Expected Compensation:

The anticipated hourly rate for this position is listed below.

California Hourly Flat Rate:
$35/Hr USD

Team Description: 

The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-machine interface applications. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future. 

Job Description & Responsibilities: 

Our Digital IC Design Engineer will be responsible for delivering micro-architecture and register-transfer level (RTL) implementation of digital IPs and systems with a focus in high-throughput low-power digital signal processor (DSP) and general-purpose hardware accelerators towards realizing state-of-the-art brain-computer interfaces. Relevant product development experience in micro-architecture design for low-power processors, on-chip bus and network interfaces, audio/video compression processors, AI/ML accelerators, and communication PHY/MAC will be preferred.

• Micro-architecture design and RTL implementation of: 
• Low-power digital signal processors
• Low-power general-purpose hardware accelerators
• Low-power graphics processing units
• Low-power radio MAC/PHY
• Low-power serial link MAC/PHY
• Design and optimization of hardware/software interface with firmware engineers
• Application-specific architecture optimization including:
• Complex system modeling for energy and performance benchmarks
• Workload analysis and modeling
• Energy/performance profiling and analysis
• Leveraging architecture-level design trade-offs with process technology and workload type
• Balancing cost and performance under manufacturing process variation 
• Collaboration on silicon bring-up tests with verification engineers 

Required Qualifications:

• Bachelor of Science (B.S.) degree in Electrical Engineering and/or Computer Science or a related field, or equivalent experience
• Evidence of exceptional ability in electrical engineering, computer science, or computer engineering
• 5+ years of experience in digital design
• Expertise in SystemVerilog, C/C++, Python
• Experience working on complex digital systems from architecture, microarchitecture, and RTL, using industry standard tools
• Experience in designing digital signal processing pipelines, from algorithm to RTL

Preferred Qualifications: 

• Experience in architecture optimization with process technology customization
• Experience in the verification of complex digital systems, using industry standard tools
• Experience in the physical design of complex digital systems, using industry standard tools
• Experience testing and debugging digital system-on-a-chips
• Functional modeling experience and logic verification with SystemVerilog, SystemC/C++
• Experience automating tool flows
• Experience with embedded design
• Experience in processor instruction set architecture design
• Experience in compiler back-end design and customization

Team Description:

The Robot Software Team builds software that enables scalable neurosurgery that allows safe implantation of the N1 device, ranging from core control, sensors and perception, autonomy, surgery analytics, and more. This role tightly integrates with the robot hardware team, surgery engineering team, as well as the BCI applications team which rely on us to deliver safe and effective implantation of the N1 device. 

Neuralink strives to be a meritocratic environment: we require honest and transparent communication to ensure the best ideas win out, and we believe the best solutions emerge and the best teams are created when you assemble high-performing individuals and allow them to engage in rigorous and thoughtful inquiry. We want to work with exceptional people, and, to the extent that you excel, we want you to take on more responsibility and help all of us succeed. If this speaks to you, come join us.

Job Description and Responsibilities:

As a Software Engineer Intern on the Robot Software Team, you will be responsible for writing software and making sure your code works on an actual surgical robot, not just simulation. Our robotics integrate actuated devices with microelectromechanical systems as well as novel surgical procedures. These applications place strong emphasis on high-precision, high-repeatability mechanical motion, as well as high reliability and fail-safe design. You will be expected to:

• Develop safety-critical software for the robot; you are responsible for contributing directly to surgery-ready software as an intern
• Take ownership of a project that is integral to robot functioning from design to implementation under the guidance of a robot software team member
• Jump on problems when they arise with a strong bias for action to support robot operation by non-software teams
• Work across different engineering disciplines; your software may involve interactions with the mechanical, electrical, biological, and neuroscience teams

Required Qualifications: 

• Evidence of exceptional ability in engineering or computer science
• Experience in writing performant applications in a system language like C, C++, and Rust
• Ability to work on mission-critical and safety-critical systems
• Strong bias for action and first principles thinking

Preferred Qualifications: 

• Hands-on experience with robotics or high-reliability systems
• Experience coding in Linux and debugging on Linux systems
• Experience in computer vision
• Experience in kinematics and motion planning
• Experience working on medical robots
• Experience working in a high-precision environment

Pay Transparency:

Based on California law, the following details are for California individuals only:

California Hourly Rate:

$35/hr USD

Team Description:

The Brain Interfaces Team is responsible for the design, manufacturing, and testing of all systems related to the implant and charger. Our projects involve electrical and mechanical test systems, custom jigs and fixtures, electronics packaging and tooling at the interface between the implant and the surgical robot.

Job Description and Responsibilities:

As our Prototyping Lab Engineer & Manager, you will be instrumental in creating and maintaining an environment that enables our engineering and manufacturing teams to innovate and deliver groundbreaking medical devices. You will go beyond managing equipment and facilities; you will be a key enabler of technical and operational success, ensuring that the R&D lab spaces are designed for efficiency and collaboration. You will play a pivotal role in supporting the company’s growth by facilitating innovation, streamlining operations, and optimizing resource utilization. Additionally, you will be expected to:

• Engineering Lab Design and Operations:
• Design and build lab spaces to meet the evolving needs of the engineering and manufacturing teams
• Continuously improve lab capabilities and operations by implementing new technologies and optimizing space for faster and more efficient workflows
• Own and maintain inventory of all lab equipment, including tools, chemicals, and consumables
• Implement systems for lab organization and cleanliness, and train users accordingly
• Ensure spaces comply with safety regulations and industry standards
• Prototyping and Fabrication:
• Provide hands-on technical support to engineers and technicians by building prototypes, setting up stations and running tests 
• Utilize various fabrication methods, including additive and subtractive manufacturing, to produce high-quality prototype parts.
• Operate and maintain a range of machines and power/hand tools necessary for prototyping
• Manage multiple projects simultaneously, prioritizing tasks to meet tight deadlines and production schedules

Required Qualifications:

• Meticulous attention to detail and exceptional organizational skills
• Eye for aesthetic design and organization
• Familiarity with R&D lab equipment, tools and workflows
• Excellent communication and collaboration skills, with the ability to work effectively with cross-functional teams 
• Thrives in a fast-paced environment where flexibility and innovation are essential
• Hands-on experience with prototyping, model making, fabrication, testing, and lab operations
• Experience planning and building out labs and R&D workspaces

Preferred Qualifications:

• Previous experience in a prototyping environment
• Part design experience
• Experience programming and operating laser cutters, 3D printers, and CNC machines
• Knowledge of regulatory standards relevant to medical device development
• Experience with inventory management systems and quality control processes

Team Description:

The Brain Interfaces Mechanical Engineering team is responsible for the mechanical and manufacturing systems related to our implant, microfabricated thin-film electrodes, wireless charger, and associated accessories. This includes product design, electronics packaging integration, manufacturing line and facility design, test infrastructure design, and related activities for these core products. 

Job Description and Responsibilities:

As a Mechanical Engineer at Neuralink, you will own the design and production of hardware solutions for our brain-computer interface devices. Projects will be highly varied, leveraging both breadth and depth of first principles in mechanical engineering, manufacturing engineering, and test engineering. You will collaborate closely with other engineers (e.g., electrical engineers, chip designers, software engineers, robotics engineers) as well as neuroscientists, neurosurgeons, clinicians, animal care specialists, and other industry experts. You may own a major product from early concept to production, while also diving deep into smaller but essential manufacturing problems to unblock production. Responsibilities will include:

• Exploring early device architectures and downselecting to drive design and company direction
• Scoping projects and requirements, large and small, to hit aggressive project schedules and ensure timely completion from inception to implementation
• Performing market research and gathering feedback from our users (e.g., patients, surgeons, animal care team) to inform product direction
• Detailed designing of 3D CAD and 2D drawings with a heavy focus on DFX, and integration onto the manufacturing line
• Rapid prototyping with existing technologies, and developing or sourcing expanded capabilities
• Identifying key vendors and developing/maintaining relationships to expand our capabilities
• Developing, maintaining, and executing test plans and electro-mechanical test systems for verification and validation of products ranging from components to sub-assemblies, full consumer electronics products, or production environments
• Identifying and tackling manufacturing rate limiters and yield hitters
• Working with data acquisition systems and control systems to continually improve in-test and in-process data recording and system useability
• Providing insight into the design of tooling and equipment from development to full-volume production including poka-yoke, controls, and standardization of componentry
• Developing requirements for, sourcing, and pitching major equipment purchases to expand manufacturing and test capabilities; becoming the subject matter expert for this equipment and training other engineers and technicians
• Developing knowledge of and implementing compliance with relevant federal regulations (e.g., GxP, 21 CFR) as they pertain to medical device design and manufacturing
• Writing and maintaining design and manufacturing documentation for internal reference and submission to regulatory bodies

Required Qualifications: 

• Bachelor’s Degree in Mechanical Engineering or related field, or equivalent experience and ability
• 5+ years of mechanical engineering industry experience, owning products from concept to production 
• Strong grasp of engineering's first principles
• Experience with DFX, conventional machining, rapid prototyping technologies, and precision design + manufacturing 
• Proficiency in CAD (SolidWorks preferred)

Preferred Qualifications: 

• Experience in the design and manufacturing of implantable electromechanical medical devices
• Knowledge of ISO 13485, ISO 10993, 21 CFR, and related standards
• Experience scaling complex low to mid-volume production lines

Team Description:

At Neuralink, we're engineering the future of automated surgeries, focusing on the safe and effective implantation of our groundbreaking Neuralink implant. Our team — a cross-functional mix of roboticists, engineers from various disciplines, and medical professionals — collaborates on developing a surgical flow from first principles. In this critical role, you'll straddle the cutting-edge worlds of robotics, software, and neuroscience.

Job Description and Responsibilities:

This is a new and foundational role for our team that will allow you to create new embedded systems from scratch while challenging and refining the old. As a Firmware Engineer, your responsibilities will encompass:

• Developing and optimizing embedded software for robotic surgery applications
• Streamlining our codebase by refining and, when necessary, retiring legacy embedded software
• Rigorous testing and validation of software systems to meet the highest safety and reliability standards
• Participating in peer code reviews
• Writing drivers and applications to extend the functionality of our robotics
• Specifying hardware and software choices as we develop future hardware platforms
• Sharing your findings and progress with the team in a collaborative environment

Required Qualifications:

• Demonstrated track record of success in a science or engineering field, evidenced by outstanding projects, innovations, or advanced problem-solving
• Proven experience in software development, preferably with exposure to embedded systems

Preferred Qualifications:

Embedded Software Development:

• 2+ years of experience with embedded systems
• Proficient with common communication protocols (SPI, UART, I2C, etc.)
• Comfortable/working knowledge of more advanced protocols such as PCIe, MIPI CSI/DSI, USB, and 802.3
• Proficient in at least one embedded language such as C, C++, or Rust
• Proficient with embedded toolchains and workflow
• Experience building and bringing-up MCUs or FPGAs
• Experience with embedded stacks for ARM cores
• Experience developing on embedded Linux platforms
• Experience with embedded Linux kernel configuration and device tree setup
• Experience with kernel driver development
• Experience with ARM bootloaders
• Experience coding drivers for actuators and sensors
• Experience with high speed data acquisition and processing

Electrical Engineering:

• Foundational understanding of MCU architectures and peripheral integration
• Solid knowledge in electrical engineering and DSP
• Ability to interpret electrical schematics and datasheets, along with proficiency in using lab equipment

Team Description: 

The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-machine interface applications. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future. 

Job Description & Responsibilities: 

Our Hardware/ Software Co-Design Engineer will be responsible for delivering micro-architecture and register-transfer level (RTL) implementation of digital IPs and systems with a focus in high-throughput low-power digital signal processor (DSP) and general-purpose hardware accelerators towards realizing state-of-the-art brain-computer interfaces. Relevant product development experience in micro-architecture design for low-power processors, on-chip bus and network interfaces, audio/video compression processors, AI/ML accelerators, and communication PHY/MAC will be preferred.

• Micro-architecture design and RTL implementation of: 
• Low-power digital signal processors
• Low-power general-purpose hardware accelerators
• Low-power graphics processing units
• Low-power radio MAC/PHY
• Low-power serial link MAC/PHY
• Design and optimization of hardware/software interface with firmware engineers
• Application-specific architecture optimization including:
• Complex system modeling for energy and performance benchmarks
• Workload analysis and modeling
• Energy/performance profiling and analysis
• Leveraging architecture-level design trade-offs with process technology and workload type
• Balancing cost and performance under manufacturing process variation 
• Collaboration on silicon bring-up tests with verification engineers 

Required Qualifications:

• Bachelor of Science (B.S.) degree in Electrical Engineering and/or Computer Science or a related field, or equivalent experience
• Evidence of exceptional ability in electrical engineering, computer science, or computer engineering
• Experience designing and implementing embedded software in C or Rust
• Expertise in SystemVerilog, C/C++, Python
• Experience designing and implementing  emulation models, transactors, and test environments to replicate hardware behavior
• Experience working on complex digital systems from architecture, microarchitecture, and RTL, using industry standard tools
• Experience in designing digital signal processing pipelines, from algorithm to RTL

Preferred Qualifications: 

• Experience in architecture optimization with process technology customization
• Experience in the verification of complex digital systems, using industry standard tools
• Experience in the physical design of complex digital systems, using industry standard tools
• Experience testing and debugging digital system-on-a-chips
• Functional modeling experience and logic verification with SystemVerilog, SystemC/C++
• Experience automating tool flows
• Experience in processor instruction set architecture design
• Experience in compiler back-end design and customization

Team Description:

Join the Quality Systems Team, where our mission is to ensure compliance with applicable regulatory standards by designing scalable, efficient, and automation-driven systems. We focus on embedding compliance directly into engineering workflows rather than treating it as a manual or reactive function.

We are a team of industry-experienced professionals who apply systems thinking and creative problem-solving to build a durable compliance infrastructure that supports rapid development. Our vision is to establish internal design and quality systems that exceed FDA expectations while enabling fast iteration and deployment of complex, safety-critical software products.

Job Description and Responsibilities:

Please note, this is a duplicate posting for the "Quality Systems Engineer" role. We are testing titling to see which attracts the most qualified candidates. Please only apply to one of the postings. 

As a Design Controls Engineer, your primary responsibility will be to design, implement, and continuously improve software-focused design control systems with regulatory compliance embedded into their architecture.

You will build systems that eliminate ambiguity, reduce manual effort, and enable rapid and reliable development of regulated medical device software. These systems will support the full software lifecycle, from requirements definition through verification, validation, risk management, and release.

You will continuously optimize these systems to improve speed, traceability, and audit readiness while supporting aggressive development timelines and frequent design changes. Your responsibilities include, but are not limited to:

• Design and implement scalable software design controls systems aligned with IEC 62304 and FDA design control requirements (21 CFR 820.30)
• Develop and maintain end-to-end traceability frameworks linking:
• User needs
• Software requirements
• Risk controls
• Design outputs (code, architecture)
• Verification and validation evidence
• Integrate software risk management into design controls, ensuring alignment with ISO 14971 principles
• Build change control mechanisms capable of supporting:
• Rapid iteration
• Parallel development
• Same-day deployment
• Partner closely with software engineering teams to embed:
• Compliance with CI/CD pipelines
• Automated evidence generation
• Controlled release processes
• Own subsets of the Quality System related to software design controls, including but not limited to:
• Software Design Control processes
• Software Risk Management
• Software Change Control
• Software Verification & Validation traceability

Required Qualifications: 

• Bachelor’s degree in Electrical Engineering, Computer Science, or a related technical field
• Demonstrated experience designing or maintaining structured engineering or compliance systems
• Familiarity with software development lifecycles in regulated or safety-critical environments
• Working knowledge of:
• Design Controls
• Software requirements management
• Proficiency in basic scripting, automation, or querying (e.g., Python, SQL, or equivalent)
• Excellent written and verbal communication skills
• Strong problem-solving mindset with the ability to think in systems rather than silos

Preferred Qualifications:

• Familiarity with IEC 62304 (Medical Device Software Lifecycle Processes)
• Familiarity with FDA Design Controls (21 CFR 820.30)
• Familiarity with Design Risk Management (ISO 14971 principles)
• 1–3 years of experience in:
  • Design Controls
  • Software Quality
  • Regulated software development

Team Description:

The Surgery & Robotics Hardware Team is looking for Electrical Engineers who want to advance the future of healthcare solutions with technology. At Neuralink we recognize that increasing healthcare costs, lack of access, and insufficient numbers of neurosurgeons globally require new approaches to enable greater access to our devices. To address these challenges we design fully autonomous robotics systems, human assistive surgical tools, and design entire surgical suites in order to provide better experiences for our customers.

Our team works on our surgical robot system which aims to fully automate the implantation of the Neuralink implant. We design and integrate multi-axis robotic arms, perception systems including custom imaging hardware, optical coherence tomography tissue imaging, power electronics, and safety systems such as 3D spatial mapping/object avoidance sensors. Robotics is part of a larger system of tools we work on. For example, using pre-op MRI scans we generate patient anatomy data that we later use in surgery to register precise surgery site locations. 

In addition to research and development of modern surgical technology, we also are responsible for bringing these technologies to market. We perform full lifecycle testing for all devices we design and ultimately manufacture them for use in human surgeries. To date, our designs have served over 20 individuals, and in the coming years our designs will serve thousands of individuals who wish to use our implant technology.

Job Description and Responsibilities:

As an Electrical Engineer on the Surgery & Robot Hardware Team, you will be expected to design, verify, and oversee the transition to production of a variety of custom electronics systems.  This role offers substantial autonomy and the exciting opportunity to own creative decisions and execute on new, impactful projects such as robotics stage designs, motor drives and controls, custom camera designs, manufacturing automation, and the firmware that enables all of these devices.

Required Qualifications: 

• Bachelor’s degree in Electrical Engineering or a related field or equivalent experience
• Professional experience delivering on all phases of electronics design (requirements, part selection, schematic, layout, manufacturing, test)
• Demonstrated depth in at least one of the following:
  • Power electronics: experience designing custom power conversion, distribution, eFusing, and battery management systems in the low-to-medium (1W-2kW) range
  • FPGA hardware design for time sensitive systems such as image processing, high-speed data acquisition, or real time networking. Professional experience in FPGA selection, RTL development, digital signal processing theory and techniques, and hardware design to interface high speed physical layer devices via PCIe, MIPI, SLVS-ec, LVDS, etc
  • Manufacturing automation design: professional experience architecting and implementing manufacturing automation solutions for products that currently ship at the scale of 1000’s+
• Practical electronics design knowledge including designing for EMC, ESD, thermals and packaging

Preferred Qualifications: 

• A portfolio showcasing your hardware designs 
• Demonstrable experience developing electronics for safety critical systems such as medical devices, aerospace, automotive, or military
• Demonstrable experience shipping code in one of the following languages: C, C++, Python, or Rust
• Altium experience

Team Description:

The Robot Reliability and Test Team is directly responsible for ensuring the surgical robot and its subassemblies are rigorously tested during both the design and production cycles. The team designs testing infrastructure, writes and provides guidance on test descriptions and outputs, and ensures the surgical robot is reliable and ready for use in human surgeries. Providing safe, effective, and smooth surgical procedures allows Neuralink to move at a rapid pace and reach more individuals who need this life-changing technology.

Job Description and Responsibilities:

As a Test Engineer, you’ll be responsible for transforming our surgical robot from an experimental medical device to a robust system capable of doing tens of thousands of surgeries. We’re looking for engineers with experience designing complex hardware systems, developing tests and fixtures to validate hardware, or debugging complex systems (or all three!). You will identify and resolve key reliability issues while designing and implementing test infrastructure to enhance the robot's engineering development and validation as well as the reliability of both the robot and its associated surgical tools. Furthermore, you will be expected to:

• Drive resolution and preventative actions for non-conforming robots
• Provide guidance on design controls and transfer processes
• Analyze data trends and debug hardware & software failures
• Define maintenance and calibration schedules

If you’re excited about solving new problems every day, or if you are passionate about test and fixture design, we would love to hear from you!

Required Qualifications:

• Bachelor’s Degree in mechanical/electrical engineering, or equivalent in experience and ability
• 1+ years of engineering experience in testing and making systems reliable (whether that's in school clubs or industry)
• Strong understanding of engineering first principles

Preferred Qualifications:

• Experience designing hardware in the loop test systems
• Proficiency interfacing with sensors, motors, etc.
• Coding experience in Python

Team Description:

Join the Brain Interfaces Embedded Systems Team and be part of an elite team of engineers working on high-performance, safety-critical embedded systems for the next-generation brain-computer interfaces. You will have the opportunity to work closely with chip designers, electrical engineers, and software engineers on a small, fast-moving team.

Job Description and Responsibilities: 

We are looking for experienced, hands-on engineers who are interested in exploring what's possible in highly powered and latency-constrained environments. Firmware is the kernel of operation for the implant, and you have the chance to define and implement features that have a significant impact on the product’s capabilities. As an Embedded Software Engineer, you will be expected to:

• Own complex challenges from definition to solution
• Utilize your ability to work cross functionally to deliver safety critical systems while considering power, radio, and thermal requirements
• Take ownership of products and/or core features; from planning and design to execution and testing
• Build on your fundamental understanding of hardware while contributing to bare-metal firmware
• Embrace a fast-paced iterative environment that prioritizes shipping manufacturable solutions 

Note: The team is hiring embedded engineers at all levels, both junior and senior. What matters most is evidence of exceptional abilities and a drive to succeed.

Required Qualifications: 

• Bachelor’s degree in computer science, electrical engineering, related field, or equivalent experience 
• 1+ years of experience with embedded systems (including internships)
• Proficient in embedded C or Rust
• Ability to design bare-metal embedded systems in highly constrained environments
• Strong Electrical Engineering fundamentals 
• Signal processing fundamentals 
• You find enormous challenges exciting and enjoy discovering and defining problems as much as solving them
• You deliver. You may enjoy thoughtful conversations about problems and perfecting design, but in the end, you know that delivering reliable manufacturable solutions matters
• You are a cross-disciplinary team member. You are excited to work with and learn from chip designers to neuroscientists

Preferred Qualifications: 

• Experience with embedded stacks for ARM cores
• Experience with safety-critical systems
• Experience with FPGA development and testing
• Experience with RF, BLE, TCP/IP stacks from a practical embedded perspective
• Prior work or experience with applied cryptography and embedded systems security

Team Description:

The Data Engineering Team works closely with other teams—neuroscientists, physicists, roboticists, chip designers, pathologists, and mechanical engineers—to build Neuralink’s centralized data aggregation and analysis platform. This data platform collects, organizes, and visualizes a diverse set of data ranging from neural signal recordings and brain histology images to microfabrication manufacturing data. Our team owns projects that drive engineering and experimentation at Neuralink.

We operate like an internal startup – rapidly prototyping and building software that solves problems for the company. If you are obsessed with smooth user experience and love to iterate rapidly on software, you may be a good fit for this role!

 See a talk on our data platform, Neuralake, below:

Job Description and Responsibilities:

As a Software Engineer on the Data Engineering Team, you will have the opportunity to impact engineering and experimentation at Neuralink. You will fully own and drive projects, from interfacing with stakeholders and gathering requirements, to delivering exceptional software. Our ideal candidate has accomplished a record of outstanding achievement in software engineering. Additionally, you will be expected to:

• Build end-to-end data systems to facilitate the easy querying of data
• Build and maintain low-latency pipelines and batch data processing jobs
• Create easy-to-use dashboarding platforms for internal data sharing
• Work directly and iteratively with stakeholders to grow MVPs into mature solutions
• Own the design, development, and testing of software development projects
• Deliver results. You may enjoy thoughtful conversations about problems and perfecting designs, but in the end, you know that what matters is delivering a solution that works
• Be a cross-disciplinary team member. You are excited to work with and learn from software, mechanical, electrical, materials, and biological engineers, as well as neuroscientists. You are comfortable communicating across teams.
• Be resourceful, flexible, and adaptable; no task is too big or too small

Jobs at Neuralink are highly dynamic; depending on your skills and our needs, you may work across a wide range of projects, from interpreting neural data to analyzing histology, developing surgical tools, or creating brand-new BCI approaches. Successful candidates will be highly adaptable, able to deploy core technical and creative skills to tackle a wide range of problems, and have a keen sense of urgency.

Required Qualifications: 

• Most important: Demonstrated leadership in delivering a product or feature, either as a team leader or key contributor
• Evidence of exceptional ability in software engineering
• A bachelor’s degree in Computer Science or equivalent demonstrated work experience
• 1-2 years of experience leading teams and owning the success of a product
• Excellent written and verbal communication skills
• Experience understanding requirements and delivering in an interactive manner
• Experience understanding requirements and delivering iteratively

Preferred Qualifications:

• Experience with building data platforms
• Experience with Python and Rust
• Experience with data analytics systems such as Clickhouse, Delta Lake, Apache Spark, Hadoop, or Snowflake

Note: You do not need to have any of these preferred qualifications in order to be considered for this role! Any exceptional software engineer is encouraged to apply.

Team Description:

Join the Brain Interfaces Software Team and be part of a team of remarkable and driven engineers accelerating our pathway to human ready brain-computer interfaces. We are a small, but fast-moving team that collaborates with other exceptional teams of mechanical, electrical, and firmware engineers.

Neuralink strives to be, as much as possible, a meritocratic environment: we require honest and transparent communication to ensure the best ideas win out, and we believe the best solutions emerge and the best teams are created when you assemble high-performing individuals and allow them to engage in rigorous and thoughtful inquiry. We want to work with exceptional people, and, to the extent that you excel, we want you to take on more responsibility and help all of us succeed. If this speaks to you, come join us.

Job Description & Responsibilities:

We are looking for a versatile Software Engineer who is passionate about architecting and implementing elegant software solutions and thrives with autonomy to propose creative approaches to problems. You will be responsible for writing software to interact with Neuralink’s implant, as well as building systems for manufacturing and testing the device. Additionally, you will be expected to:

• Develop and improve Neuralink’s implant manufacturing line acceptance software and station
• Develop and improve Neuralink's implant design verification testing software
• Optimize and maintain Neuralink’s implant software build infrastructure
• Develop and improve Neuralink’s implant SDK

Required Qualifications:

• Fluent in Python and at least one system language including Rust, C++, and C (don’t get hung up on this—being an exceptional software engineer matters above all)
• Experience and proficiency with Linux/Unix systems
• Evidence of exceptional ability in engineering, mathematics, or computer science
• Solid understanding of engineering first principles
• Strong intuition for what matters in a production system vs. research-grade environments

Additional Requirements and Competencies:

• You find large challenges exciting and enjoy discovering and defining problems as much as solving them
• You deliver; you may enjoy thoughtful conversations about problems and perfecting design, but in the end, you know that what matters is delivering reliable solutions (Our ultimate aim is to help people; the “right” solution doesn’t always achieve that)
• You are mission-driven and goal-oriented in your approach to solving problems
• You feel a sense of urgency to get things done sooner rather than later—because there is so much we, as people, can contribute to the world and accomplish in this life, it’s a shame to waste time
• You are resourceful, flexible, and adaptable; no task is too big or too small

Team Description:

We build the electrical systems that make high-bandwidth brain–computer interfaces possible. This includes neural signal acquisition and stimulation to wireless power delivery, embedded processing, and system integration—all within devices small enough to be implanted in the human body and efficient enough to operate under strict thermal and power constraints. Our work sits at the intersection of analog, RF, digital, and biological systems. Many problems in this space do not present clean abstractions or clear failure modes. Success often depends on careful measurement, iteration, and engineering judgment across multiple interacting systems.

Job Responsibilities:

• Utilize electrical engineering fundamentals and best system design practices to deliver high-performant, reliable, and manufacturable extremely size-constraint systems
• Contribute to all phases of system and board design, from system definition to part selection, schematic design, layout, bring up, and design verification
• Help conduct R&D investigations and experiments to demonstrate feasibility of new technology for the implant and the charger
• Work cross functionally to ensure successful systems integration
• Contribute to system improvements that decrease latency and increase battery life, reliability, and safety
• Design and deploy systems for implant-charger hardware in the loop testing, and manufacturing line quality control

Note: The team is hiring electrical engineers at all levels, both junior and senior. What matters most is evidence of exceptional abilities and a drive to succeed.

Required Qualifications:

• Bachelor’s degree in Electrical Engineering or equivalent experience
• Strong electrical engineering and physics fundamentals, with demonstrated ability to apply them under real-world constraints (noise, power, size, non-ideal interfaces)
• Proven ability to independently design, bring up, debug, and verify complex PCBAs operating under tight power and size constraints, including mixed-signal circuits, sensitive sensor interfaces, and embedded compute
• Experience debugging systems where issues span multiple domains (analog, digital, RF, power) and root causes are not immediately obvious
• Deep familiarity with lab instrumentation (oscilloscopes, power supplies, spectrum analyzers, VNAs) and the ability to extract meaningful insight from imperfect measurements

Preferred Qualifications:

• Experience shipping highly integrated, size- and power-constrained devices (e.g., wearables, implantables, compact wireless systems)
• Experience with wireless systems and RF design tradeoffs (BLE, Wi-Fi, antenna design, coexistence)
• Experience supporting hardware through manufacturing at scale, including yield, test, and failure analysis
• Experience in safety-critical or regulated environments, where reliability and risk must be explicitly managed
• Familiarity with mechanical integration constraints (CAD tools, packaging, stack-ups)
• Experience with electromagnetic simulation and antenna validation (FEM/FDTD or equivalent)

Team Description:

We build the electrical systems that make high-bandwidth brain–computer interfaces possible. This includes neural signal acquisition and stimulation to wireless power delivery, embedded processing, and system integration—all within devices small enough to be implanted in the human body and efficient enough to operate under strict thermal and power constraints. Our work sits at the intersection of analog, RF, digital, and biological systems. Many problems in this space do not present clean abstractions or clear failure modes. Success often depends on careful measurement, iteration, and engineering judgment across multiple interacting systems.

Job Description and Responsibilities:

We are looking for an experienced, hands-on electrical engineer for implant electronics board design, integration with our custom chips, testing, and quality control. You will have the opportunity to contribute to advanced projects, not only work on incremental changes, and be an integral member of a small, fast-moving team. You will be working on all phases of board design (part selection, schematic design, layout, and bring-up) as well as collaborating closely with chip designers, firmware engineers, mechanical engineers, and microfabrication experts for system integration.

• Utilize electrical engineering fundamentals and best system design practices to build on your ability to deliver high-performant, reliable, and manufacturable extremely size-constraint systems
• Gain understanding of all phases of system and board design, from system definition to part selection, schematic design, layout, bring up, and design verification
• Contribute to R&D investigations and experiments to demonstrate feasibility of new technology for the implant and the charger
• Gain experience working cross functionally to ensure successful systems integration
• Contribute to system improvements that decrease latency and increase battery life, reliability, and safety
• Develop ability to design and deploy systems for implant-charger hardware in the loop testing, and manufacturing line quality control

Required Qualifications: 

• Strong EE fundamentals
• Experience designing PCBs for low power and size constrained applications
• Experience with PCB CAD tools (Altium, Eagle, KiCad, Allegro)
• Experience with sensors, power management, and signal/power integrity
• Comfortable with common communication protocols (SPI, UART, I2C, etc.)
• Comfortable with lab equipment (oscilloscope, VNA, etc.)
• Basic C and Python programming skills

Preferred Qualifications:

• Experience with firmware development for embedded systems (C/C++)
• Experience with wireless systems (BLE, WIFI, Zigbee)
• Experience building and bringing-up MCUs or FPGA
• Proficiency with ME CAD tools (Solidworks, AutoCAD)
• Experience with analog circuit design

Expected Compensation:

The anticipated hourly rate for this position is listed below.

California Hourly Flat Rate:
$35/Hr USD

Job Summary

We are seeking a talented Signal Processing Engineer to design, develop, and optimize advanced digital signal processing (DSP) algorithms for on-chip and embedded implementation. In this role, you will create efficient, hardware-friendly algorithms that run directly on custom SoCs, enabling real-time processing with constraints on power, latency, area, and throughput. You will collaborate closely with the SoC, Firmware, and Machine Learning teams to translate high-level signal processing needs into production-ready solutions.

Key Responsibilities

• Design and develop signal processing algorithms for sensing neural activity in the cortex (e.g. spike detection), monitoring cortical electrode health, and more.
• Design and develop numerical algorithms, such as custom data compression to increase radio throughput.
• Develop fixed-point or quantized versions of algorithms optimized for constrained hardware.
• Implement and verify algorithms in high-level languages and transition them to hardware-friendly representations.
• Perform algorithm-to-architecture mapping: analyze trade-offs between accuracy, latency, power, and resource utilization on the SoCs.
• Collaborate with the digital design team to define micro-architectures for custom on-chip processing pipelines, including dataflow, pipelining, and parallelization.

Required Qualifications

• Education: BS, MS or PhD in Electrical Engineering, Computer Engineering, Signal Processing, or a related field.
• Experience: 3+ years in digital signal processing algorithm development or real-world products, with a focus on embedded or hardware-constrained implementations.
• Fluent in signal processing fundamentals (both analog and digital) and strong numerical capabilities.
• Familiarity with fixed-point arithmetic, quantization effects, and numerical precision trade-offs.
• Proficiency in Python and C for algorithm prototyping and simulation.

Preferred Qualifications

• Hands-on experience with Verilog/VHDL, or transitioning algorithms to RTL.
• Experience with dedicated DSP cores or accelerators.
• Track record of optimizing for power/area/latency in resource-constrained environments.

Base Salary Range:

 $121,000 - $230,500

Team Description:

Designing and building facilities and infrastructure is key to enabling Neuralink to scale. The EPC team is responsible for all aspects of engineering, procurement, and construction ranging from greenfield site developments to tenant improvements of our existing facilities. We regularly interface with cross-functional teams to identify their short- and long-term needs, plan, and deliver purpose-built spaces.This position requires an outgoing and highly organized mindset, an ability to perform at a high level on a consistent basis, a desire to work on multi-disciplinary projects, and an excitement to work at Neuralink!

Job Description and Responsibilities:

As part of the construction team, an EPC Engineer is responsible for ensuring that the output of Neuralink construction projects meets the technical requirements and specifications created during design development. When a challenge arises during construction, an EPC Engineer is expected to identify the roadblock, determine potential solutions, assemble stakeholders, and ensure that the solution is implemented as per design specifications or create a design that can be used to implement a solution. An EPC Engineer:

• Leads: 
• Inspections and quality control during construction
• Contractor scheduling to ensure projects meet deadlines
• Responding to or sourcing responses for RFIs related to constructability or deviations from construction drawings or manufacturer specifications
• Negotiating and managing contracts with vendors, contractors, consultants, and other third parties as needed
• Preparing purchase orders while following appropriate pricing and scope evaluations
• Reviewing and approving invoices for contractors and materials Neuralink sources
• Is a contributor to:
• Attending regular meetings between trades on site, and between contractors and the internal EPC team, in order to address technical construction questions
• Collaborating with architects, engineers, contractors, and other stakeholders to deliver constructable plansets
• Vetting and selecting contractors
• Understanding and implementing the processes of end users to ensure that their design intent is met in new construction or tenant improvements
• Generates:
• Construction review meetings and reports with internal stakeholders at major milestones during construction
• Quality control reviews and reports to document the quality of constructed items
• RFIs and Submittals for the design team to review and approve during construction projects

Required Qualifications:

• Bachelor’s degree in civil, mechanical, architectural or similar engineering discipline
• 3+ years of relevant experience

Preferred Qualifications:

• Experience in site civil design including grading, roadway, pavements, utilities, stormwater management plans (flood control and stormwater quality), erosion and sediment control plans, project sites with multi-users and modes of transportation, and industrial construction and operations
• Experience commissioning and startup of Mechanical and Electrical Equipment
• Has passed the FE exam or has the ability to pass it within 6 months of starting
• Experience with structural engineering, deep and shallow foundation designs, steel, concrete, and other building materials is preferred
• Experience managing external consultants and contractors through full scopes

Team Description:

As part of the Surgery & Robot Hardware Department, the Surgical Consumables Team is responsible for producing a wide range of critical mechanical devices that enable our life-changing surgical procedures. Balancing immediate needs with long-term scalability, we drive innovation with precisely engineered tools that ensure safety, reliability, and high-quality surgical execution.

Job Description and Responsibilities:

We’re looking for a Manufacturing Engineer to help scale the manufacturing of consumables used in our robotic surgeries. These consumables include the Needle Cartridge (the end effector that inserts electrodes into the cortex) as well as other complex mechanical assemblies and surgical proxies, like the one being assembled here.

In this role, you will help expand our team’s capabilities by supporting the build-out of a new manufacturing site in Texas while sustaining production at existing sites. You’ll work hands-on to troubleshoot manufacturing issues, analyze data, improve processes, and design fixtures. You will collaborate closely with hardware designers, machinists, quality engineers, and the surgery team to ensure parts are built correctly, released on time, and delivered where they’re needed. 

You will contribute to technical solutions for complex manufacturing problems and help design processes that scale as production ramps. This role is well suited to someone who enjoys working closely with hardware, learning how products move from development to production, and operating in a fast-paced environment. The Manufacturing Engineer will:

• Support day-to-day production to meet consumables demand across the company
• Provide manufacturability input as products move into more mature lifecycle stages
• Design, test, and implement production fixtures, tooling, workstations, and assembly aids
• Troubleshoot manufacturing issues, perform root cause analysis, and implement corrective actions
• Support quality control activities in compliance with Design Control requirements, cGMP, FDA regulations, and internal policies
• Generate and maintain manufacturing documentation, including work instructions, Device Master Records (DMRs), and Design History Files (DHFs)
• Conduct risk assessments and support mitigation efforts to ensure product safety and reliability
• Drive continuous improvement efforts focused on yield, throughput, and process robustness

Required Qualifications:

• Strong interest in manufacturing small, safety-critical assemblies where precision and quality are paramount
• Bachelor’s degree in Mechanical Engineering, Electrical Engineering, Industrial Engineering, Biomedical Engineering, or a related field, or equivalent experience
• 1+ year of experience in manufacturing engineering or engineering design
• Experience in Solidworks (preferred), OnShape, Creo, or an equivalent CAD program
• Demonstrated ability to execute on hardware-focused projects
• Hands-on experience physically building hardware (machining, fabrication, soldering, assembly, prototyping, etc.); personal projects are a plus
• A genuine interest in manufacturing and passion for learning

Preferred Qualifications:

• Experience working in a manufacturing environment
• Familiarity with ISO 13485, FDA 21 CFR Part 820, or other regulated manufacturing standards
  
  

Additional Requirements and Competencies:

• This role will initially require frequent travel to Fremont, CA, which is expected to decrease over time

A new paradigm of computing

Magic Leap is a pioneer in Augmented Reality (AR) optics, display systems, platforms, devices services, prototyping and manufacturing capabilities. We are known for our unmatched optics stack and have developed ultra-lightweight waveguides and display systems that advance what is possible in AR. With more than a decade of experience in AR innovation, we have made groundbreaking advancements in text legibility, color fidelity and rich digital content visuals while continually expanding the field of view to create engaging, immersive AR experiences. 

Magic Leap could be your place if you want to be part of a united team where everyone is empowered and trusted to make an impact. At Magic Leap, you can explore innovative solutions and use your talents to solve real-world problems. Working alongside industry experts, you can grow your skills while helping make our technology available to millions of people as a partner in the AR ecosystem.  We know that successful change and progress accelerate diverse perspectives. As we shape our future, everyone's voice matters. Together, we can reimagine the world of work and, with our bold partners, make the impossible possible.

The opportunity 

We are seeking an experienced, hands-on Senior Manager, Metrology & Optical Test expert to lead a focused group of engineers in our waveguide manufacturing team. This leadership role involves overseeing all aspects of measurement, calibration, and instrumentation, including nanostructure characterization and optical performance testing for outgoing products. Responsibility spans across the organization, ensuring the highest standards of accuracy and compliance are maintained to deliver on customer requirements. The ideal candidate will be a leader and player/coach with a deep technical understanding of metrology and optical test principles, quality systems, and advanced measurement equipment. This role is integral to advancing our Optics NPI and Manufacturing practices and will work closely with cross-functional design, process, materials, and integration teams.

Location: This role will be based fully onsite in Austin, TX. Relocation assistance is available for non-local candidates.

What you’ll do 

• Strategy and Leadership:
  • Develop and implement the Optical NPI and Manufacturing metrology strategy, ensuring alignment with overall business objectives and quality standards.
  • Lead a small team of metrology and optics professionals, defining actionable goals, developing their professional growth, while fostering a culture of continuous improvement.
  • Lead and develop best practices for problem solving (8D, 5 Whys, Fishbone, etc.) and technical communication. 
  • Seamless integration of workflows across R&D, Manufacturing, NPI, and Materials team to deliver solutions to support manufacturing operations activities from early NPI through High Volume ramp.
  • Ownership of delivering clear, concise technical documentation and presentations, and building effective partnerships across teams and with external suppliers.
• Measurement and Optical Test Tools:
  • Oversee the maintenance, calibration, and verification of all measurement and test equipment (M&TE) to maintain traceability and compliance with national and international standards (e.g., ISO/IEC 17025, ISO 9001).
  • Establish and enforce standard operating procedures (SOPs) for all metrology and optical test processes, including measurement uncertainty analysis, gauge R&R studies, and calibration schedules.
  • Define, develop, budget, and qualify advanced testing/characterization techniques to deepen the fundamental understanding of waveguide materials, processes, and their impact on device performance. This includes recipe/configuration setups, statistical validation such as GR&R and matching studies, calibrated standards, golden unit creation,  long-term stability (LTS), and factory and site acceptance testing for new equipment.
• Technical Expertise and Support:
  • Serve as the primary subject matter expert (SME) for all complex dimensional, mechanical, and electrical measurement challenges, providing technical guidance to cross-functional teams (e.g., R&D, Manufacturing, Quality).
  • Apply expertise in metrology, characterization, optics, and nanofabrication to support imprint and replication processes, wafer cleaning, plasma etch, chemical vapor deposition (CVD), and metals deposition.
  • Establish project priorities and manage resources, ensuring efficient workflow across metrology (AFM, ellipsometry, interferometry, and other characterization equipment) and waveguide optical testers (for KPIs such as ANSI, MTF, Transmission, etc).
  • Analyze Interpret data from metrology equipment, including identification of potential measurement errors, tool variance, and tester to tester correlations. 
• Operations and Compliance:
  • Manage the departmental budget, including definition of capital equipment requirements and resource allocation.
  • Drive the selection, procurement, and implementation of new metrology and optical test technologies and software to enhance measurement capabilities and efficiency.
  • Act as the representative for all external audits related to metrology and optical test solutions.
  • Collaborate with the Quality department to ensure metrology practices support the company's Quality Management System (QMS).

The experience you bring

• Bachelor’s or Master’s degree in Engineering, Physics, or a related technical field. 
• Minimum of 8 years of progressive experience in metrology, quality control, optical test, or precision manufacturing, with at least 3 years in a management or leadership role. Minimum 7 years of hands-on experience in advanced materials characterization techniques.
• Technical Expertise:
  • In-depth knowledge of geometric dimensioning and tolerancing (GD&T) per ASME Y14.5.
  • Demonstrated expertise in measurement uncertainty budgets and calculations, sensitivity analysis, and variance analysis.
  • A strong statistical background and experience in large data set analysis using industry standard tools (e.g., JMP, R, Python, Matlab).
  • Proficiency with various measurement systems, including CMMs, optical scanners, vision systems, and conventional gauges.
  • Hands-on experience with materials and nanostructure characterization methods, including SEM, AFM, ellipsometry, interferometry, XRD, EDX, uXRF, FTIR, DSC, and TGA.
• Standards Knowledge: Strong working knowledge of relevant international quality and metrology standards (e.g., ISO 9001, ISO/IEC 17025). Knowledge of statistical methods (MSA/GRR) and process improvement techniques.  
• Work Environment: 
  • Must be comfortable working in a cleanroom laboratory environment, adhering to all safety and contamination control protocols.
  • Demonstrated ability to perform effectively in fast-paced environments and under tight deadlines.

It’s exciting if you also have

• Ph.D. in Materials Science, Engineering, Chemistry, Chemical Engineering, Applied Physics, or a closely related discipline is highly desirable.
• Certification as a Certified Quality Engineer (CQE) or Certified Metrology Manager.
• Experience in a regulated industry (e.g., aerospace, medical devices, automotive, semiconductor, or AR hardware development).
• Six Sigma Greenbelt or equivalent experience.
• Demonstrated experience implementing laboratory information management systems (LIMS) or similar calibration management software and manufacturing systems integration.
• Experience in custom scripting for data post-processing (e.g., JMP, R, Python, Matlab).

Additional Information

All your information will be kept confidential according to Equal Employment Opportunities guidelines.

Please note that we do not accept any application documents via (e-)mail. Furthermore, we do not accept applications from recruitment agencies for this role.

All legitimate Magic Leap email communications will end with "@magicleap.com". Please carefully review all emails you receive, to ensure you only engage with legitimate representatives of Magic Leap. For the protection of your Personal Information, do not click any links, open any attachments, or further engage with any suspicious communications. In the event you receive an unexpected or suspicious communication claiming to come from Magic Leap, please reach out directly to TalentAcquisition@magicleap.com for assistance.

Accommodations

If you need an accommodation during the application, interviewing, or hiring process, you may request an accommodation by emailing ApplicantAccommodation@magicleap.com. Magic Leap will reasonably accommodate qualified individuals with disabilities to the extent required by applicable law.

#LI-SM2

#LI-ONSITE

We are thrilled to announce an opportunity for a Field Superintendent to join our team and support the construction of some of the most challenging and exciting projects in the Southwest. This includes innovative and impactful work in commercial, industrial, mission-critical, and water/wastewater treatment facilities. If you are passionate about leading dynamic teams and driving excellence in construction, we want to hear from you!

Responsibilities 

• Emphasizes a culture of exceptional safety and best-in-class quality to all foremen and craft, including associated trade partners. 
• Responsible for supporting and developing Foremen, including fostering a positive environment for our craft and trade partners to prosper. 
• Provides guidance and support to the Field Engineer regarding survey and layout needs, including providing a schedule as to when such work is required. 
• Assists the Project Superintendent with project schedule development and maintenance, including pull plans, look-ahead schedules, and implementation of the Last Planner System 
• Prepares work plans for critical work and facilitates detailed reviews of such plans with the Field Engineer and Foreman 
• Understands budgeted values for labor, equipment, and consumables; responsible for collaboratively planning work with the Foremen to be commercially successful. 
• Responsible for ensuring efficient crew sizing and makeup is always present and adjusting when necessary. 
• Ensures Foremen are promptly and accurately completing all necessary reports and documentation for their crews (timesheets, daily reports, safety/quality forms, employee evals etc.) 
• Leads coordination and Support for all QC processes for their specific scope or assigned project. 
• Actively participates in daily and weekly project meetings. 
• Promptly reports field issues to the Field Engineer and Project Superintendent 
• Assists this Field Engineer with the development of lift drawings. 
• Develops rapport with owners, clients, engineers, and trade partners while ensuring contractual compliance with all parties. 
• Planning and safe execution of Hazardous energy control, T&E, Working at Heights, and confined space. 

Qualifications   

• Working knowledge of all aspects of construction and industry practices, processes, standards, and their impact on project activities 
• Ability to multi-task, collaborate with others, set priorities, and take initiative. 
• Demonstrated success supporting a team through complex project execution. 
• Experience leading project teams and holding them accountable to project goals. 
• Excellent organizational, verbal, written, presentation skills are a must. 
• Proficiency with Microsoft Office Suite (Outlook, Word, Excel, PowerPoint, etc.) 
• STSC trained. 
• Proficiency with Primavera P6 scheduling software a huge plus. 
• Positive and teachable attitude. 
• Possesses excellent organizational, verbal, written and presentation skills. 

Education & Certifications 

• OSHA 30 Certification 

Safety Level
This is a safety sensitive position, and all applicable policies including drug test and background check will apply.

• The inherent responsibilities of your role may include physical working conditions. In order to safely and successfully perform job duties you must be able to:  
• Potentially lift up to 50 pounds 
• Potentially need to do repeated pushing, pulling, carrying, reaching (or working above shoulder), walking, standing, sitting, stooping, kneeling, bending, and climbing  
• Potentially operate a motor vehicle, crane, tractor, etc.  
• We reserve the right to continually monitor your ability to safely and successfully complete these inherent physical responsibilities and take action as deemed appropriate in accordance to the Americans with Disability Act (ADA)

 #CORBIND1

ICON is looking for a Senior Robotics Software Engineer to join our Software team in Austin, TX. As a Senior Robotics Software Engineer, you will help develop and maintain robotic control software for all of ICON’s robotic systems. You will be responsible for developing high-performance C++ software to drive complex arm motions, integrating real-time sensor data, and ensuring reliable motion planning. This role is based at ICON’s Austin, TX headquarters, and will report to the Director of Embedded Software Engineering.

RESPONSIBILITIES

• Design, develop, and optimize high-performance C++ software for controlling and coordinating large-scale robotic arms.
• Develop robust motion planning and trajectory generation algorithms to safely navigate industrial arms through complex workspaces.
• Implement real-time sensor fusion and state estimation algorithms (using sensors like IMUs, LiDAR, etc.) to improve arm localization and end-effector precision.
• Program robotic arm motions in coordination with other systems.
• Develop and maintain simulated environments and automated test frameworks to support continuous integration and system verification.
• Lead system integration and validation efforts across hardware and software.
• Participate in architecture decisions for controls and electrical systems, including component selection and standardization.
• Participate in design & code reviews to maintain consistency and high-quality output.

MINIMUM QUALIFICATIONS

• Masters Degree or higher in Software Engineering, Robotics, Mechanical Engineering, or a related field.
• 5+ years of professional experience in robotics software development.
• Expert-level proficiency in modern C++ (17 or newer) and Python within a professional robotics software development environment.
• Deep foundational understanding of robotic arm kinematics (forward and inverse), multi-body dynamics, and motion planning.
• Hands-on experience with robotic platforms, sensors, actuators, localization, perception, and control systems.
• Practical experience designing and optimizing sensor fusion and state estimation algorithms (e.g., Kalman Filters).
• Strong knowledge of autonomy algorithms, robotics frameworks (such as ROS), and simulation environments.

PREFERRED QUALIFICATIONS

• Experience programming industrial robots in high-level languages.
• Experience in formal control theory and linear algebra.
• A general understanding of how to manage redundant kinematic chains or stabilize dynamic systems.
• Proven track record of delivering products to end users and production environments.
• Familiarity with hardware design, prototyping, and manufacturing processes.
• Excellent problem-solving skills and a strong analytical mindset to identify issues, propose innovative solutions, and make data-driven decisions.
• Ability to earn trust, maintain positive and professional relationships, and contribute to a culture of performance.

About us

Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry.

As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone.

Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation.

Job Summary

We are seeking a Staff Hardware Engineer to provide advanced operational, diagnostic, and engineering support for Graphcore’s Arm-based hardware platforms across lab and data center environments.

This role focuses on supporting hardware bring-up, validation, and troubleshooting of complex AI compute platforms, including server blades, racks, and rack-scale infrastructure. The successful candidate will collaborate closely with engineering, platform, and data center teams to ensure the reliability and performance of next-generation AI systems.

The Team

The Systems Engineering and Hardware Engineering teams are responsible for enabling the bring-up, validation, and operational reliability of Graphcore’s AI infrastructure platforms.

The team works closely with server engineering, firmware teams, platform architects, and data center operations to support the development, testing, and deployment of next-generation AI compute systems.

This collaborative environment enables rapid problem-solving and continuous improvement of Graphcore’s hardware platforms from early development through production deployment.

Responsibilities and Duties

• Lead advanced break-fix troubleshooting for server blades, motherboards, power systems, and rack-scale infrastructure.
• Support engineering bring-up activities, including component validation and firmware interaction testing.
• Diagnose system-level failures involving thermal behavior, power anomalies, network configuration, and BIOS/BMC issues.
• Collaborate with server engineering teams to perform root cause analysis and propose corrective actions or design improvements.
• Support deployment and rollout of next-generation hardware platforms through structured validation and qualification cycles.
• Interface with facilities and infrastructure teams to understand environmental factors impacting system reliability.
• Develop and maintain standard operating procedures (SOPs), troubleshooting guides, and validation documentation.
• Provide guidance and mentorship to junior technicians and engineers on troubleshooting methodologies and hardware diagnostics.
• Participate in on-call rotations or off-hours support during critical engineering milestones or hardware bring-up phases.

Candidate Profile

Essential

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related discipline.
• Strong experience with server hardware architectures and board-level debugging.
• Experience analyzing system logs, hardware telemetry, and power/thermal metrics to isolate hardware failures.
• Hands-on experience with HPC systems, AI compute platforms, or rack-scale infrastructure.
• Strong collaboration skills and ability to work effectively in fast-paced engineering environments.
• Excellent written and verbal communication skills.

Desirable

• Experience supporting prototype or pre-production hardware bring-up.
• Familiarity with data center facilities, including liquid cooling and power distribution systems.
• Experience using Python, Bash, or automation tools for hardware validation or troubleshooting.
• Exposure to structured failure analysis and reliability engineering methodologies.

About us

Graphcore is one of the world’s leading innovators in Artificial Intelligence compute.

It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry.

As part of the SoftBank Group, Graphcore is a member of a best-in-class family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone.

Graphcore’s teams are drawn from a diverse set of backgrounds and bring a broad range of skills and perspectives.   A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation.

Job Summary

We are seeking a principled and dynamic Lead Systems and Validation Engineer to drive end-to-end system validation for AI compute blade and rack platforms. This high-visibility role focuses on first silicon bring-up, system enablement, and post-silicon validation across hardware, firmware, and software domains. You will lead validation strategy, execution, and debug while collaborating closely with cross-functional engineering teams to deliver high-quality, industry-leading AI systems.

The Team

The Systems Validation team is responsible for enabling and validating Graphcore’s AI compute platforms from first silicon through production. The team works closely with system architects, firmware, silicon, and infrastructure teams to ensure system readiness, scalability, and quality at rack level.

Responsibilities and Duties

• Lead system enablement including first silicon bring-up and integration of firmware and platform components to meet system architecture specifications.
• Develop validation methodologies, lab hardware infrastructure, system software capabilities, and debug tools for blade and rack-level validation.
• Triage and debug issues across bring-up, post-silicon validation, and production phases ensuring timely resolution with high quality.
• Define and own validation test plans, develop test cases, and drive execution across domains such as CPU, GPU, memory, HBM, and IO.
• Drive innovation in validation through development of tools, scripts, and improved methodologies to enhance coverage, efficiency, and quality.
• Enable comprehensive system verification by integrating storage, networking, and infrastructure capabilities within lab environments.  
• Collaborate with multi-functional teams including system architecture, embedded software, hardware build, and ODM partners.    
• Provide technical leadership and mentorship, fostering engineering perfection and continuous improvement.

Candidate Profile

Essential:

• Strong analytical and problem-solving skills with high attention to detail.
• Extensive experience in system validation encompassing initial silicon integration and HW/FW/SW validation.  
• Strong understanding of industry-standard interfaces such as PCIe and CXL.
• Experience enabling storage and networking systems in lab environments for end-to-end validation.
• Deep knowledge of ARM or x86 architectures, SoC design, memory, RAS, and power management.
• Experience with system-level debug, operating systems, BIOS, and device drivers.
• Strong experience with Linux, Windows, and virtualization technologies (VMware, KVM, Hyper-V).
• Excellent communication, organization, and cross-functional collaboration skills.
• Ability to lead multiple workstreams and deliver under tight timelines.
• Experience in technical program management and driving validation initiatives.

Desirable:

• Master’s or PhD in Electrical Engineering, Computer Engineering, or related field.
• Demonstrated ability working on complex system validation and debug in data center or rack-scale environments.
• Experience designing or validating AI/ML rack-scale systems.
• Knowledge of hardware development best practices and industry standards.
• Familiarity with emerging AI and data center infrastructure technologies.
• Experience collaborating with ODM partners globally.

About us 

Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. 

As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. 

Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation. 

Job Summary 

We are seeking an experienced Principal Security Firmware Engineer to design, implement, and validate security mechanisms within embedded firmware and low-level system software supporting Graphcore’s AI compute platforms. 

This role focuses on protecting hardware platforms through secure firmware architecture, trusted boot mechanisms, and secure firmware update frameworks while working closely with hardware, firmware, and security architecture teams. 

The Team 

Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. 

The Firmware and Platform Security team is responsible for securing Graphcore’s AI infrastructure platforms across firmware and hardware interface layers. 

The team collaborates with silicon engineering, hardware design teams, firmware developers, and security architects to implement trusted boot chains, secure firmware update mechanisms, and hardware-rooted security capabilities. 

Responsibilities and Duties 

• Design and implement secure firmware architectures for embedded and hardware systems. 

• Develop secure boot, firmware authentication, hardware root of trust, and secure firmware update mechanisms. 

• Define threat models and security requirements for firmware components. 

• Develop and maintain secure embedded firmware using languages such as C, C++, and Rust. 

• Integrate cryptographic libraries and hardware security modules (HSM/TPM). 

• Implement protections against firmware tampering, side-channel attacks, fault injection, and reverse engineering. 

• Perform firmware security assessments, code reviews, and vulnerability analysis. 

• Conduct penetration testing, fuzz testing, and other security validation techniques. 

• Collaborate with hardware teams to integrate chip-level security features. 

• Ensure firmware implementations align with industry standards such as NIST, FIPS, and Secure Development Lifecycle practices. 

Candidate Profile 

Essential 

• Bachelor’s or Master’s degree in Computer Engineering, Computer Science, Electrical Engineering, or related discipline. 

• 5–10+ years of experience in embedded systems or firmware development. 

• Strong programming experience in C and C++. 

• Deep understanding of secure boot architectures and trusted boot chains. 

• Strong knowledge of cryptographic protocols and secure firmware design practices. 

• Experience working with embedded operating systems such as FreeRTOS, Zephyr, or Linux. 

• Experience implementing secure firmware update systems and cryptographic key management. 

Desirable 

• Programming experience in Rust. 

• Experience integrating TPM or hardware security modules (HSM). 

• Experience with static analysis and security tools such as Coverity. 

• Knowledge of secure silicon architectures and trusted execution environments. 

• Experience contributing to open-source firmware security projects. 

Benefits:

In addition to a competitive salary, Graphcore offers a competitive benefits package. We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments. 

About us

Graphcore is one of the world’s leading innovators in Artificial Intelligence compute.
It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry.

As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone.

Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation.

Job Summary

We are seeking a Senior Principal Network Engineer to help design, deploy, and optimize next‑generation AI data center networks. AI training and inference workloads require extremely high bandwidth, deterministic low latency, and zero‑packet‑loss networking environments.

In this role, you will partner closely with the Network Architecture Lead to design and scale high‑performance computing (HPC) network fabrics supporting GPU clusters. You will work across hardware, networking, and AI application layers to ensure Graphcore’s large‑scale AI infrastructure operates at peak performance.

The ideal candidate brings deep experience operating hyperscale or HPC data center networks and has expertise in high‑speed Ethernet fabrics, RDMA technologies, advanced automation, and telemetry systems.

The Team

The Data Center Network Engineering team designs and operates the high‑performance network fabrics that power Graphcore’s AI compute platforms. The team collaborates closely with hardware engineering, AI researchers, and infrastructure teams to build scalable networking environments optimized for distributed training and inference workloads.

Engineers work on pioneering technologies including high‑speed Ethernet fabrics, lossless networking, RDMA transport, and large‑scale automation frameworks to support next‑generation AI clusters.

Responsibilities and Duties

• Assist in defining ultra‑high‑bandwidth, non‑blocking AI network fabrics (Clos spine‑leaf‑super‑spine architectures) for large‑scale distributed AI workloads.
  • Optimize performance of lossless Ethernet fabrics using congestion control mechanisms such as PFC, ECN, and DCQCN to support RDMA/RoCEv2 communication.
  • Lead initiatives to implement NetDevOps practices and develop automation for provisioning, configuration management, and network remediation.
  • Design and deploy high‑resolution telemetry pipelines to monitor network health, detect microbursts, and analyze congestion patterns.
  • Support modeling, deployment, configuration, and monitoring of data center network fabrics including scale‑out, scale‑up, and front‑end networks.
  • Collaborate cross‑functionally with hardware engineers, AI researchers, and data center operations teams to co‑design high‑performance infrastructure.
  • Provide technical leadership and mentorship to network engineers while establishing best practices and operational standards.
  • Contribute to the long‑term networking strategy and roadmap for Graphcore’s AI infrastructure.
  • Research and evaluate next‑generation high‑speed networking technologies and vendor solutions.
  
  

Candidate Profile

Essential

• BS or MS or equivalent experience in Computer Science, Electrical Engineering, Network Engineering, or related technical discipline.
  • 12+ years of progressive network engineering experience with at least 3 years in hyperscale, high‑density, or HPC data center environments.
  • Expert‑level knowledge of data center routing and switching protocols including BGP, OSPF, and EVPN‑VXLAN architectures.
  • Strong operational understanding of RDMA networking technologies such as RoCEv2 or InfiniBand.
  • Hands‑on experience with modern merchant silicon networking platforms and NOS platforms such as Arista EOS, Cisco NX‑OS, or SONiC.
  • Experience deploying high‑speed network technologies including 400G/800G optics and large‑scale fabric architectures.
  • Proficiency in automation and scripting languages such as Python, Go, Bash, or similar tools.
  • Strong collaboration and communication skills across cross‑functional engineering teams.
  
  

Desirable

• Experience operating large‑scale AI or GPU clusters.
  • Familiarity with network telemetry frameworks and streaming analytics.
  • Experience implementing NetDevOps workflows and infrastructure automation pipelines.
  • Experience influencing vendor roadmaps or evaluating next‑generation networking technologies.
  
  

About us

Graphcore is one of the world’s leading innovators in Artificial Intelligence compute.

It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry.

As part of the SoftBank Group, Graphcore is a member of a best-in-class family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone.

Graphcore’s teams are drawn from a diverse group of backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation.

Job Summary

We are seeking a senior validation lead engineer to lead at-scale rack validation efforts for next-generation AI hyperscale systems. This role focuses on post-silicon system validation across the full lifecycle, ensuring functional, electrical, and thermal performance meets product objectives. You will own end-to-end blade and rack validation including planning, development, execution, and debug while collaborating across firmware, systems, and hardware teams.

The Team

The Rack Validation team is responsible for ensuring system readiness and quality at scale. The team works cross-functionally with firmware, silicon, and system engineering teams to validate complex AI compute platforms.

Responsibilities and Duties

• Lead post-silicon validation of AI compute blades and racks including test planning, development, and automation.
• Drive provisioning and integration of system components (SoC FW, BMC, RMC, OS) for rack-level readiness.
• Own execution against program achievements and report validation progress and risks.
• Triage test failures, collect debug data, and collaborate on root cause analysis.
• Track validation coverage and continuously improve test processes and infrastructure.
• Collaborate with ODM/JDM partners on validation and quality.
• Mentor engineers and drive engineering excellence.

Candidate Profile

Essential:

• Bachelor’s or Master’s degree or equivalent experience in Computer Engineering, Electrical Engineering, Computer Science, or related field.
• Proven track record in system, rack, or embedded validation with leadership experience.
• Strong experience in large-scale hardware validation environments.
• Expertise in CPU/GPU, memory, IO, and firmware validation.
• Experience with Linux/server OS and automation using Python/Bash.
• Knowledge of IPMI, Redfish, PLDM.
• Experience with CI/CD pipelines and hardware interfaces.

Desirable:

• Experience in hyperscale environments.
• Familiarity with OpenBMC and processes for verifying firmware functionality.  
• Knowledge of firmware security and HIL testing.
• Experience with test management tools.

About us

Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry.

As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies.

Job Summary

We are seeking a highly skilled and hands-on Test Framework Software Engineer to develop, implement, and maintain robust test automation solutions that drive hardware quality and reliability across our AI hardware platforms. This role focuses on building scalable automation frameworks, translating hardware specifications into test solutions, and enabling efficient validation across development and production environments.

The Team

You will work closely with hardware, systems, and product engineering teams to ensure high-quality validation of complex AI systems. The team operates across hardware platforms, system validation, and production test environments.

Responsibilities and Duties

- Design, implement, and extend test automation frameworks for hardware qualification and validation.

- Translate hardware specifications into scalable, maintainable automated test suites.

- Collaborate with cross-functional teams to ensure test coverage meets product and quality requirements.

- Debug and troubleshoot issues in automation frameworks across environments and platforms.

- Develop tooling to process, analyze, and visualize test data for actionable insights.

- Optimize test execution efficiency and improve validation methodologies.

- Communicate technical status, risks, and insights to engineering stakeholders.

Candidate Profile

Essential:

- Bachelor’s or Master’s degree in Computer Science, Electrical Engineering, or related field.

- Extensive experience (10–15+ years) in automation systems, test frameworks, or infrastructure.

- Strong proficiency in Python, Bash, or similar scripting languages.

- Experience with Linux/Unix environments and hardware testing frameworks.

- Strong problem-solving skills and ability to work independently in cross-functional teams.

- Experience building scalable, maintainable, and reliable automation systems.

- Excellent communication and collaboration skills.

Desirable:

- Experience with test orchestration systems or automation infrastructure.

- Familiarity with CI/CD pipelines and version control (e.g., Git).

- Background in AI hardware, embedded systems, or BMC environments.

- Experience integrating automated testing into manufacturing or deployment systems.

About us

Graphcore is one of the world’s leading innovators in Artificial Intelligence compute.
It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry.

As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone.

Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation.

Job Summary

Graphcore is seeking a Staff Mechanical Engineer to join our Data Center Engineering organization and drive engineering coordination efforts with external data center developers. You will be working with a multi-disciplinary team of technical leaders to deliver best-in-class infrastructure solutions. The ideal location for this position will be based out of Austin. Roughly 10-20% travel time can be expected..

The Team

The Data Center Engineering team is responsible for the design, development, and deployment of infrastructure that supports Graphcore’s advanced AI compute platforms.
The team collaborates with internal engineering groups, external consultants, and data center developers to deliver reliable and scalable environments for high-performance computing workloads.

Team members work across multiple disciplines—including mechanical, electrical, facilities, and IT infrastructure—to ensure that Graphcore’s data center deployments meet stringent performance, efficiency, and operational reliability requirements.

Responsibilities and Duties

• Develop and review design standards and specifications, ensuring alignment with industry standard methodologies and Graphcore’s reliability goals.
• Perform detailed engineering analysis of designs, ensuring efficiency and reliability of operation.
• Provide direction, coordinate with, and review the designs of external consultants and partners.
• Ensure delivery of future-proof engineered solutions.
• Conduct site inspections and attend factory visits critical infrastructure and equipment.
• Define and issue owner’s requirements for mechanical systems design.
• Manage design teams from an owner’s perspective and make decisions to keep projects moving forward.
• Stay informed on the latest industry developments and emergent technologies within the data center industry.

Candidate Profile:

Essential:

• Bachelor’s degree or equivalent experience in Mechanical Engineering or related field.
• Deep technical knowledge of HVAC equipment and systems including: chillers, boilers, pumps, air handling equipment, duct and piping design, sequence of controls.
• Experience coordinating with IT teams for infrastructure design in support of HPC racks and data centers.
• Excellent interpersonal skills and ability to collaborate in a cross-discipline team.
• Comfortable with a fast-paced environment that is rapidly developing and changing.
• Professional Engineering (PE) license or equivalent international certification (this position will not be stamping drawings as EOR).

Desirable:

• Prior experience with hyperscale data center environments or co-location facilities at the Tier III or Tier IV levels as defined by Uptime Institute.
• Experience with plumbing systems equipment and design (domestic water, waste/vent, etc.)
• Visio, BlueBeam, AutoCAD, Revit, or other design and drafting software.

Position Summary 

The AI Implementation Lead is the Data Team's hands-on builder, deploying AI solutions where Data Team work meets the business. The ideas are coming faster than the implementation; this role exists to close that gap. The work spans agents, plug-ins, applications, integrations, and whatever form the use case calls for. You will scale IEM's existing AI-native infrastructure (Claude Code in daily use, multiple local MCP servers wired to production data systems, an internal multi-agent portfolio across analytics and operations, and an established AI-assisted development culture) from a director-led prototype into a Data Team production platform. This role works in coordination with IEM's Enterprise AI team, which sets enterprise AI strategy and policy; the AI Implementation Lead applies that framework to the solutions you build rather than authoring it. This is the first dedicated AI engineer on the Data Team, offered with track flexibility as either a principal individual contributor or a hands-on people leader managing 2 to 4 engineers as the function scales. 

Ideal Candidate Profile 

You have 5+ years of software engineering experience with hands-on AI and agentic system development. You have built agents, plug-ins, or AI applications that real organizations have used, not coursework or POCs. You think first about the use case and the user, then about the system, then about the model. You write production code yourself and pride yourself on building solutions that actually get adopted. You partner naturally with non-technical stakeholders, translating fuzzy AI ideas into deployed solutions and surfacing the questions behind the questions. You are comfortable working with modern agent tooling such as Claude Code, MCP, LangGraph, Mastra, or Pydantic AI, and you treat AI-assisted development as a daily multiplier for engineering, governance, documentation, and adoption work. You have a working knowledge of AI governance and security including prompt injection mitigation, data leakage prevention, and model risk. You are excited about defining a new function inside a Data Team that already has the foundation in place. 

Key Responsibilities 

• AI Solution Deployment: Build agents, plug-ins, applications, and integrations as use cases emerge from the Data Team's work and the partners it supports 

• Agent Development: Design and develop custom agents and agent harnesses, including MCP servers, orchestration logic, prompt engineering, and eval scaffolding. Agents are the centerpiece of the function. 

• Vendor AI Extension: Build on top of Salesforce Einstein, Tableau Pulse-AI, ETQ-AI, Fellow.ai, and the data-platform AI capabilities IEM brings on next 

• Solution Discovery: Run intake conversations with internal partners to surface high-value AI use cases, pressure-test feasibility against existing tooling, and prioritize the implementation roadmap 

• AI Governance and Security: Build with data leakage prevention, prompt injection mitigation, and model risk as first-class concerns, in alignment with IEM's broader AI policy framework 

• Adoption and Enablement: Train users, write documentation, and run enablement programs so the AI solutions you deliver get used by the people they were built for 

• Cross-Functional Delivery: Coordinate with the internal teams the Data Team serves through build and rollout, keeping stakeholders aligned as solutions move from idea to deployment 

• Documentation: Maintain design notes, integration docs, and runbooks for the AI solutions you deliver so the team can support and extend your work 

• AI-Assisted Development: Use modern AI coding tools such as Claude Code and Cursor as part of your daily practice, setting the standard for the rest of the Data Team 

• Team Leadership: If filling the people-leader track, hire, coach, and grow a small team of AI engineers as the function scales 

• Engineering Standards: Participate in code reviews, follow Git workflows and CI/CD practices, and contribute to evolving the team's AI engineering conventions 

• Continuous Learning: Stay current with the rapidly evolving AI tooling landscape, bringing ideas back to the team and helping raise the bar over time 

Qualifications 

• Bachelor's degree in Computer Science, Information Systems, Data Science, Engineering, or a related technical field, or equivalent professional experience 

• 5+ years of software engineering experience, with at least 2 years building AI or agentic systems used by a real organization 

• Direct experience building agents, plug-ins, or AI applications used in a real working environment, not coursework, prototypes, or POCs 

• Hands-on experience with modern agent tooling such as Claude Code, MCP (Model Context Protocol), LangGraph, Mastra, Pydantic AI, or comparable frameworks 

• Strong programming skills in Python, including async patterns, type hints, and testing 

• Working knowledge of large language model APIs (Anthropic, OpenAI, or comparable), with hands-on prompt engineering, evaluation, and iteration on production prompts 

• Working knowledge of AI governance and security including prompt injection mitigation, data leakage prevention, model risk, and vendor review 

• Track record of driving adoption of AI or technical solutions with users outside the immediate engineering team 

• Strong written and verbal communication skills with the ability to explain technical AI concepts to non-technical stakeholders and to gather requirements from business users 

• Comfortable with Git version control, code review, and modern engineering workflows including CI/CD 

• Self-motivated with the ability to work independently in a remote environment while collaborating effectively across a distributed team 

• Preferred: People leadership experience including managing 2 to 5 engineers and running technical hiring 

• Preferred: Experience extending vendor AI platforms in the data and analytics ecosystem (Salesforce Einstein, Tableau Pulse-AI, BI vendors, vertical SaaS) 

• Preferred: Mid-market or operational and manufacturing context, vs. a purely big-tech background 

• Preferred: Familiarity with manufacturing systems such as Infor Syteline, ERP platforms, or shop floor and quality systems 

Location 

Fully remote within the United States. May require up to 10% travel to IEM facilities for team collaboration, project kickoffs, and stakeholder meetings. 

At Tenstorrent, we’re redefining compute performance from the ground up by designing CPUs that power the future of AI and high-performance workloads. As a CPU Microarchitecture & Performance Modeling Intern, you’ll help analyze, model, and optimize real processor designs to push efficiency and speed to new limits. If you love figuring out how every cycle, cache, and pipeline stage adds up to performance, this role is for you!

This role is hybrid based out of Toronto, Boston, Austin or Santa Clara (preferred).

Who You Are

• A detail-oriented engineer who loves understanding how CPUs really work — from pipelines and caches to instruction flow and branch prediction.
• Excited to turn theoretical architecture concepts into measurable performance insights.
• Analytical, curious, and eager to explore the trade-offs between power, area, and performance in modern CPU design.
• Comfortable using data and modeling tools to drive real engineering decisions.
• Collaborative and motivated to learn from experienced hardware architects in a fast-paced, hands-on environment.

What We Need

• A co-op or PEY student pursuing a BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• Strong foundation in computer architecture and CPU microarchitecture (pipelines, caches, memory hierarchies, branch prediction, etc.).
• Experience or coursework in performance modeling, simulation tools, or workload analysis.
• Familiarity with CPU workloads and performance metrics (IPC, CPI, latency, throughput, etc.).
• Proficiency with Python or other scripting languages for data analysis and automation.

What You Will Learn

• Develop and run CPU performance models to explore architectural trade-offs and identify bottlenecks.
• Conduct CPU workload analysis using real benchmarks and synthetic tests to measure performance efficiency.
• Collaborate with microarchitecture and RTL teams to connect performance data with design decisions.
• Support validation and tuning of CPU pipelines, memory subsystems, and branch prediction logic.
• Automate data collection, visualization, and reporting workflows for performance experiments.
• Contribute to ongoing research on improving CPU design methodologies for next-generation compute architectures.

Tenstorrent is seeking a SoC Physical Design Verification Engineer to drive full-chip signoff and ensure manufacturable, high-quality silicon across advanced technology nodes. You’ll lead physical verification closure (DRC, LVS, ERC, etc.), debug issues using standard industry PV tools, and collaborate across RTL, PD, CAD, and packaging teams to achieve successful tapeouts. If you thrive in a fast-paced environment and enjoy solving complex challenges in cutting-edge silicon, we’d love to hear from you.

This role is hybrid, based out of Santa Clara, CA or Austin, TX or Fort Collins, CO.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A seasoned engineer with a strong background in CPU/IP/SoC physical verification and tapeout closure.
• A hands-on problem solver who excels at debugging and driving signoff through complex verification flows.
• A collaborative team player who works effectively across RTL, PD, CAD, and foundry interfaces.
• A mentor and technical leader passionate about building efficient, manufacturable silicon.
  
  

What We Need

• BS/MS in Electrical/Electronics Engineering (or related) with 7–14 years of hands-on CPU/IP/SoC physical verification experience.
• Proven expertise in DRC, LVS, ERC, PERC, Antenna, and DFM verification using industry-standard tools and flows (Calibre, ICV, Pegasus, FC, Innovus, etc.).
• Strong background in ESD planning, padring integration, bump/RDL strategies, and reliability analysis (IR drop, EM), with solid understanding of advanced nodes (7nm, 5nm, 3nm) and FinFET design challenges.
• Scripting proficiency in Python and TCL for automation and flow optimization.

What You Will Learn

• Advanced physical verification methodologies and flow optimization for next-generation SoCs.
• Integration and verification strategies for full-chip signoff across advanced process technologies.
• Cross-functional collaboration across design, CAD, and foundry teams to ensure flawless tapeouts.
• Leadership and mentoring opportunities in building scalable PV methodologies and automation.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This position requires access to technology that requires a U.S. export license for persons whose most recent country of citizenship or permanent residence is a U.S. EAR Country Groups D:1, E1, or E2 country. 

We are seeking a junior-to-mid level SOC Emulation Engineer to support our hardware emulation infrastructure and internal chip design teams. This role focuses on integrating vendor and custom hardware transactors, developing Python-based test frameworks, and providing technical support to emulation users across multiple chip projects.

This role is hybrid, based out of Santa Clara, CA or Austin, TX.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Background in Electrical/Computer Engineering or Computer Science with 1-3 years of experience in chip design, verification, or emulation.
• Proficient in Python for automation and test development, with a working knowledge of C++ and the ability to navigate SystemVerilog RTL.
• Skilled at using modern AI tools (Claude, ChatGPT, Copilot) to accelerate code generation, debugging, and documentation analysis.
• Energetic about supporting diverse teams, from high-level software to low-level firmware, to solve complex runtime and build issues.

What We Need

• Ability to integrate vendor and custom transactors into RTL testbenches while handling clock domain and tri-state resolution.
• Experience building Python APIs (using pybind11) and maintaining CMake-based compilation flows for emulation libraries.
• Solid understanding of standard chip interfaces, bus protocols, and hardware synchronization (resets/clocking).
• A commitment to triaging and debugging the full stack, spanning from Python tests and C++ bindings down to hardware.

What You Will Learn

• Deepening your expertise with world-class platforms like Synopsys Zebu for massive-scale silicon validation.
• Gaining a holistic view of chip development by bridging the gap between hardware RTL and software drivers.
• Building and optimizing large-scale emulation build and run tooling for high-performance engineering teams.
• Refining your ability to gather requirements and facilitate communication between hardware designers and software engineers.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

As a Senior Chiplet Physical Design Engineer at Tenstorrent, you will work on a high-profile, cutting-edge program designing and integrating multiple chiplets into a System-in-Package (SiP). You’ll collaborate closely with Tenstorrent experts and leaders across the USA, Japan, and other global sites, as well as external partners, to deliver world-class CPU and AI silicon. In this role, you will own critical aspects of synthesis and place-and-route for high-speed CPU core designs, contributing directly to performance, power, and area outcomes on advanced process nodes.

This role is remote, based out of The United States.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• An experienced physical design engineer who thrives in complex, multi-stakeholder projects.
• Detail-driven, with a strong sense of ownership from synthesis through design closure.
• Comfortable working at advanced nodes (3nm and below) and multi-GHz designs.
• A collaborative team player who enjoys mentoring others and influencing methodology.
• Clear communicator who can balance technical depth with schedule and resource constraints.

What We Need

• Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or Computer Science.
• 10+ years of industry experience in physical design for CPU, or GPU products.
• Strong hands-on experience with Synopsys and/or Cadence tools across synthesis, P&R, and closure.
• Proven expertise in timing closure, ECO flows, and PV convergence at block and chip level.
• Proficiency in scripting (TCL required; Python or similar strongly preferred) and strong English communication skills.

What You Will Learn

• How large-scale chiplet-based systems are architected, implemented, and integrated into SiP solutions.
• Best practices for achieving timing and power convergence on advanced silicon technologies.
• How physical design decisions impact system-level performance and scalability.
• Effective collaboration across global teams and external partners.
• How Tenstorrent evolves and standardizes physical design methodologies across projects.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is seeking an experienced EDA/PDK CAD Engineer to build and maintain world-class design infrastructure that accelerates our silicon innovation. In this role, you'll install and optimize PDKs, manage EDA tool flows, and partner with analog, digital, and software teams to continuously improve design efficiency. If you're passionate about solving complex CAD challenges and enabling cutting-edge chip design, we want you on our team.

This role is hybrid, based out of Santa Clara, CA or Austin, TX or Fort Collins, CO.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A self-driven problem solver with deep knowledge of PDKs, EDA tools, and IC design flows.
• Experienced in troubleshooting complex CAD issues and developing creative work-around solutions.
• Collaborative communicator who actively seeks feedback to improve team productivity.
• Passionate about challenging industry-leading tools and methodologies to drive continuous improvement.

What We Need

• BS, MS, or Ph.D. in Electrical Engineering and/or Computer Science with 5+ years of industry experience.
• Hands-on expertise installing, configuring, and maintaining PDKs and EDA environments.
• Strong background supporting physical verification flows (DRC, LVS, EM/IR, extraction) and mixed-signal simulation.
• Proven ability to work with vendors, foundries, and cross-functional teams to resolve technical issues.

What You Will Learn

• How to architect and scale design infrastructure for state-of-the-art AI silicon development.
• Advanced techniques for optimizing EDA flows across analog, digital, and mixed-signal domains.
• Direct collaboration with world-class engineers to shape tools and methodologies that define industry standards.
• Best practices for proactive CAD support and continuous flow improvement in a fast-paced innovation environment.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is seeking a SoC Physical Design Verification Engineer to drive full-chip signoff and ensure manufacturable, high-quality silicon across advanced technology nodes. You’ll lead physical verification closure (DRC, LVS, ERC, etc.), debug issues using standard industry PV tools, and collaborate across RTL, PD, CAD, and packaging teams to achieve successful tapeouts. If you thrive in a fast-paced environment and enjoy solving complex challenges in cutting-edge silicon, we’d love to hear from you.

This role is hybrid, based out of Santa Clara, CA; Austin, TX; or Fort Collins, CO.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A seasoned engineer with a strong background in CPU/IP/SoC physical verification and tapeout closure.
• A hands-on problem solver who excels at debugging and driving signoff through complex verification flows.
• A collaborative team player who works effectively across RTL, PD, CAD, and foundry interfaces.
• A mentor and technical leader passionate about building efficient, manufacturable silicon.
  
  

What We Need

• BS or MS in Engineering (Electrical, Electronics, or related field).
• 7–14 years of hands-on experience in CPU/IP/SoC physical verification.
• Strong command of industry-standard tools and flows (Calibre, ICV, Pegasus, FC, Innovus, etc.).
• Proven expertise in DRC, LVS, ERC, PERC, Antenna, and DFM verification.
• Solid understanding of advanced node challenges (7nm, 5nm, 3nm) and FinFET design considerations.
• Scripting proficiency (Python, TCL) for automation and flow optimization.
• Familiarity with ESD planning, padring integration, bump/RDL strategies, and reliability analysis (IR drop, EM).
  
  

What You Will Learn

• Advanced physical verification methodologies and flow optimization for next-generation SoCs.
• Integration and verification strategies for full-chip signoff across advanced process technologies.
• Cross-functional collaboration across design, CAD, and foundry teams to ensure flawless tapeouts.
• Leadership and mentoring opportunities in building scalable PV methodologies and automation.
  
  

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

RISC-V CPU RTL owner will play a key role in developing next-generation CPU design. This position requires a deep understanding of CPU design including Architecture, RTL, Design Verification, Physical Design Flow. The ideal candidate will drive the unit specification, RTL design, and unit verification.

This role is Remote, based out of The United States.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Key Responsibilities:

• RISC-V CPU Unit Microarchitecture Specification: Define and develop microarchitecture specifications for the assigned unit (branch predictor, rename, instruction scheduling, vector execution, load/store, vector load/store support). The specification includes not only design, but also comprehensive analysis / strategy for verification and PPA (power, performance, area) closure.
• RISC-V CPU Core Unit RTL Design: The candidate will be responsible for the quality of RTL including design verification and PPA closure. This includes writing RTL, reviewing / refining unit verification environment, applying right RTL optimization to control PPA.
• AI Assisted Design Adaption: To maximize the team’s output, the candidate actively uses AI tools to accelerate the CPU design process.
• Mentoring Junior Engineers: depending on a seniority of the engineer, the engineer may mentor junior members in the team.

Qualifications:

• Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• Proven track record of designing high-performance CPU RTL for x86, Arm, POWER, SPARC, or RISC-V.
• Deep understanding of design verification strategy and trade-offs for verification methodology (simulation, formal, various checkers, etc…)
• Deep understanding of CPU microarchitecture and PPA trade-off.
• Basic understanding of RISC-V Architecture including V-extension is preferred.
• Proficiency in hardware description languages (HDLs) such as Verilog, SystemVerilog or VHDL.
• Excellent problem-solving abilities and analytical skills.
• Strong communication skills, with the ability to convey complex technical concepts to diverse audiences.
• Ability to work collaboratively in a team-oriented environment and across multiple disciplines.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent is seeking an Physical Design Engineer to lead  cross-functional efforts to solve complex physical design challenges and develop end-to-end RTL-to-GDS methodologies across advanced nodes, with a strong focus on PPA and runtime improvements. The engineer will architect, integrate, and deploy AI/ML-driven solutions into production physical design flows, creating custom CAD tools and partnering with internal teams and EDA vendors to drive next-generation, ML-enabled capabilities. 

This role is hybrid, based out of Santa Clara, CA or Austin, TX or Fort Collins, CO.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who you are

• BS in Electrical or Computer Engineering (or equivalent experience) with 5+ years in Physical Design CAD methodology at advanced nodes.
• Proven track record improving PPA and/or runtime on high-performance, low-power taped-out designs.
• Hands-on with industry-standard EDA tools (e.g., Fusion Compiler) across synthesis, P&R, STA, signoff, and hierarchical flows.
• Strong Python/Tcl and data skills, with interest or experience in ML frameworks (PyTorch, TensorFlow), and the ability to drive complex projects independently.

What we need

• Lead and contribute to cross-functional efforts solving complex physical design challenges across IPs, projects, and advanced technology nodes.
• Develop and enhance RTL-to-GDS methodologies, including floorplanning, synthesis, P&R, STA, signoff, and assembly.
• Architect and deploy AI/ML-driven solutions in production flows to improve engineering efficiency, turnaround time, and QoR.
• Optimize EDA tools and custom CAD flows using data-driven and ML-based techniques, in close collaboration with verification, extraction, timing, DFT, and EDA vendors.

What you will learn

• How to scale AI/ML-driven methodologies across diverse products and advanced technology nodes in real production flows.
• New ways to blend classical EDA algorithms with modern ML techniques to push PPA and runtime limits.
• Best practices for deploying, validating, and monitoring ML models in production CAD environments.
• How to influence next-generation ML-enabled EDA tools and collaborate deeply with cross-functional teams (PV, extraction, timing, DFT).

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This position requires access to technology that requires a U.S. export license for persons whose most recent country of citizenship or permanent residence is a U.S. EAR Country Groups D:1, E1, or E2 country. 

Tenstorrent is seeking a Signal Integrity Engineer to join our growing team. The ideal candidate will have a wealth of exposure designing high speed interconnects, breakout design, material trade-offs and verification. A background in electrical engineering, electronics or relevant fields is required. Must love all things high speed!

This role is hybrid, based out of Santa Clara, CA or Austin, TX or Toronto, ON.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• You have a Bachelor’s degree in Electrical Engineering (or equivalent) and 5+ years working in high-speed digital design with a focus in high-speed PCB or package design at 10Gbps and above (e.g. 100GbE, GDDR6, PCIe Gen5+).
• You’re comfortable working with high-speed performance metrics such as ICR, ERL, COM, NEXT, and FEXT as well as knowledge of high-speed connector technologies, including NPO, CPO, and emerging standards.
• You are proficient with PCB ECAD tools (ideally Cadence Allegro).
• You communicate clearly (written and verbal), think critically, and love solving complex signal integrity problems.
• You’re enthusiastic about all things high speed and enjoy collaborating across teams

What We Need

• Design, extract, and simulate complex breakout structures, including end-to-end simulations and validation against physical hardware. Perform simulation and extraction of board models for both SI and PI.
• Contribute to design and sign-off with internal and external ASIC packaging teams, ODMs, and internal layout teams. Create design specifications, work with external vendors, and drive adoption of new interconnect and packaging technologies.
• Actively participate in design reviews, providing insight from your SI/PI expertise and a broader system perspective.
• Support post-silicon bring-up and help troubleshoot production and field failures related to signal and power integrity. Document design processes and provide training/knowledge sharing to other team members.

What You Will Learn

• How to work at the cutting edge of high-speed interconnects, influencing the next generation of ASIC packaging and PCB architectures.
• Deep exposure to advanced ASIC packaging flows and collaboration models with internal and external packaging teams.
• Hands-on experience with emerging high-speed connector technologies and materials, including evaluating material trade-offs for performance and manufacturability.
• Best practices for end-to-end SI/PI validation, from simulation through to lab correlation, post-silicon bring-up, and field failure analysis.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is seeking a senior High Speed Interconnect / Signal Integrity Engineer to design and validate high-bandwidth links for large-scale AI systems. You will define, model, and qualify interconnect solutions across copper and optical technologies for next-generation AI inference and training clusters. 

This role is on-site in Santa Clara, CA, Austin, TX, or Toronto, Canada.

We welcome candidates at various experience levels. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting

Who You Are

• An experienced electrical engineer with a Bachelor’s or Master’s in Electrical Engineering.
• 5+ years working on high-speed communications (100G–1.6T), including signal integrity, channels, and links.
• Comfortable building and owning link and channel budgets and making clear tradeoffs between reach, loss, BER, and margin.
• Hands-on with SI tools and lab equipment such as Keysight ADS, VNAs, TDRs, BERTs, and protocol analyzers.
• Familiar with cable specification and testing, as well as accelerated life testing, mating life, and failure analysis.
• Able to collaborate across hardware, systems, and manufacturing teams; manufacturing/DFM/DTM experience is a plus.

What We Need

• Define and specify high-speed interconnect architectures between systems within large AI clusters.
• Develop requirements, validation plans, and test strategies for passive and active copper cables and optical transceivers at 100G, 400G, 800G, and 1.6T.
• Document topologies, routing assumptions, and cable requirements for internal and customer-facing clusters.
• Perform link and channel budget analysis, including loss, jitter, eye margin, and BER considerations across PVT and aging.
• Lead and execute qualification and reliability testing, including accelerated life testing, mating life, and failure analysis for interconnect components.
• Interface with key industry suppliers, track their roadmaps, and align Tenstorrent’s system designs to future interconnect capabilities.

What You Will Learn

• How to design and validate interconnects for large-scale AI training and inference clusters, spanning multiple generations of Tenstorrent silicon and systems.
• Practical methodologies for closing SI margins at cutting-edge speeds (up to 1.6T) across diverse media (backplane, copper cable, optics).
• How to translate supplier roadmaps and standards into concrete system requirements and deployment constraints for real customer workloads.
• End-to-end exposure to AI system architecture, from rack-level topology choices down to connector, cable, and transceiver details, in collaboration with world-class AI hardware and systems teams.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

The Hardware team at Hudson River Trading (HRT) creates high performance compute engines using FPGA and ASIC technology to drive low latency trading decisions on global markets. We build custom solutions across the spectrum of speed and smarts: from bespoke circuits to world-class machine learning accelerators.

These high performance designs require even higher performance verification. We are looking for experienced Design Verification (DV) engineers who are skilled at writing testbenches and building verification environments to exercise complex HDL. Our ideal candidate is not only an ace tester, but a practicing toolsmith. You know the EDA landscape and want to be part of a team actively working to rethink, redesign, and surpass the status quo. For example, members of our team are active maintainers of popular open source projects such as Slang, Verilator, and Cocotb.

FPGA and ASIC verification is part of an innovative, growing team at HRT which is integral to the success of our trading. You can expect to always be challenged by the ever-changing financial markets as you work to ensure correctness and robustness of our critical hardware in an extremely fast-paced, real-time environment. No financial experience is necessary.

Responsibilities

• Creating testbenches and tests for our hardware platform, leveraging a hybrid open-source/proprietary, highly flexible environment
• Writing detailed verification plans
• Quickly root-cause RTL bugs
• Collaborating directly with designers for rapid bringup of new projects and debugging of existing designs
• Managing test suites and continuous integration infrastructure
• Developing and improving open-source and internal tools

Qualifications 

• Superb debug and analytical skills 
• Professional experience (2+ years) in RTL functional verification for FPGA or ASIC
• Experience with code and functional coverage collection/analysis
• Experience with SystemVerilog and industry-standard frameworks such as UVM
• Experience with Python
• Comfortable in a Linux environment
• Familiarity with Verilator and/or Cocotb preferred
• C++ experience is a plus
• A bachelor’s degree in computer science, electrical engineering, or a related field

The estimated base salary range for this position is 175,000 to 250,000 USD per year (or local equivalent). The base pay offered may vary depending on multiple individualized factors, including location, job-related knowledge, skills, and experience. This role will also be eligible for discretionary performance-based bonuses and a competitive benefits package.

The Hardware team at Hudson River Trading (HRT) creates high performance compute engines using FPGA and ASIC technology to drive low latency trading decisions on global markets. We build custom solutions across the spectrum of speed and smarts: from bespoke circuits to world-class machine learning accelerators.

FPGAs and ASICs are critical pieces of our technology stack. We are looking for talented hardware developers to architect and design complex systems on a highly collaborative global team. In this role, you'll identify efficient ways to perform on-the-fly transformations of market data and implement models with complex data structures in RTL. Deep knowledge of SystemVerilog, FPGA internals and/or ASIC primitives, computer architecture, and vendor tool suites are essential to succeeding in this role. Expertise in networking protocols, CPU design, and/or machine learning accelerators is a big plus. No financial experience is necessary.

Responsibilities

• Collaborate with a cross-functional team to develop and deploy custom FPGA and/or ASIC solutions for a wide range of trading applications
• Investigate new technologies and tools
• Contribute to a nimble hardware development tech stack

Qualifications

• Ability to describe hardware designs at a high level, low level, or anywhere in between
• Brilliant design, optimization, debugging and problem solving skills
• Professional experience (2+ years) in RTL design for FPGA or ASIC
• Expert SystemVerilog development skills with a thorough understanding of the language 
• Expert on low level FPGA or ASIC architectures, with a deep understanding of what makes them "tick"
• Skilled in network communications, processing pipelines, and/or machine learning
• Working knowledge of Python and/or C++
• Comfortable in a Linux environment
• Strong verification experience
• Familiarity with AMD Vivado is a plus
• A bachelor’s degree in computer science, electrical engineering, or a related field

This job is accepting ongoing applications and there is no application deadline.

The estimated base salary range for this position is 200,000 to 300,000 USD per year (or local equivalent). The base pay offered may vary depending on multiple individualized factors, including location, job-related knowledge, skills, and experience.

This role will also be eligible for discretionary performance-based bonuses and a competitive benefits package which includes medical, dental, vision, basic life insurance, and enrollment in our company’s retirement savings plans. Employees will receive sick and parental leave, as well as other paid time off (including 20 vacation days and 10 paid holidays in the US). Please note that benefits and time off policies will vary across non-US locations.

In any materials you submit, you may redact or remove age-identifying information such as age, date of birth, or dates of school attendance or graduation. You will not be penalized for redacting or removing this information.

JOB SUMMARY

We are seeking a highly skilled and experienced Staff Compute Engineer to lead the design and implementation of the next-generation compute solution for our humanoid robot platform. In this pivotal role, you will be the technical lead responsible for architecting a compute solution that meets our most demanding requirements for real-time performance, sensor bandwidth, and, most critically, functional safety.

ESSENTIAL DUTIES AND RESPONSIBILITIES or KEY ACCOUNTABILITIES

• Lead the architectural design of the robot's next-generation compute solution, from high-level system architecture to component-level selection.
• Define and validate compute requirements based on the needs of complex robotics algorithms, including motion control, perception, and AI tasks.
• Develop a robust and scalable solution capable of handling high-bandwidth data from a wide array of sensors
• Design for functional safety from the ground up, implementing redundant systems, fail-safe mechanisms, and diagnostic features to meet or exceed industry safety standards.
• Collaborate closely with cross-functional teams, including software, electrical, and systems engineers, to ensure seamless integration of the compute solution with the overall robot platform.
• Conduct performance benchmarking and power analysis to optimize the compute stack for maximum efficiency and thermal management.
• Design, simulate, implement, and test multi-layer high-speed PCBs for integration of advanced System-on-Modules (SoMs) like NVIDIA Orin.
• Lead efforts in high-speed signal integrity (SI) and power integrity (PI) analysis, modeling, and validation.
• Knowledge of compute and processor power requirements, power trees, PMICs, and power sequencing.
• Drive the selection and qualification of critical components, including SoMs, memory, storage (NVMe/eMMC), high-speed interconnects, and peripheral interfaces.
• Develop comprehensive validation and test plans (DVT/PVT), design necessary test fixtures, and execute rigorous testing to confirm compliance with performance specifications and regulatory standards (e.g., FCC, CE).
• Stay abreast of the latest advancements in embedded systems, real-time operating systems (RTOS), and robotics compute hardware to inform future design decisions.
• Own the entire lifecycle of complex compute hardware systems, from initial concept and architecture definition through design, prototyping, validation, production release, and ongoing support.
• Act as a technical leader and mentor within the electrical engineering team, guiding junior and senior engineers on best practices for complex hardware design and troubleshooting.

SKILLS AND REQUIREMENTS

• Proven experience in architecting and shipping complex, high-performance compute solutions for robotics, autonomous systems, or similar applications.
• Deep understanding of functional safety principles and standards (e.g. IEC 61508) and experience with safety-critical design.
• Expertise in a variety of compute platforms, including but not limited to, NVIDIA Jetson, Intel, and other high-performance embedded systems.
• Strong knowledge of real-time operating systems (RTOS), multi-core processing, and communication protocols (e.g., Ethernet, CAN).
• Experience with sensor bandwidth management and high-speed data transfer.
• Excellent problem-solving skills and a collaborative approach to engineering.
• Experience with humanoid robotics is a significant plus.

EDUCATION and/or EXPERIENCE

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field; Master's or Ph.D. preferred.
• 10+ years of experience in embedded systems or robotics compute design.

PHYSICAL REQUIREMENTS: 

• Prolonged periods of sitting at a desk and working on a computer 
• Must be able to lift 15 pounds at times 
• Vision to read printed materials and a computer screen 
• Hearing and speech to communicate