This role is for one of Weekday’s clients

Experience: 3 to 7 years
Location: Bengaluru
JobType: full-time

Role and Responsibilities:
Must be able to do characterization using Liberate/Primelib tools and understand the issues , failure fixes and QA of liberty.

Requirements

Skill Requirements:

• Experience and understanding of standard cell library design simulation.

• Understanding of concepts of balancing the cells, impact of width change on devices, issues in advanced technology nodes.
• Experience with at least one characterization tool (SiliconSmart/Liberate) for complete characterization of a library to generate the front end and back end views.
• Understanding of characterization methodologies for combinational, sequential cells and timing, power, capacitance models. Knowledge of cell characterization flows and methodologies, library verification and validation .
• Familiarity with circuit simulators, liberty syntax, library compiler, design compiler. Basic understanding of static timing analysis and synthesis. Scripting skills with perl, shell or python Setup simulation environment , write decks and perform design simulation.
• Write API/tcl coding for post processing liberty.
• Characterization and generation of front end and back end views for standard cell libraries Custom cell characterization setup and flows
•  Library verification and validation.
• Apache(Redhawk) and voltus view generation and QA.
• Automation for the QA checks, for small tasks in setting up the flows for characterization and QA Documentation of and recording the issues, debugs, solutions and new/enhanced work flows
• Mentor and enhance the skill set of junior team members
  

Good to have:

• 
  Automation expert
   

Must-have skills

Characterization, Liberate, Primelib