This role is for one of the Weekday's clients

Salary range: Rs 700000 - Rs 1800000 (ie INR 7-18 LPA)

Experience: 4+ yrs

Location: Hyderabad

Job Type: full-time

We are seeking a highly skilled Design for Test (DFT) Engineer to drive the implementation, validation, and optimization of DFT methodologies across complex SoC designs. This role involves working on scan insertion, ATPG generation, MBIST, LBIST, and boundary scan implementation at both RTL and gate levels to ensure high test coverage, manufacturability, and silicon quality.

The ideal candidate will collaborate closely with design, verification, synthesis, STA, and validation teams to develop robust DFT architectures and ensure seamless integration across the chip development lifecycle. This position offers an opportunity to work on advanced semiconductor technologies while contributing to the successful delivery of high-performance SoCs.

Requirements

Key Responsibilities

• Implement and integrate DFT methodologies including Scan, MBIST, LBIST, and Boundary Scan at hard macro and chip-top levels.
• Develop, configure, and validate DFT architectures to achieve optimal test coverage and silicon quality.
• Generate, analyze, and validate ATPG patterns through simulation and test coverage analysis.
• Perform RTL and gate-level validation of DFT implementations to ensure functional correctness and test readiness.
• Debug and resolve DFT-related issues across the design and implementation flow.
• Collaborate with cross-functional teams including Design, STA, Synthesis, LEC, Verification, Physical Design, and Validation teams.
• Support timing closure, design signoff, and manufacturing test readiness activities.
• Utilize industry-standard EDA tools for DFT implementation, pattern generation, and validation.
• Develop automation scripts and utilities to improve DFT productivity and flow efficiency.
• Contribute to DFT methodology improvements, best practices, and process optimization initiatives.

What Makes You a Great Fit

• Strong hands-on experience in Design for Test (DFT) methodologies and implementation.
• Proven expertise in Scan Insertion, ATPG, MBIST, LBIST, and Boundary Scan techniques.
• Experience validating DFT implementations at RTL and gate levels.
• Strong understanding of SoC architecture, digital design, and semiconductor design flows.
• Hands-on experience with leading EDA tools from Siemens, Synopsys, and/or Cadence.
• Proficiency in hardware description languages such as Verilog and VHDL.
• Strong scripting and programming skills using TCL, Perl, Python, C, or C++.
• Experience working with synthesis, STA, equivalence checking (LEC), verification, and physical implementation teams.
• Strong debugging, analytical, and problem-solving capabilities.
• Excellent communication and collaboration skills with the ability to work effectively in cross-functional engineering environments.
• A detail-oriented engineer passionate about delivering high-quality, testable, and reliable silicon solutions.