À propos de ce poste Sr. Staff Engineer - DFT chez Ambiq Micro, Inc.
Company Overview
Ambiq is on a mission to enable intelligence everywhere — powering the AI edge revolution with the world's lowest-power semiconductor solutions.
Built on our proprietary sub- and near-threshold technology, our chips deliver multi-fold improvements in energy efficiency without costly process scaling. Since 2010, we've shipped over 300 million units to customers building smarter wearables, medical devices, IoT products, and AI-powered edge applications.
Our cross-functional teams span design, research, development, production, marketing, sales, and operations across Austin, Hsinchu, Shanghai, Shenzhen, and Singapore. We move fast, tackle hard problems, and create space for people to grow through complex, meaningful work that shapes the future of technology.
We're looking for self-motivated, creative problem-solvers who are eager to push technological limits and make a real impact in energy efficiency.
At Ambiq, we live by five values: Innovate. Collaborate. Focus. Learn. Achieve.
If that's you, join us — the intelligence everywhere revolution starts here.
This role will be on-site 5 days a week in NW Austin.
Scope
We are seeking an experienced DFT (Design for Testability) Engineer to design, implement, and optimize test architectures for semiconductor products. This role involves collaborating with design, verification, and manufacturing teams to ensure products meet testability, yield, and quality objectives. The successful candidate will own the DFT strategy, develop test methodologies, and drive continuous improvement in test coverage and manufacturing efficiency.
Responsibilities
- Responsible for scan insertion, boundary scan, MBIST, and ATPG for ultra-low power SoC based on subthreshold operation using standard EDA tools.
- Develop and implement low-power DFT architecture and infrastructure.
- Generate structural test vectors, analyze, and improve coverage, test time, and test cost.
- Perform pre/post-layout scan and MBIST simulations.
- Work with designers on STA, physical, power, and logical issues related to DFT.
- Work with test engineers to bring up test vectors on silicon.
Qualifications
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BS/MS in Electrical Engineering, Electronics Engineering, or related field with 10+ years of DFT implementation experience.
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Hands-on expertise with Cadence Genus and Modus Compression for low-power scan insertion and ATPG pattern generation (required).
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Strong knowledge of DFT methodologies, including scan (stuck-at, at-speed, path-delay), scan compression, boundary scan, and MBIST.
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Proven experience defining and implementing hierarchical DFT architectures for complex SoCs.
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Expertise in Low-Power DFT, MBIST implementation, and memory test strategies.Experience generating, validating, and deploying memory repair patterns using the Tessent MBIST flow.
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Strong background in test coverage, test time analysis, and optimization for scan and MBIST patterns.
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Experience collaborating with test engineering teams to develop and bring up production test programs.
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Solid understanding of timing analysis and constraint development.
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Experience developing ATPG and MBIST testbenches and performing pre-/post-layout simulations.
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Experience analyzing ATE failure data and performing diagnosis using ATPG tools.
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Working knowledge of RTL design and verification.
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Proficiency in Tcl; experience with Perl and/or Python preferred.
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Experience with gate-level simulation (GLS) preferred.
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Self-motivated, detail-oriented engineer with strong problem-solving skills.
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Excellent verbal and written communication skills.
