In this role, you will tackle one of the most critical challenges in high-performance networking: Power.

This is an opportunity to join a high-impact team at the ground floor of a subject that is becoming a top priority. You won't be writing RTL; instead, you will have a holistic impact on our next-generation switches by estimating, measuring, and debugging power across the entire chip. This is a role for an engineer who wants to grow into a power expert within the world's most innovative silicon environment.

What you’ll be doing:

• Working with the design team to define power-aware architectural methodologies and drive power-conscious design decisions across the Switch architecture.

• Leading the research, development, and implementation of Switch micro-architecture power optimizations.

• Participating in silicon validation to debug power-related issues and define the chip power profile.

What we need to see:

• B.Sc. in Electrical Engineering or Computer Engineering

• 3–8 years in digital design or a related hardware field. We are looking for someone with a solid foundation who is ready to grow with us.

• This role thrives on collaboration. You must be able to communicate effectively across diverse teams and drive technical alignment.

• Ability to read and navigate complex SystemVerilog to analyze design behavior (no RTL writing required).