This role is for one of the Weekday's client

Min Experience: 3+ years

Location: Hyderabad, Telangana, India
JobType: full-time

We are looking for a highly motivated Analog Layout Engineer with 3–10 years of experience in custom analog and mixed-signal IC layout. The ideal candidate will have strong expertise in advanced CMOS technology nodes and will be responsible for developing high-quality, manufacturable layouts for complex analog and mixed-signal circuits. You will work closely with circuit designers, verification teams, and physical design engineers to deliver silicon-proven layouts that meet performance, reliability, and manufacturability requirements.

This role demands strong technical expertise in analog layout methodologies, excellent problem-solving abilities, and the capability to work collaboratively in a fast-paced semiconductor development environment.

Requirements

Key Responsibilities

• Design and develop custom analog and mixed-signal layouts for high-performance semiconductor products.
• Create optimized floorplans, device placement, routing, matching structures, shielding, guard rings, and power distribution for analog circuits.
• Perform physical verification, including DRC, LVS, ERC, and parasitic extraction, ensuring layouts are clean and tape-out ready.
• Optimize layouts for performance, area, reliability, and manufacturability while adhering to foundry design rules.
• Collaborate closely with analog circuit designers to achieve layout goals while minimizing parasitic effects.
• Work on complex analog and mixed-signal IPs including PLLs, Bandgap References, LDOs, ADCs, DACs, SERDES, HBM interfaces, IO cells, and related circuits.
• Analyze and resolve layout-related issues throughout the design cycle.
• Support design reviews, debugging, and silicon bring-up activities when required.
• Contribute to continuous improvement of layout methodologies, design automation, and best practices.
• Ensure timely completion of project milestones while maintaining high quality standards.

Required Skills & Qualifications

• 3–10 years of hands-on experience as an Analog Layout Engineer.
• Strong expertise in advanced CMOS technologies, including 2nm, 3nm, 5nm, 7nm, and 14nm process nodes.
• Solid understanding of analog layout techniques, including:
• Device matching
• Common centroid layout
• Interdigitation
• Symmetry
• Guard rings
• Shielding
• Well engineering
• Dummy structures
• Extensive experience with layout activities including floorplanning, placement, routing, DRC, LVS, and parasitic-aware optimization.
• Experience working on analog and mixed-signal blocks such as:
• PLL
• HBM
• Bandgap
• LDO
• ADC
• DAC
• SERDES
• IO circuits
• Proficiency with industry-standard EDA tools including:
• Cadence Virtuoso
• Virtuoso XL
• Virtuoso EXL
• IC12.1
• Calibre
• Strong understanding of physical and electrical layout effects and their impact on circuit performance.
• Good knowledge of reliability physics, including:
• Electromigration (EM)
• Electrostatic Discharge (ESD)
• Crosstalk
• Shielding
• Latch-up
• Deep sub-micron layout challenges
• Familiarity with semiconductor manufacturing processes and design rule constraints.
• Ability to independently debug complex layout issues and propose effective solutions.

Preferred Qualifications

• Experience across multiple semiconductor foundries and advanced process technologies.
• Exposure to high-speed, low-power, and high-performance analog design environments.
• Understanding of parasitic extraction and post-layout optimization techniques.
• Experience supporting tape-out and silicon validation activities.

Soft Skills

• Excellent analytical and problem-solving abilities.
• Strong communication and interpersonal skills.
• Ability to work effectively in cross-functional engineering teams.
• Self-driven, detail-oriented, and committed to delivering high-quality layouts within project timelines.
• Willingness to learn emerging semiconductor technologies and continuously improve technical expertise.

Must-Have Skills

• Analog Layout Engineer
• CMOS