M9 Solutions is seeking a Senior Systems and Test Integration Engineer to work on-site on a government contract for a client located in Scottsdale, AZ. Candidates must be eligible to obtain a TS/SCI clearance.

Responsibilities

• Designs, deploys, and integrates the payload emulation suite in tandem with the DevOps and Special Test Equipment groups to support National Security.
• Works directly with other engineering disciplines and program management in a cross-functional environment.
• Collaborates across engineering disciplines to define unit functionality, document interface requirements, and verify behavior on hardware.
• Independently leads FPGA implementation and troubleshooting efforts to meet program milestones.
• Works with test equipment including power supplies, multimeters, signal generators, signal/logic analyzers, and oscilloscopes.
• Manages task priorities, coordinates schedules, and communicates clear status to the team.
• Works in Linux (RHEL/Ubuntu) and Windows (Win11) operating systems.
• Uses the Microsoft tools suite.
• Performs integration and test of space flight hardware.
• Understands new technologies and works with vendors to stay on the cutting edge.

Required Skills and Qualifications

• Ability to obtain a TS/SCI security clearance.
• Bachelor’s degree in Electrical Engineering, or a related Science, Engineering, Technology, or Mathematics field and 5+ years of job-related experience, or a Master's degree plus 3 years of job-related experience.
• U.S. citizenship is required for this role.

Preferred Skills and Qualifications

• Direct Integration and Test experience with hi-reliability space payloads and/or vehicles.
• Experience with Automated Testing Environments or Special Test Equipment.
• Experience with failure review board processes, Failure Reporting and Corrective Action systems relevant to electronic systems for space.
• Experience with SRR/PDR/CDR/TRR/PSA evolution.
• 5+ years of FPGA development experience on Xilinx Ultrascale/Ultrascale+ devices.
• Proficiency in VHDL and/or SystemVerilog for RTL design, from microarchitecture definition through hardware integration.
• Experience designing FPGA firmware for high-speed serial interfaces including JESD204B (6+ Gbps), 10GbE, and SerDes.
• Proficiency in Xilinx Vivado toolchain - synthesis, implementation, timing closure, and ILA debug.
• Experience with SPI command/control interfaces, JTAG, and general-purpose digital I/O.
• Familiarity with FMC mezzanine card interfaces (VITA 57).
• Creative thinker with demonstrated success leading the integration and test life cycle.
• Collaborative team player eager to provide technical leadership and position others for success.
• Exceptional communication, presentation, and influence management skills, with notable record of securing buy-in on concepts and ideas.
• Experienced in the art of negotiation with ability to meet challenging customer requirements with win-win solutions.
• Demonstrated ability to interface with program management and customers.
• Commitment to ongoing professional development for self and others.
• Identifies opportunities to apply AI for continuous improvement and innovation.

GH 1043