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About this Principal Product Engineer - In-Design Physical Verification (DRC/FILL) role at Cadence Design Systems

Cadence Design Systems · Onsite · GYEONGGI-DO (Seoul)

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

The Product Engineering team works closely with customers, foundries, R&D, and application engineering teams to deliver leading-edge physical verification solutions for advanced semiconductor designs.


Responsibilities

  • Work closely with foundries and mutual customers to enable and support in-design Physical Verification (PV) solutions throughout the design implementation flow.
  • Serve as a technical expert in Physical Verification methodologies, including Design Rule Checking (DRC), Fill, and Layout Versus Schematic (LVS), with a focus on advanced node technologies.
  • Support customers in deploying, debugging, and optimizing in-design PV flows using Cadence implementation and verification technologies, including Innovus and Pegasus/PVS solutions.
  • Collaborate with foundries to validate and enhance Physical Verification rule decks and ensure seamless integration into customer design flows.
  • Provide technical support and guidance to customers for complex PV-related issues, working both onsite and remotely.
  • Interface closely with corporate R&D, field teams, foundries, and customers to identify product enhancements, resolve technical challenges, and improve overall solution quality.
  • Develop and drive efficient methodologies and automation flows that improve design productivity, verification coverage, and turnaround time.

Required Qualifications

  • 8+ years of professional experience with a Master's degree, or 10+ years with a Bachelor's degree.
  • Strong hands-on experience with digital implementation tools, preferably Cadence Innovus.
  • In-depth understanding of Physical Verification methodologies, including:DRC (Design Rule Checking) Fill LVS (Layout Versus Schematic)
  • Experience supporting physical implementation and signoff flows for advanced technology nodes (16nm/14nm FinFET and below).
  • Practical experience debugging and resolving Physical Verification issues in customer design environments.
  • Working knowledge of commercial Physical Verification tools such as:Pegasus / PVS Calibre ICV or equivalent solutions.
  • Strong communication and customer-facing skills, with the ability to work effectively across customers, foundries, R&D, and field teams.
  • Professional proficiency in spoken and written English.

Preferred Qualifications

  • Experience with foundry enablement and Physical Verification rule deck development or validation.
  • Experience in a design service or customer support organization.
  • Scripting or automation experience using Tcl, Python, Perl, or similar languages.
  • Familiarity with advanced-node implementation challenges, including DRC closure, fill strategies, and signoff verification methodologies.

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