Job Details:

Job Description:

📌 Role Overview 

We are seeking a Senior Technical Lead to drive the development, modeling, and validation of FPGA IP and simulation models within Altera Quartus Prime ecosystem. 

This is a hands-on leadership role — you will: 

• Define technical direction 
• Lead complex problem-solving 
• Actively contribute to design, modeling, and debugging 

You will play a critical role in improving IP quality, simulation accuracy, and engineering productivity, while mentoring engineers and shaping best practices. 

🎯 Key Responsibilities 

🔹 Technical Leadership (Hands-On) 

• Own technical direction for IP and simulation model 
• Lead design reviews, architecture discussions, and validation strategies 
• Dive deep into complex issues and personally drive resolution 

🔹 IP Development & Modeling 

• Design and implement FPGA IP (RTL/SystemVerilog/VHDL) 
• Develop high-fidelity simulation models:  
  • Behavioral 
  • Cycle-accurate 
• Ensure consistency between:  
  • Simulation models 
  • Hardware implementation 

🔹 Verification & Validation Strategy 

• Define and enforce robust verification methodologies:  
  • SystemVerilog 
  • Assertion-based verification 
• Oversee and contribute to:  
  • Testbench architecture 
  • Coverage strategy 
  • Regression systems 

🔹 Debug & Root Cause Leadership 

• Lead debugging of complex issues across:  
  • Simulation 
  • Fitter 
  • Timing analysis 
• Translate low-level issues into:  
  • Clear root cause 
  • Actionable fixes 

🔹 Quartus Flow Integration 

• Ensure seamless integration with:  
  • Compilation 
  • Fitter 
  • Timing closure 
• Identify and drive improvements in:  
  • Tool usability 
  • Debuggability (e.g., Fitter insights) 

🔹 Productivity & Automation 

• Champion engineering productivity improvements:  
  • Automation frameworks (Python, Tcl) 
  • Regression infrastructure 
  • AI-assisted workflows (where applicable) 

🔹 Mentorship & Team Development 

• Mentor engineers in:  
  • Debugging 
  • Design quality 
  • Verification practices 
• Raise overall team capability in:  
  • Root cause analysis 
  • System-level thinking

Qualifications:

🧠 Required Qualifications 

• Bachelor’s or Master’s in:  Electrical Engineering / Computer Engineering 
• 8–12+ years of experience in:  FPGA design, IP development, or verification 
• Strong hands-on expertise in:  RTL design (Verilog/SystemVerilog/VHDL)
• Simulation & verification 
• Deep experience with:  Altera Quartus Prime or equivalent FPGA toolchains 
• Proven ability to:  Debug complex system-level issues  and Lead technical initiatives 

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