EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.

• End-to-End DFT Strategy: Define and implement the complete DFT architecture as independent as possible, including Scan, MBIST, BSCAN, and Boundary Scan.
• Constraint Management: Take charge of DFT constraint development and management, ensuring seamless integration with synthesis and STA (Static Timing Analysis) teams.
• ATPG & Simulation: Generate high-coverage test patterns (Stuck-at, At-speed, Transition, Path Delay) and lead the verification of these patterns through timing-annotated simulations.
• AI-Specific Optimization: Implement advanced DFT techniques tailored for Edge AI architectures, such as high-bandwidth memory testing and low-power test modes.
• Hierarchical DFT: Design and execute hierarchical DFT flows to manage complexity in large-scale AI SOCs.
• Silicon Bring-up: Partner with the ATE (Automated Test Equipment) teams to debug patterns on silicon and drive yield improvement initiatives.

• The Experience: 9–10 years of hands-on experience in DFT, preferably with at least one full tape-out cycle in a lead or staff capacity.
• The Toolkit: Expert-level proficiency with industry-standard tools (e.g., Siemens Tessent, Synopsys DFTMAX/TetraMAX, or Cadence Genus/Modus).
• Technical Depth: Deep understanding of DFT-centric STA, power-aware DFT, and high-speed IO testing.
• Startup Mindset: You are comfortable wearing multiple hats. You don't wait for a manual; you build the manual.
• Edge AI Interest: A genuine interest in how AI hardware differs from general-purpose CPUs/GPUs.

• High Impact: In a startup, your decisions aren't buried in layers of bureaucracy; they are visible in the final silicon.
• Growth: You’ll be working alongside veterans from top-tier chipmakers, solving problems that haven't been solved yet.
• Ownership: We value "intrapreneurs"—engineers who treat the product like it’s their own.

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.

• End-to-End Ownership: Drive RTL-to-GDSII implementation, including floorplanning, placement, CTS, routing, and physical verification (LVS/DRC/ERC).
• Performance Optimization: Execute high-performance design closure focusing on PPA (Power, Performance, Area) targets in advanced process nodes ( 3nm or below)
• Static Timing Analysis (STA): Perform comprehensive timing closure, including signal integrity, crosstalk analysis, and CPPR (Common Path Pessimism Removal) optimization.
• Power Integrity: Conduct IR-drop analysis (Static/Dynamic) and EM (Electromigration) checks to ensure robust power delivery.
• Innovation: Develop and integrate AI/ML-based automation scripts to optimize the physical design flow and reduce turnaround time.

• Education: B.Tech/M.Tech in Electrical/Electronics Engineering from a Top Tier University.
• Experience: 2–4 years of hands-on experience in Physical Design within the semiconductor industry.
• Tool Expertise: Expert-level proficiency in industry-standard tools (Preferred Innovus).
• Technical Depth: Strong understanding of multi-corner multi-mode (MCMM) closure, low-power design techniques (UPF/CPF), and physical verification.
• Mindset: A proven "go-getter" who is diligent, detail-oriented, and capable of taking complete ownership of blocks under tight deadlines.
• The "Plus": Proficiency in Python/Tcl and experience using AI/ML models for EDA tool automation or predictive PPA analysis.
• Location: Bangalore

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.

Senior Emulation Engineer

Location: India - Remote

Job Description:

At EnCharge AI, we are building the next generation of AI compute silicon — purpose-built

for high-performance, low-power, and scalable AI inference. As an Emulation Engineer, you

will play a critical role in validating complex AI accelerator architectures on emulation

platforms before tape-out. This position is ideal for someone passionate about bridging the

gap between hardware and software in fast-paced, deep tech environments.

Responsibilities:

• Set up and maintain Siemens Veloce emulation and prototyping platforms

• Adapt SoC designs for Emulation and Prototyping

• Develop and debug emulation testbenches and system-level environments

• Support pre-silicon validation, power/performance analysis, and early software bring-up. Participate in silicon bring-up and validation.

• Collaborate with design and verification teams to isolate design issues and accelerate debug.

• Optimize performance of the emulation workloads and reduce turnaround time.

• Work with firmware/software teams to enable use of emulators for OS and driver testing.

Required Background:

• BS/MS/Ph.D. in EE, CS, or related field with 7+ years of SoC design experience.

• Experience with emulation platforms (Veloce, Palladium, or ZeBu) and FPGA-based prototyping systems (proFPGA, HAPS, or Protium)

• Experience with emulating high speed I/O interfaces such as PCIe and UCIe and memory technologies such as LPDDR and HBM

• Solid understanding of digital design, RTL (Verilog/SystemVerilog), and SoC architecture.

• Proficiency in hardware debug tools, waveform viewers, and logic analyzers

• Scripting skills (e.g., Python, Tcl, Perl) for automation and infrastructure development

• Familiarity with UVM, simulation, and testbench environments. SystemVerilog and UVM-based verification experience a plus

• Hand-on software development experience with C/C++ is a plus

About EnCharge AI: 

EnCharge AI is building the next generation AI platform. Our novel in-memory-computing architecture delivers a 10x step-function improvement in compute energy efficiency and performance for AI inference workloads. As the demands of artificial intelligence move beyond today's models, we believe fundamental underlying infrastructure must evolve. We are an experienced team of AI researchers, silicon & systems engineers, and architects backed by leading investors, poised to become the essential platform for the next wave of AI innovation. 

The Opportunity: 

Video generation represents one of the most compute-intensive frontiers in AI—and one of the most promising applications for our hardware's energy efficiency advantages. We're building a vertically-integrated video generation stack that will showcase the transformative potential of our silicon while delivering real value to customers today. 

We are seeking a Software Engineer to build the infrastructure and applications that bring our video generation capabilities to market. You'll build the serving stack, customer-facing APIs, and develop agentic systems that demonstrate what's possible when video generation meets energy-efficient hardware. 

This is a foundational role. You won't be inheriting a mature codebase—you'll be architecting production systems from scratch, making critical technical decisions, and building software that directly enables our go-to-market motion. 

Key Responsibilities: 

• Inference & Serving Infrastructure: Design and build scalable serving infrastructure for video generation models (Wan, LTX-Video, Flux, and beyond). Own latency, throughput, reliability, and cost optimization. 

• API & Platform Development: Build robust APIs and SDKs that enable customers and partners to integrate video generation into their products. Design abstractions that balance flexibility with ease-of-use. 

• Video Applications & Demos: Develop compelling demo applications that showcase our platform's capabilities—interactive experiences, batch processing workflows, and vertical-specific solutions that support the GTM team. 

• Agentic Workflows: Build agentic systems that leverage video generation as a core capability—autonomous video editing pipelines, multi-step generation workflows, and tool-use patterns that extend what's possible with video AI. 

• Production Operations: Establish monitoring, observability, and deployment practices for video generation workloads. Ensure systems are reliable, debuggable, and ready for customer-facing use. 

Qualifications: 

• 5+ years of software engineering experience, with a focus on backend systems or ML infrastructure 

• Strong fundamentals in Python and at least one systems language (Go, Rust, C++) 

• Experience building and operating production APIs and serving systems 

• Familiarity with ML inference pipelines (model serving, GPU workloads, batching strategies) 

• Comfort working in fast-moving, ambiguous environments where you define the roadmap 

• Strong product instincts—you think about how software will be used, not just how it works 

Nice to Have: 

• Experience with video processing pipelines or media infrastructure 

• Background building agentic systems or multi-step AI workflows 

• Familiarity with diffusion models or generative AI systems 

• Experience with Kubernetes, Ray, or other orchestration frameworks 

• Track record shipping developer tools or APIs 

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.

• Timing Convergence Leadership: Drive full-chip SOC timing closure across all corners and modes (func, shift, capture, etc.).
• Cross-Functional Coordination: Partner with Architecture to validate timing feasibility, RTL to optimize logic structures, and DFT to streamline test-mode timing.
• Left-Shift Strategy: Proactively identify and resolve structural timing issues, congestion, and high-latency paths early in the RTL/Synthesis phase to ensure predictable physical design execution.
• Advanced Analysis: Perform complex timing tasks including CPPR/CRPR analysis, NoC (Network-on-Chip) timing, and constraint validation (SDC).
• Automation & Agility: Architect and build sophisticated automation utilities (Tcl, Python, Perl) to accelerate timing sign-off, reduce manual audits, and improve schedule agility.
• PPA Optimization: Drive best-in-class PPA by guiding physical design teams on floorplanning, clock tree synthesis (CTS) strategies, and placement optimizations.

• Experience: 9 to 14 years of hands-on experience in STA and Timing Closure on advanced process nodes (7nm, 5nm, or below).
• Critical Thinking: Proven ability to debug complex timing violations, identify root causes (e.g., data-to-clock skew, crosstalk), and propose architectural or physical solutions.
• Technical Mastery: * Expertise in industry-standard sign-off tools (e.g., PrimeTime, Tempus). Preferable Tempus tool.
• Deep understanding of Multi-Mode Multi-Corner (MMMC) challenges and Hierarchical vs. Flat timing closure.
• Proficiency in SDC/CDC constraints.
• Soft Skills: Strong leadership presence with the ability to influence cross-functional teams and drive execution in a fast-paced environment.
• Education: B.Tech/M.Tech in Electrical/Electronics Engineering or a related field.

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.

Staff/Senior Staff Physical Design Floorplan & PDN Lead

Experience: 10–14 Years

Location:  Bangalore/2 days to work

Department: RTL-to-GDSII / Physical Implementation

Role Overview

We are seeking a high-caliber Staff or Senior Staff Physical Design Engineer with a specialized mastery of Floorplanning and Power Delivery Network (PDN) design. You won’t just be pushing buttons; you will be the architectural bridge between RTL/Systems and the final GDSII. This role requires a visionary who understands how a single floorplan decision ripples through the entire PPA (Power, Performance, Area) spectrum.

As a technical lead, you will own the chip-top floorplan for complex, large-scale SoCs or Sub-chips, driving strategies that balance aggressive performance targets with robust power integrity.

Key Responsibilities

• Architectural Floorplanning: Lead chip-level floorplanning, including macro placement, pin assignment, and partition definition for multi-million gate designs.
• Strategic PDN Design: Architect and implement complex Power Delivery Networks. You will define the metal stack usage and grid density to support high-performance cores while minimizing routing congestion.
• EMIR Mastery: Perform exhaustive IR-drop (Static/Dynamic) and Electromigration (EM) analysis. You must be able to diagnose root causes and propose architectural or physical fixes that don't compromise timing.
• Cross-Functional PPA Trade-offs: Collaborate directly with RTL and Architecture teams. You will use "Design Thinking" to influence the micro-architecture, suggesting changes to bus widths, pipeline stages, or memory configurations to optimize physical outcomes. 
• Methodology Development: Establish best practices and automated flows for floorplanning and PDN synthesis to be used by the wider implementation team.

Technical Requirements

• Core Experience: 10+ years in Physical Design with a proven track record of multiple successful tape-outs at advanced nodes (7nm, 5nm, or 3nm).
• PDN Expertise:Ability to model complex power-up sequences and multi-voltage domains.
• Floorplanning Savvy: Deep proficiency in hierarchical physical design and top-level integration using industry-standard tools (Innovus or IC Compiler II).
• Analysis Skills: Strong understanding of thermal-aware PDN and the physical implications of high-current density paths.
• Scripting: Advanced proficiency in Tcl, Python, or Perl to automate complex floorplanning tasks and data analysis.

Behavioral Attributes

• Critical Thinker: You don't just follow a recipe. You question constraints and look for "hidden" PPA gains.
• Design Thinking: Ability to empathize with the challenges of upstream (RTL) and downstream (Sign-off) teams to create a holistic solution.
• Influence: You can articulate technical trade-offs to stakeholders, 

Education

• B.Tech/M.Tech in Electrical/Electronic Engineering or equivalent.

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.

• Full-Flow Ownership: Lead the implementation of massive, high-speed blocks/SoCs from Synthesis through Sign-off using the Cadence Digital Suite.
• PPA Optimization: Push the theoretical limits of the PDK and tools. You will analyze and optimize the interplay between library cells, metal stacks, and tool engines to squeeze out every millivolt and picosecond.
• Methodology & Scalability: Build and refine a "Push-Button" style execution methodology that is robust, repeatable, and minimizes manual "human-in-the-loop" iterations.
• Cross-Functional "Left-Shift": Collaborate with RTL, Architecture, and DFT teams to influence design decisions early. You will drive a holistic approach where physical constraints inform the architecture, not just react to it.
• Bottleneck Elimination: Identify "drag" in the execution pipeline—whether it’s runtime, convergence issues, or tool limitations—and architect automated solutions to bypass them.

• Holistic Thinking: You look at the "Big Picture." You solve timing by fixing the floorplan or the RTL/ARCH
• Influence & Rapport: You can build strong technical bridges with Front-End, Foundry, and EDA vendors to align on a unified execution strategy.
• Critical Thinking: You operate on first principles. You don't just follow a vendor's "Best Practices" if they don't make sense for our specific architecture.
• Mentorship: You act as a force multiplier, elevating the technical competence of the entire PD team.

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.

We are looking for a visionary Principal Engineer to spearhead Encharge AI Timing leadership role.

This isn't just an execution role; we need a technical trailblazer who can navigate the complexities of advanced process nodes (2nm/3nm and beyond) while fostering a culture of innovation and rigorous critical thinking.

As the India Timing Lead, you will bridge the gap between architectural intent and silicon reality, ensuring our high-performance designs meet the most stringent timing, power, and reliability targets.

Key Responsibilities

• Technical Leadership: Drive the STA strategy for complex SoC and IP designs
• Innovation & Methodology: Develop and deploy "out-of-the-box" solutions for timing closure. This includes defining sign-off margins, variation modeling (POCV/LVF), and managing multi-corner multi-mode (MCMM) scenarios.
• Execution Excellence: Lead the team through full-cycle STA, from initial constraints validation to final GDS sign-off.
• Cadence Tempus Expert: Act as the primary subject matter expert for Cadence Tempus, optimizing tool flows for distributed processing, ECO generation, and power-aware timing analysis.
• Cross-Functional Collaboration: Partner with RTL, Synthesis, and Physical Design teams to influence floorplanning and clock tree synthesis (CTS) strategies for timing-friendly layouts.
• Mentorship: Elevate the technical caliber of the India team through active code reviews, white-boarding sessions, and fostering a "first-principles" approach to problem-solving.

Required Skills & Expertise

Mindset & Qualifications

• Critical Thinker: You don't just follow a checklist; you challenge existing flows to find efficiencies and hidden risks.
• Leadership Presence: 14+ years of experience in VLSI, with a clear track record of leading high-impact teams in India.
• Education: B.Tech/M.Tech in Electrical/Electronic Engineering or a related field.
• Communication: Ability to distill complex technical hurdles into actionable insights for global stakeholders.

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.

Job Description: Lead DFT Engineer (Edge Computing)
Developing silicon for Edge Computing isn't just about speed; it’s about balancing high-performance data processing with extreme power efficiency and reliability in remote environments.

As the Design for Test (DFT) Lead, you will be the architect of our testing strategy, ensuring our data center chips are flawlessly manufacturable and resilient enough for edge deployment.

Key Responsibilities
Architectural Leadership: Define and implement the end-to-end DFT architecture for complex SoCs, including Hierarchical DFT, Scan compression, Boundary Scan and MBIST.

Edge-Specific Reliability: Develop strategies for In-System Test (IST) and power-on self-test (POST) to ensure chip health in remote edge data centers.

Implementation & Flow: Oversee scan insertion, ATPG (Stuck-at, Transition, Path Delay), and Memory/Logic BIST.

Cross-Functional Synergy: Collaborate with Design, Physical Design, and Yield teams to ensure high test coverage while minimizing area overhead and power impact as well as timing analysis.

Post-Silicon Validation: Lead the bring-up and debug phase on ATE (Automated Test Equipment) to root-cause silicon failures and optimize test time.

Technical Requirements
Experience: 12+ years in DFT, with at least 2 years in a leadership or principal role.

Tools: Mastery of industry-standard tools (e.g., Synopsys TestMAX, Siemens/Mentor Tessent, or Cadence Modus).

Memory & Logic Test: Deep expertise in MBIST (Memory Built-In Self-Test) with repair capabilities, SCAN, IJTAG (IEEE 1687) and boundary scan (IEEE 1149.1/6).

Advanced Nodes: Proven track record with FinFET nodes (7nm, 5nm, or below).

Low Power: Experience managing DFT in multi-voltage/power-gated designs—crucial for edge efficiency.