EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.

• End-to-End DFT Strategy: Define and implement the complete DFT architecture as independent as possible, including Scan, MBIST, BSCAN, and Boundary Scan.
• Constraint Management: Take charge of DFT constraint development and management, ensuring seamless integration with synthesis and STA (Static Timing Analysis) teams.
• ATPG & Simulation: Generate high-coverage test patterns (Stuck-at, At-speed, Transition, Path Delay) and lead the verification of these patterns through timing-annotated simulations.
• AI-Specific Optimization: Implement advanced DFT techniques tailored for Edge AI architectures, such as high-bandwidth memory testing and low-power test modes.
• Hierarchical DFT: Design and execute hierarchical DFT flows to manage complexity in large-scale AI SOCs.
• Silicon Bring-up: Partner with the ATE (Automated Test Equipment) teams to debug patterns on silicon and drive yield improvement initiatives.

• The Experience: 9–10 years of hands-on experience in DFT, preferably with at least one full tape-out cycle in a lead or staff capacity.
• The Toolkit: Expert-level proficiency with industry-standard tools (e.g., Siemens Tessent, Synopsys DFTMAX/TetraMAX, or Cadence Genus/Modus).
• Technical Depth: Deep understanding of DFT-centric STA, power-aware DFT, and high-speed IO testing.
• Startup Mindset: You are comfortable wearing multiple hats. You don't wait for a manual; you build the manual.
• Edge AI Interest: A genuine interest in how AI hardware differs from general-purpose CPUs/GPUs.

• High Impact: In a startup, your decisions aren't buried in layers of bureaucracy; they are visible in the final silicon.
• Growth: You’ll be working alongside veterans from top-tier chipmakers, solving problems that haven't been solved yet.
• Ownership: We value "intrapreneurs"—engineers who treat the product like it’s their own.

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.

• End-to-End Ownership: Drive RTL-to-GDSII implementation, including floorplanning, placement, CTS, routing, and physical verification (LVS/DRC/ERC).
• Performance Optimization: Execute high-performance design closure focusing on PPA (Power, Performance, Area) targets in advanced process nodes ( 3nm or below)
• Static Timing Analysis (STA): Perform comprehensive timing closure, including signal integrity, crosstalk analysis, and CPPR (Common Path Pessimism Removal) optimization.
• Power Integrity: Conduct IR-drop analysis (Static/Dynamic) and EM (Electromigration) checks to ensure robust power delivery.
• Innovation: Develop and integrate AI/ML-based automation scripts to optimize the physical design flow and reduce turnaround time.

• Education: B.Tech/M.Tech in Electrical/Electronics Engineering from a Top Tier University.
• Experience: 2–4 years of hands-on experience in Physical Design within the semiconductor industry.
• Tool Expertise: Expert-level proficiency in industry-standard tools (Preferred Innovus).
• Technical Depth: Strong understanding of multi-corner multi-mode (MCMM) closure, low-power design techniques (UPF/CPF), and physical verification.
• Mindset: A proven "go-getter" who is diligent, detail-oriented, and capable of taking complete ownership of blocks under tight deadlines.
• The "Plus": Proficiency in Python/Tcl and experience using AI/ML models for EDA tool automation or predictive PPA analysis.
• Location: Bangalore

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.

About the Position:

The Silicon Operations Manager is responsible for driving operational activities from product definition and production ramp to sustained production. The individual will drive new product introduction activities, operational readiness for production and product lifecycle management. The silicon Operations Manager will be responsible for development, qualification and manufacturing ramp up of the company’s silicon products. The Silicon Operations Manager will report to the COO.

Responsibilities:

• Coordinate transitioning tests from the lab environment to the production environment
• Develop, debug, qualify, and deploy test programs to meet and exceed evolving customer needs and expectations
• Drive yield optimization activities and improvements
• Control the company’s RMA procedures and process.
• Work with marketing teams to provide a first line of defense for yield loss, RMA and customer returns.
• Drive failure analysis activities, investigating and solving complex issues in a fast-paced test department.
• Designing experiments and analyzing data to root cause and debug product failures
• Provide primary interface between the company and external semiconductor vendors (OSATs, foundries etc.)
• Lead cross-functional teams in operations, engineering, and quality assurance to meet production targets and KPIs.
• Collaborate with Supply Chain and Planning to develop and execute efficient production schedules based on customer demand and inventory goals.
• Develop, manage, and execute qualification activities, including prototyping parts, engineering samples and qualification builds.
• Coordinate Supply Chain Planning, Procurement and Sales Operations to support product development and manufacturing ramp‑up.
• Oversee Bill of Materials (BOM) accuracy and SKU management
• Maintain and update internal systems to reflect NPI/engineering demand, assembly instructions, build requirements, and engineering sample plans.
• Lead continuous improvement initiatives to advance operational modeling, automation, and cost‑reduction opportunities.

Qualifications:

• 10+ years’ experience in Semiconductor and high-tech manufacturing
• Deep understanding of semiconductor manufacturing process from semiconductor manufacturing to production test.
• Strong background in semiconductor development and product lifecycle management.
• Experience with FMA activities and failure analysis in the lab and production test environments
• Experience in Semiconductor Parametric & Functional Test and Characterization
• Experience in manufacturing metrics and problem-solving in a manufacturing environment
• Excellent interpersonal skills, energetic, motivated, and self-driven
• Outstanding communication skills - both written and verbal
• Demonstrated ability to communicate well with all levels of the organization and experience in working with external constituencies
• Strong organizational skills; demonstrated ability to manage multiple tasks simultaneously, and able to react to shifting priorities to meet business needs
• Demonstrated ability to meet deadlines and commitments
• Familiar with 6-sigma, DOE, FMEA

The salary range for this position is $125,000 to $200,000 per year. Actual compensation offered will be determined based by factors as job-related knowledge, skills and experience.

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.

• Timing Convergence Leadership: Drive full-chip SOC timing closure across all corners and modes (func, shift, capture, etc.).
• Cross-Functional Coordination: Partner with Architecture to validate timing feasibility, RTL to optimize logic structures, and DFT to streamline test-mode timing.
• Left-Shift Strategy: Proactively identify and resolve structural timing issues, congestion, and high-latency paths early in the RTL/Synthesis phase to ensure predictable physical design execution.
• Advanced Analysis: Perform complex timing tasks including CPPR/CRPR analysis, NoC (Network-on-Chip) timing, and constraint validation (SDC).
• Automation & Agility: Architect and build sophisticated automation utilities (Tcl, Python, Perl) to accelerate timing sign-off, reduce manual audits, and improve schedule agility.
• PPA Optimization: Drive best-in-class PPA by guiding physical design teams on floorplanning, clock tree synthesis (CTS) strategies, and placement optimizations.

• Experience: 9 to 14 years of hands-on experience in STA and Timing Closure on advanced process nodes (7nm, 5nm, or below).
• Critical Thinking: Proven ability to debug complex timing violations, identify root causes (e.g., data-to-clock skew, crosstalk), and propose architectural or physical solutions.
• Technical Mastery: * Expertise in industry-standard sign-off tools (e.g., PrimeTime, Tempus). Preferable Tempus tool.
• Deep understanding of Multi-Mode Multi-Corner (MMMC) challenges and Hierarchical vs. Flat timing closure.
• Proficiency in SDC/CDC constraints.
• Soft Skills: Strong leadership presence with the ability to influence cross-functional teams and drive execution in a fast-paced environment.
• Education: B.Tech/M.Tech in Electrical/Electronics Engineering or a related field.

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.

Principal DFT Engineer

Job Description:
Developing silicon for AI Computing isn't just about speed; it’s about balancing high-performance data processing with extreme power efficiency and reliability in remote environments.

As a Principal DFT(Design for Test) Engineer, you will lead our testing strategy, ensuring the manufacturing quality, reliability, and test efficiency of complex, high-performance AI accelerators.

Key Responsibilities:
Architectural Leadership: Define and implement the end-to-end DFT architecture for complex SoCs, including Hierarchical DFT, Scan compression, Boundary Scan and MBIST.

Edge-Specific Reliability: Develop strategies for In-System Test (IST) and power-on self-test (POST) to ensure chip health in remote edge data centers.

Implementation & Flow: Oversee scan insertion, ATPG (Stuck-at, Transition, Path Delay), and Memory/Logic BIST.

Cross-Functional Synergy: Collaborate with Design, Physical Design, and Yield teams to ensure high test coverage while minimizing area overhead and power impact as well as timing analysis.

Post-Silicon Validation: Lead the bring-up and debug phase on ATE (Automated Test Equipment) to root-cause silicon failures and optimize test time.

Technical Requirements:
Experience: 10+ years in DFT, with at least 2 years in a leadership or principal role.

Tools: Mastery of industry-standard tools (e.g., Synopsys TestMAX, Siemens/Mentor Tessent, or Cadence Genus/Modus).

Memory & Logic Test: Deep expertise in MBIST (Memory Built-In Self-Test) with repair capabilities, SCAN, IJTAG (IEEE 1687) and boundary scan (IEEE 1149.1/6).

Advanced Nodes: Proven track record with FinFET nodes (7nm, 5nm, or below).

Low Power: Experience managing DFT in multi-voltage/power-gated designs—crucial for edge efficiency.

The salary range for this position is $180,000 to $220,000 per year. Actual compensation offered will be determined based by factors as job-related knowledge, skills and experience.

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.

About the Position:

Hardware Technical Writer (Part-time)

The Hardware Technical Writer will report to the Chief Operating Officer and is a Remote Virtual, 1099 contract position.

Responsibilities:

• Collaborate with internal Architecture, Analog and Digital Design Engineering Teams to gather information for technical documents
• Writing design specifications, user manuals, and datasheets for AI Hardware
• Reviewing and revising architecture specifications, conference papers, integration guides
• Produce Government reports, Integration Guides, SDK User Manuals
• Translates complex ASIC or VLSI concepts into clear and concise documentation for engineers and customers

Qualifications:

• 5+ years experience in Technical Writing
• Experience with writing technical design specifications, user manuals, and datasheets
• Experience in collaborating with Engineering teams to gather technical information
• Experience in Technical Writing for ASIC or VLSI teams
• Work experience in Technical Writing for Artificial Intelligence companies is a plus
• B.S. in Electrical Engineering or similar field
• Clear communication with engineers to ensure accuracy
• Experience in tools such as Markdown, LaTeX, Microsoft Word

This is a 1099 contractor role. With an estimated 10 hours a week scope. The pay range for this position is $50 to $55 USD per hour if located in US. Actual compensation offered will be determined based by factors as job-related knowledge, skills and experience.

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.

Staff/Senior Staff Physical Design Floorplan & PDN Lead

Experience: 10–14 Years

Location:  Bangalore/2 days to work

Department: RTL-to-GDSII / Physical Implementation

Role Overview

We are seeking a high-caliber Staff or Senior Staff Physical Design Engineer with a specialized mastery of Floorplanning and Power Delivery Network (PDN) design. You won’t just be pushing buttons; you will be the architectural bridge between RTL/Systems and the final GDSII. This role requires a visionary who understands how a single floorplan decision ripples through the entire PPA (Power, Performance, Area) spectrum.

As a technical lead, you will own the chip-top floorplan for complex, large-scale SoCs or Sub-chips, driving strategies that balance aggressive performance targets with robust power integrity.

Key Responsibilities

• Architectural Floorplanning: Lead chip-level floorplanning, including macro placement, pin assignment, and partition definition for multi-million gate designs.
• Strategic PDN Design: Architect and implement complex Power Delivery Networks. You will define the metal stack usage and grid density to support high-performance cores while minimizing routing congestion.
• EMIR Mastery: Perform exhaustive IR-drop (Static/Dynamic) and Electromigration (EM) analysis. You must be able to diagnose root causes and propose architectural or physical fixes that don't compromise timing.
• Cross-Functional PPA Trade-offs: Collaborate directly with RTL and Architecture teams. You will use "Design Thinking" to influence the micro-architecture, suggesting changes to bus widths, pipeline stages, or memory configurations to optimize physical outcomes. 
• Methodology Development: Establish best practices and automated flows for floorplanning and PDN synthesis to be used by the wider implementation team.

Technical Requirements

• Core Experience: 10+ years in Physical Design with a proven track record of multiple successful tape-outs at advanced nodes (7nm, 5nm, or 3nm).
• PDN Expertise:Ability to model complex power-up sequences and multi-voltage domains.
• Floorplanning Savvy: Deep proficiency in hierarchical physical design and top-level integration using industry-standard tools (Innovus or IC Compiler II).
• Analysis Skills: Strong understanding of thermal-aware PDN and the physical implications of high-current density paths.
• Scripting: Advanced proficiency in Tcl, Python, or Perl to automate complex floorplanning tasks and data analysis.

Behavioral Attributes

• Critical Thinker: You don't just follow a recipe. You question constraints and look for "hidden" PPA gains.
• Design Thinking: Ability to empathize with the challenges of upstream (RTL) and downstream (Sign-off) teams to create a holistic solution.
• Influence: You can articulate technical trade-offs to stakeholders, 

Education

• B.Tech/M.Tech in Electrical/Electronic Engineering or equivalent.

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.

• Full-Flow Ownership: Lead the implementation of massive, high-speed blocks/SoCs from Synthesis through Sign-off using the Cadence Digital Suite.
• PPA Optimization: Push the theoretical limits of the PDK and tools. You will analyze and optimize the interplay between library cells, metal stacks, and tool engines to squeeze out every millivolt and picosecond.
• Methodology & Scalability: Build and refine a "Push-Button" style execution methodology that is robust, repeatable, and minimizes manual "human-in-the-loop" iterations.
• Cross-Functional "Left-Shift": Collaborate with RTL, Architecture, and DFT teams to influence design decisions early. You will drive a holistic approach where physical constraints inform the architecture, not just react to it.
• Bottleneck Elimination: Identify "drag" in the execution pipeline—whether it’s runtime, convergence issues, or tool limitations—and architect automated solutions to bypass them.

• Holistic Thinking: You look at the "Big Picture." You solve timing by fixing the floorplan or the RTL/ARCH
• Influence & Rapport: You can build strong technical bridges with Front-End, Foundry, and EDA vendors to align on a unified execution strategy.
• Critical Thinking: You operate on first principles. You don't just follow a vendor's "Best Practices" if they don't make sense for our specific architecture.
• Mentorship: You act as a force multiplier, elevating the technical competence of the entire PD team.

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.

We are looking for a visionary Principal Engineer to spearhead Encharge AI Timing leadership role.

This isn't just an execution role; we need a technical trailblazer who can navigate the complexities of advanced process nodes (2nm/3nm and beyond) while fostering a culture of innovation and rigorous critical thinking.

As the India Timing Lead, you will bridge the gap between architectural intent and silicon reality, ensuring our high-performance designs meet the most stringent timing, power, and reliability targets.

Key Responsibilities

• Technical Leadership: Drive the STA strategy for complex SoC and IP designs
• Innovation & Methodology: Develop and deploy "out-of-the-box" solutions for timing closure. This includes defining sign-off margins, variation modeling (POCV/LVF), and managing multi-corner multi-mode (MCMM) scenarios.
• Execution Excellence: Lead the team through full-cycle STA, from initial constraints validation to final GDS sign-off.
• Cadence Tempus Expert: Act as the primary subject matter expert for Cadence Tempus, optimizing tool flows for distributed processing, ECO generation, and power-aware timing analysis.
• Cross-Functional Collaboration: Partner with RTL, Synthesis, and Physical Design teams to influence floorplanning and clock tree synthesis (CTS) strategies for timing-friendly layouts.
• Mentorship: Elevate the technical caliber of the India team through active code reviews, white-boarding sessions, and fostering a "first-principles" approach to problem-solving.

Required Skills & Expertise

Mindset & Qualifications

• Critical Thinker: You don't just follow a checklist; you challenge existing flows to find efficiencies and hidden risks.
• Leadership Presence: 14+ years of experience in VLSI, with a clear track record of leading high-impact teams in India.
• Education: B.Tech/M.Tech in Electrical/Electronic Engineering or a related field.
• Communication: Ability to distill complex technical hurdles into actionable insights for global stakeholders.

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.

Job Description: Lead DFT Engineer (Edge Computing)
Developing silicon for Edge Computing isn't just about speed; it’s about balancing high-performance data processing with extreme power efficiency and reliability in remote environments.

As the Design for Test (DFT) Lead, you will be the architect of our testing strategy, ensuring our data center chips are flawlessly manufacturable and resilient enough for edge deployment.

Key Responsibilities
Architectural Leadership: Define and implement the end-to-end DFT architecture for complex SoCs, including Hierarchical DFT, Scan compression, Boundary Scan and MBIST.

Edge-Specific Reliability: Develop strategies for In-System Test (IST) and power-on self-test (POST) to ensure chip health in remote edge data centers.

Implementation & Flow: Oversee scan insertion, ATPG (Stuck-at, Transition, Path Delay), and Memory/Logic BIST.

Cross-Functional Synergy: Collaborate with Design, Physical Design, and Yield teams to ensure high test coverage while minimizing area overhead and power impact as well as timing analysis.

Post-Silicon Validation: Lead the bring-up and debug phase on ATE (Automated Test Equipment) to root-cause silicon failures and optimize test time.

Technical Requirements
Experience: 12+ years in DFT, with at least 2 years in a leadership or principal role.

Tools: Mastery of industry-standard tools (e.g., Synopsys TestMAX, Siemens/Mentor Tessent, or Cadence Modus).

Memory & Logic Test: Deep expertise in MBIST (Memory Built-In Self-Test) with repair capabilities, SCAN, IJTAG (IEEE 1687) and boundary scan (IEEE 1149.1/6).

Advanced Nodes: Proven track record with FinFET nodes (7nm, 5nm, or below).

Low Power: Experience managing DFT in multi-voltage/power-gated designs—crucial for edge efficiency.

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.

About the Role

We are seeking a highly experienced Senior Physical Design Engineer with a strong background in chip-level implementation and EDA tools. The ideal candidate will have deep expertise in physical design, timing closure, and low-power design.

Qualifications

• 10+ years of experience in physical design (excluding other areas such as logic design or CAD).

• Strong understanding of EDA implementation for chip design, with hands-on experience in Cadence tools (must-have).

• Strong knowledge of timing concepts and timing closure techniques for chip design.

• Experience with both top-level and block-level physical design is required; experience with hierarchical floorplanning is a plus.

• Proficiency in low-power design concepts and debugging is necessary.

• Experience with EM/IR checks, debugging, and issue resolution, including power grid verification, is required.

• Strong scripting skills in TCL or Python for automation are important.

• Understanding of process concepts is needed for physical verification as part of routing tasks.

• Experience with physical design methodology and flow setup is preferred; this role will involve advanced flow evaluations.

• Additional experience in areas such as PDK management or foundry tapeout processes is a plus,