This role is for one of the Weekday's clients

Salary range: Rs 2000000 - Rs 4000000 (ie INR 20-40 LPA)

Experience: 5+ yrs

Location: Bengaluru, Karnataka, India

Job Type: Full-Time

We are seeking an experienced Static Timing Analysis (STA) Engineer to drive timing analysis, timing closure, and timing sign-off for complex ASIC and SoC designs across advanced technology nodes. This role is ideal for professionals with strong expertise in Synopsys PrimeTime, Cadence Tempus, MMMC analysis, and timing optimization who are passionate about delivering high-quality silicon for tape-out.

As an STA Engineer, you will work closely with RTL, Physical Design, DFT, Synthesis, and Verification teams to develop timing constraints, analyze timing reports, implement timing ECOs, and achieve timing closure throughout the design cycle. You will play a critical role in ensuring timing integrity, optimizing performance, and supporting successful silicon implementation.

Requirements

Key Responsibilities

• Perform block-level and full-chip Static Timing Analysis (STA) and timing sign-off for complex ASIC and SoC designs.
• Develop, validate, and maintain SDC timing constraints for multiple operating modes and process corners.
• Execute MMMC (Multi-Mode Multi-Corner) timing analysis and identify critical timing paths.
• Drive setup and hold timing closure by collaborating with Physical Design teams on optimization strategies.
• Analyze timing reports, implement timing ECOs, and support timing convergence throughout the implementation flow.
• Perform clock tree analysis, validate timing exceptions, and optimize clock uncertainty.
• Generate and validate SDF files to support Gate-Level Simulations (GLS).
• Support synthesis activities using Design Compiler or Fusion Compiler while ensuring timing objectives are met.
• Collaborate with RTL, DFT, Design, and Verification teams to resolve timing-related issues efficiently.
• Perform timing constraint validation along with Lint and CDC checks to ensure design quality.
• Support timing model generation and integration activities for IPs and SoC designs.
• Contribute to continuous improvement of timing methodologies, automation, and sign-off processes.

What Makes You a Great Fit

• Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, or a related discipline.
• 5+ years of hands-on experience in Static Timing Analysis (STA) for ASIC or SoC development.
• Strong expertise in Synopsys PrimeTime and/or Cadence Tempus.
• Proven experience with MMMC timing analysis, timing sign-off, and timing closure.
• Strong knowledge of SDC constraint development, debugging, and validation.
• Experience implementing setup and hold timing closure across advanced technology nodes.
• Hands-on experience with synthesis using Synopsys Design Compiler or Fusion Compiler.
• Good understanding of Clock Tree Synthesis (CTS), timing ECO implementation, and SDF generation.
• Familiarity with DFT concepts, Lint, CDC analysis, and Gate-Level Simulation support.
• Experience working on advanced process technologies such as 28nm, 16nm, 7nm, 5nm, 3nm, or FinFET nodes.
• Knowledge of scripting languages such as Tcl, Perl, Python, or Shell for automation is an advantage.
• Strong analytical, debugging, and problem-solving skills with excellent communication and collaboration abilities across cross-functional engineering teams.