This role is for one of the Weekday's clients

Min Experience: 8+ years

Location: Bengaluru
JobType: full-time

We are looking for an experienced RTL Design Engineer to join our semiconductor design team and contribute to the development of next-generation ASIC solutions. The ideal candidate will have extensive experience in RTL design, microarchitecture development, and digital logic implementation for complex System-on-Chip (SoC) designs. You will play a critical role in translating architectural specifications into high-quality RTL, ensuring design scalability, performance, power efficiency, and manufacturability.

This role requires close collaboration with architecture, verification, synthesis, physical design, DFT, and firmware teams throughout the ASIC development lifecycle. The ideal candidate is passionate about building reliable, high-performance digital hardware and has a strong understanding of modern ASIC design methodologies.

Requirements

Key Responsibilities

• Design and develop RTL for complex digital blocks using Verilog and SystemVerilog.
• Translate architectural specifications into efficient, synthesizable RTL implementations.
• Participate in microarchitecture definition and contribute to design reviews.
• Optimize designs for performance, area, power, and timing requirements.
• Collaborate with verification engineers to develop comprehensive verification plans and resolve functional issues.
• Work closely with synthesis, STA, DFT, and physical design teams to ensure smooth design implementation.
• Analyze simulation results, debug RTL issues, and implement robust design fixes.
• Review code, mentor junior engineers, and promote RTL coding best practices.
• Support IP integration and SoC-level design activities.
• Participate in design documentation, specification reviews, and technical discussions throughout the project lifecycle.
• Ensure compliance with ASIC development processes, coding standards, and quality guidelines.

Must-Have Skills

• Strong experience in ASIC Design with multiple successful tape-outs.
• Deep expertise in RTL development using Verilog and SystemVerilog.
• Strong understanding of digital design fundamentals, finite state machines, pipelining, clock domain crossing (CDC), reset strategies, and synchronization techniques.
• Experience with SoC architecture and IP integration.
• Strong knowledge of synthesis concepts, timing closure, and design optimization.
• Familiarity with simulation and debugging using industry-standard EDA tools.
• Excellent understanding of low-power design methodologies and ASIC design flows.
• Ability to interpret architecture specifications and convert them into efficient RTL implementations.
• Strong analytical, debugging, and problem-solving skills.
• Experience collaborating across cross-functional engineering teams.

Good-to-Have Skills

• Experience with Lint tools and methodologies for RTL quality improvement.
• Exposure to CDC analysis and formal verification.
• Knowledge of DFT concepts including scan insertion and ATPG.
• Familiarity with scripting using Python, Perl, or Tcl for design automation.
• Experience with FPGA prototyping.
• Understanding of AMBA protocols such as AXI, AHB, or APB.
• Exposure to low-power verification techniques including UPF.
• Experience with modern EDA tools from Synopsys, Cadence, or Siemens EDA.

Preferred Qualifications

• Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, or a related discipline.
• 8–20 years of hands-on experience in RTL design and ASIC development.
• Proven experience delivering complex ASIC or SoC projects from specification through tape-out.
• Strong communication skills and the ability to work effectively within global engineering teams.
• Experience mentoring engineers and driving technical excellence is highly desirable.