NXP’s Industrial & IoT Edge solutions range from the smallest MCUs to very high-performance processors to provide real-time insights and efficient automation when performance matters most. NXP’s advanced portfolio of edge processing solutions lets developers explore their most innovative ideas with confidence, enabling applications across the autonomous home, industrial automation, and personal electronics.

NXP is building new teams in Catania to create high impact micro-controllers (MCU) as part of NXP’s intelligent AI at the Edge. This team will include a wide range of engineering talent from analog to SOC digital design. Full product development local will product world class products at a world class pace. 

As a Junior Physical Design Engineer, you will learn, execute and support the RTL-to-GDSII physical implementation flow for complex SoC/MCU designs on advanced nodes. Working closely with experienced engineers, you will play an active role in meeting performance, power, and area targets.

Your Responsibilities.

• Support SOC-level floorplanning, power grid design, IO placement, Place & Route (P&R), Clock-Tree Synthesis (CTS) and physical verification (DRC, LVS, ERC, Antenna).
• Assist with tool setup, static timing analysis (STA), basic timing constraints management, IR-drop, and Electromigration (EM) analysis.
• Collaborate with RTL, DFT, and Analog design teams to facilitate smooth design hand-offs and integration.
• Maintain and extend automation scripts (TCL, Python, Perl) to improve flow efficiency and design analysis.
• Learn and apply state-of-the-art EDA tools and work with vendors to troubleshoot issues.

Your Profile.

• Bachelor’s or Master's degree in Electrical Engineering, Electronics Engineering, or related field.
• Solid understanding of digital design principles, semiconductor physics, and integrated circuit fundamentals.
• Familiarity with the basic IC design flow (from RTL concepts to GDSII layout).
• Understanding of basic timing analysis (setup/hold time), clock distribution, and low-power fundamentals (e.g., clock gating).
• Basic knowledge of scripting languages such as TCL, Python, and/or Perl.
• Excellent verbal and written communication skills in English.
• Fast learner with strong curiosity and passion for microelectronics and hardware development.
• Analytical mindset, structured, fact-based approach to problem-solving with attention to detail.
• Strong collaborative spirit with good communication skills for international teamwork.

Desirable skills/experience:

• Prior internship, university thesis, or hands-on projects involving Physical Design / Implementation or VLSI design.
• Familiarity with industry-standard EDA platforms: Synopsys (Fusion Compiler, ICC2, Formality) or Cadence (Innovus, Genus).
• Exposure to IR-drop analysis tools (e.g., Ansys RedHawk, Cadence Voltus).
• Basic knowledge of UPF/CPF low-power techniques or full-custom layout fundamentals.
• Exposure to AI/ML applications in EDA or microcontrollers.

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NXP is committed to equal pay for equal work and work of equal value and applies fair, consistent and transparent remuneration practices.

As of the date of this posting, the estimated gross annual base salary range for this position in Italy is between 31,200 € and 43,000 € annually. This range is intended as a guideline. Actual compensation may vary based on qualifications, experience, skills, and specific business or organizational needs. This position falls under the applicable National Collective Labour Agreement (Metalmeccanica Industria). Where relevant, the total compensation package may also include additional elements such as annual incentive opportunities and/or equity, along with a competitive benefits package.

More information about NXP in Italy...

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