Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

The Heterogeneous Integration Group (HIG) sits within Micron’s Technology and Products Group and is at the heart of our HBM innovation. We design and optimize industry‑leading HBM solutions that power AI, ML, and high‑performance computing platforms. By combining TSV technology, advanced IO architectures, and deep system‑level thinking, we deliver the highest bandwidth with the lowest power per bit in the industry.

As a Principal Engineer in HBM IO Design Architecture, you will be the technical authority for HBM IO circuits and PHY architecture. You will lead multi‑generation IO initiatives spanning TSV link definition, PHY circuit architecture, IO training features, and silicon validation. This role is critical to maintaining Micron’s leadership in HBM speed, power efficiency, and quality, and offers the opportunity to shape long‑term architectural direction across the organization.

Responsibilities:

• Define and own HBM IO and data path architecture across multiple product generations from pathfinding through tape‑out
• Architect and analyze TSV‑based HBM link schemes including topology, signaling strategy, and parasitic co‑design
• Define and drive HBM PHY IO training features to ensure robust PVT margin across product generations
• Architect high‑speed IO circuits for the HBM interface die targeting best‑in‑class bandwidth and power efficiency
• Establish IO and TSV design standards and drive alignment across design, product, package, and process teams

Minimum Qualifications:

• Bachelor’s degree in Electrical Engineering or equivalent experience
• 7+ years of hands‑on experience in memory or high‑speed IO design with proven silicon success
• Deep expertise in analog and mixed‑signal CMOS circuit design and simulation
• Strong experience with high‑speed IO architectures such as Rx/Tx, PLL, DLL, DCC, phase interpolators, or equalizers
• Excellent communication skills with the ability to influence technical direction across teams

Preferred Qualifications:

• Master’s degree or PhD in Electrical Engineering or related field
• 10+ years of experience in HBM, DRAM, or advanced memory interface design
• Patents, publications, or trade secrets in high‑speed IO, TSV interfaces, or IO training
• Experience with HBM, LPDDR, UCIe, or other JEDEC memory standards
• Demonstrated technical leadership across multi‑disciplinary, multi‑generation programs

As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future.  We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget.  Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave.  Additionally, Micron benefits include a robust paid time-off program and paid holidays.  For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits.

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.

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To learn more about Micron, please visit micron.com/careers

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