Role Overview

Astera Labs is seeking a Physical Design Engineering Manager to lead a team of physical design engineers at our Toronto site, driving the implementation of connectivity ASICs within our Signal Connectivity Group. This group is responsible for products that enable high-speed serial connectivity including PCIe retimers, Ethernet retimers, and signal conditioning solutions—deployed across the world's largest AI clusters and hyperscale data centers.

As an Physical Design Manager Engineering Manager, you will combine hands-on technical leadership with people management, owning physical design execution from RTL to GDSII while building and mentoring a high-performing team. You will drive floorplanning, place-and-route, timing closure, and sign-off for complex designs requiring deep understanding of high-speed physical layer interfaces and SerDes integration at TSMC advanced nodes. This role is fully on-site at our Toronto location.

Basic Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field; Master's preferred.
• 12+ years of experience in physical design implementation of complex SoCs at advanced nodes (7nm and below).
• 2+ years of experience leading teams or projects with demonstrated ability to mentor and develop engineers.
• Hands-on expertise across the physical design flow: synthesis, place-and-route, CTS, extraction, timing closure, EM-IR, DRC/LVS, and equivalence checking.
• Proficiency with Cadence Innovus and/or Synopsys Fusion Compiler/ICC2 and supporting toolchains.
• Strong scripting ability in Tcl, Python, and/or Perl.
• Professional attitude with the ability to prioritize a dynamic list of tasks, plan and prepare for customer meetings in advance, and work with minimal guidance.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind! 

Required Experience

• Build, lead, and mentor a physical design team, owning Physical Design execution and team development for Signal Connectivity Group products.
• Drive block and top-level physical design implementation from floorplan through tapeout for retimer and signal conditioning ASICs.
• Own floorplanning, macro placement, power grid design, clock tree synthesis, and place-and-route for complex blocks and full-chip designs.
• Drive timing closure at both block and full-chip levels, developing and maintaining timing constraints and signoff methodology.
• Ensure DRC/LVS/EM-IR closure and physical verification sign-off to foundry requirements.
• Integrate hard macros, high-speed SerDes, analog IP, and third-party IP blocks, ensuring seamless physical integration at block boundaries.
• Collaborate with RTL, DFT, STA, EMIR, and verification teams to drive design convergence from synthesis through sign-off.
• Work with IP vendors for both RTL and hard-macro integration, ensuring placement constraints and routing guidelines are met.
• Drive team execution, hiring, career development, and sprint planning for the Toronto PD team.
• Establish physical design best practices, flow improvements, and quality checks to scale execution across multiple concurrent programs.
• Coordinate with global PD teams (San Jose, Irvine, Bangalore) to ensure consistent methodology and design quality.
• Experience with Cadence and/or Synopsys physical design tools/flows.
• Familiarity and working knowledge of SystemVerilog/Verilog.

Preferred Experience

• Deep understanding of high-speed SerDes physical layer, including equalization, CDR, and signal integrity considerations impacting physical design.
• Experience with PCIe, Ethernet, or retimer/signal conditioning ASIC implementation.
• Knowledge of physical layer timing challenges specific to high-speed serial interfaces.
• Hands-on experience with UPF-based multi-voltage/multi-power-domain implementations.
• Familiarity with advanced packaging or multi-die integration and its impact on physical design.
• Experience with ECO methodologies and DFT-aware physical design.
• Knowledge of EMIR-aware implementation techniques and early-stage IR drop mitigation.
• Track record of building and scaling physical design teams through multiple tapeouts.
• Knowledge of agentic AI solutions for EDA automation.

Salary range is CAD $180,000 to $220,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives, and benefits.

Tenstorrent is seeking a highly skilled and experienced Engineer to lead post-silicon power characterization and correlation activities for cutting-edge semiconductor products. In this role, you will be responsible for developing and executing detailed power measurement strategies on silicon, correlating results with pre-silicon models, and driving improvements across power architecture, design, and modeling methodologies. You will serve as a key technical leader, interfacing across design, architecture, validation, and systems teams to ensure silicon meets power and performance specifications under all operating conditions.

This role is hybrid, based out of Toronto, ON or Austin, TX or Santa Clara, CA.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who you are

• A Principal-level engineer with 8+ years in silicon power analysis and characterization, and a Master’s or PhD in EE, CE, or related field.
• Deep understanding of digital and mixed-signal power domains, including DVFS, leakage vs. dynamic power, and power gating.
• Highly proficient in lab-based power measurement using oscilloscopes, current probes, power analyzers, and SMUs, plus Python/Perl/MATLAB for automation and analytics.
• A strong debugger and collaborator, comfortable driving cross-functional investigations and clearly communicating technical findings.

What we need

• Own the post-silicon power measurement strategy end-to-end across operating modes, voltages, frequencies, and workloads.
• Build and maintain lab infrastructure, automated workflows, and data analysis pipelines for high-fidelity, repeatable power characterization.
• Correlate silicon power data to pre-silicon models (RTL, gate-level, sign-off), drive root-cause analysis, and refine power estimation methodologies with design and modeling teams.
• Characterize power across PVT corners and work with bring-up/validation teams to develop test content, debug power anomalies, and ensure products meet power and performance specs.

What you will learn

• How state-of-the-art SoCs behave in real silicon across diverse workloads, system configurations, and operating conditions.
• How to influence power architecture, RTL design, and modeling flows by feeding silicon insights directly back into early design phases.
• Best practices for building scalable, automated post-silicon power infrastructures that support multiple products and generations.
• Advanced correlation, margining, and variability analysis techniques that deepen your expertise in both SoC-level power and system-level behavior.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is seeking an experienced Silicon Validation Engineer to validate and qualify our cutting-edge die-to-die (D2D) subsystem, AI, and Processor IP testchips for the rapidly growing chiplet ecosystem. You'll develop hardware infrastructure for validation platforms, perform comprehensive electrical characterization, and support customer silicon bring-up. If you’re passionate about hands-on silicon testing and want to help usher in the chiplet era of semiconductor products, join us.

This role is on-site, based out of Santa Clara, CA; or Toronto, Canada. 

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A hands-on engineer with 5+ years of silicon test and characterization experience in lab environments.
• Expert with oscilloscopes, BERTs, and test equipment who can independently debug complex validation challenges.
• Self-driven problem solver with strong EE fundamentals in both digital and analog circuit design.
• Excellent communicator who collaborates effectively with design teams and tracks progress meticulously.

What We Need

• BS/MS in Electrical Engineering with 5+ years of hands-on silicon validation using Keysight/Tektronix equipment.
• Proven experience with high-speed measurements (Tx jitter, Rx JTOL) and test automation scripting (Python, Perl, LabVIEW).
• Strong understanding of datacomm circuits (amplifiers, PLLs, equalizers) and signal integrity concepts.
• Track record of independently running validation tests and driving issue resolution with design teams.

What You Will Learn

• State-of-the-art die-to-die chiplet validation methodologies for next-generation semiconductor architectures.
• How to build and evolve hardware infrastructure for advanced D2D validation and demo platforms.
• Customer-facing silicon bring-up techniques and product qualification best practices.
• The opportunity to shape validation standards in the emerging chiplet ecosystem at a fast-moving startup.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Job Description

We are seeking a Technical Lead Digital Design Engineer with deep expertise in high-performance PCIE controller and bridge design, micro-architecture, RTL implementation, and IP integration. The ideal candidate will play a critical role in the development of cutting-edge connectivity solutions.

Key Responsibilities:

• Design and implement high-performance digital solutions, including RTL development and synthesis.
• Collaborate with cross-functional teams on IP integration for Serdes and Controller IPS, processor and peripherals
• Own block-level and full-chip designs from architecture to GDS, focusing on designs at nodes ≤ 16nm.
• Ensure timing closure, assess verification completeness, CDC, lint etc.
• Utilize tools from Synopsys/Cadence for design and emulation.

Basic Qualifications:

• Bachelor’s in Electronics/Electrical engineering (Master's preferred).
• 5+ years of digital design experience, with 4+ years focused on PCIE controller, PCS or PHY implementation.
• Proven expertise in RTL development, synthesis, and timing closure.
• Experience with front-end design, gate-level simulations, and design verification.
• Strong work ethic, ability to handle multiple tasks, and a proactive, customer-focused attitude.

Required Expertise:

• Hands-on experience with PCIE Controller or Serdes/PHY IP.
• Hands-on pre-silicon and post-silicon design implementation.
• Hands-on experience  FW interaction and embedded design.
• Strong proficiency in System Verilog/Verilog and scripting (Python/Perl).
• Experience with block-level and full-chip design at advanced nodes (≤ 16nm).
• Top level integration and DFT knowledge.

Preferred Experience:

• PCIE SerDes controller or IP level experience.
• Understanding of PAD design, DFT, and floor planning.
• Experience with NIC, switch, or storage product development including embedded FW.
• Familiarity with working in design and verification workflows in a CI/CD environment.

The Role 

We are seeking a highly skilled and motivated Manufacturing Bring-up Engineer to join our team. As the Manufacturing Bring-up Engineer you will support our system level bring-up process execution, implementation, and evolution in the manufacturing pipeline. This is a high visibility role that requires strong technical expertise, coordination, and collaboration to deliver our product from manufacturing to the customer. 

Responsibilities 

• Support the Cerebras manufacturing bring-up process execution to configure, test, and validate system performance prior to customer shipment 

• Collaborate cross-functionally with Asic, SW, Diagnostics, and QA teams to further automate and streamline the workflow for optimal manufacturing efficiency 

• Troubleshoot and resolve technical issues during system bring-up across Asic, SW, and QA domains 

• Design and implement efficient processes to manage and track system bring-up status and progress 

• Track and report on critical bring-up metrics to drive continuous improvement  

• Implement further SW automation and efficiencies to effectively scale the manufacturing bring-up process in support of the manufacturing roadmap 

Skills & Qualifications 

• BS or MS in EE, ECE, CS or equivalent work experience 

• 3+ years of industry experience in an operations environment 

• Experience in hardware bring-up and the debug of complex systems 

• Working knowledge and experience in Asic bringup and test processes 

• Working knowledge of scripting in languages such as Python and/or Perl 

• Proven experience in system bring-up and validation of complex computer systems or equivalent technologies 

• Understanding of computer system architecture and hardware components  

• Proficiency in scripting and automation tools for system bringup  

• Excellent problem-solving and communication skills with the ability to work collaboratively in a fast-paced environment 

• Very strong coordination and collaboration skills to manage a business-critical workflow directly in support of customer demand 

Preferred: 

• Familiarity in creating test and s/w infrastructure at large scale 

• Working across global time zones  

Location 

Bangalore, India/Toronto, Canada/ Sunnyvale, California.

The base salary range for this position is $170,000 to $230,000 annually.  Actual compensation may include bonus and equity, and will be determined based on factors such as experience, skills, and qualifications.

The Role 

We are seeking a highly skilled and motivated Manufacturing Bring-up Engineer to join our team. As the Manufacturing Bring-up Engineer you will support our system level bring-up process execution, implementation, and evolution in the manufacturing pipeline. This is a high visibility role that requires strong technical expertise, coordination, and collaboration to deliver our product from manufacturing to the customer. 

Responsibilities 

• Support the Cerebras manufacturing bring-up process execution to configure, test, and validate system performance prior to customer shipment 

• Collaborate cross-functionally with Asic, SW, Diagnostics, and QA teams to further automate and streamline the workflow for optimal manufacturing efficiency 

• Troubleshoot and resolve technical issues during system bring-up across Asic, SW, and QA domains 

• Design and implement efficient processes to manage and track system bring-up status and progress 

• Track and report on critical bring-up metrics to drive continuous improvement  

• Implement further SW automation and efficiencies to effectively scale the manufacturing bring-up process in support of the manufacturing roadmap 

Skills & Qualifications 

• BS or MS in EE, ECE, CS or equivalent work experience 

• 3+ years of industry experience in an operations environment 

• Experience in hardware bring-up and the debug of complex systems 

• Working knowledge and experience in Asic bringup and test processes 

• Working knowledge of scripting in languages such as Python and/or Perl 

• Proven experience in system bring-up and validation of complex computer systems or equivalent technologies 

• Understanding of computer system architecture and hardware components  

• Proficiency in scripting and automation tools for system bringup  

• Excellent problem-solving and communication skills with the ability to work collaboratively in a fast-paced environment 

• Very strong coordination and collaboration skills to manage a business-critical workflow directly in support of customer demand 

Preferred: 

• Familiarity in creating test and s/w infrastructure at large scale 

• Working across global time zones  

Location 

Sunnyvale, California/ Bangalore, India/Toronto, Canada.

The base salary range for this position is $170,000 to $230,000 annually.  Actual compensation may include bonus and equity, and will be determined based on factors such as experience, skills, and qualifications.

Rumble is seeking a Senior Infrastructure Engineer (CDN) who will be a pivotal member of the team that builds and maintains the infrastructure that is at the core of the Rumble platform. Candidates applying for this position should be very experienced and highly skilled network infrastructure engineers who are excited about the opportunity of building and supporting a fast growing, fault tolerant and high capacity platform.  A person who would be a successful candidate for this position loves challenges and problem solving, and has spent their career working on mission critical infrastructure.  This role requires someone who is motivated and can work both independently and as part of a team.

What you will do:

• Have a key role in designing and supporting Rumble’s Content Distribution Network and DNS infrastructure
• Building out fault tolerant infrastructure at a sometimes fast and relentless pace
• Improve performance and stability by optimizing routing, network performance, enhancing caching, load balancing and capacity planning
• Documenting improvements and exchanging ideas with other members of the team
• Participation in an on-call rotation, responding to and resolving incidents while communicating status to other members of the team
• Occasional travel as needed

Required Qualifications:

• 8+ years of relevant network experience
• Strong understanding of IP networking, TCP/IP, HTTP/HTTPS, and caching mechanisms to handle traffic routing and content distribution efficiently
• In depth knowledge of DNS architecture, including hierarchy, name resolution processes and record types (A, AAAA, CNAME, MX, etc.)
• Previous experience managing a robust DNS deployment
• Proficiency in programming languages such as Python, Bash or Perl for automating server configurations, deployments and maintenance
• Solid experience with linux systems and using them in a production environment
• Expert troubleshooting experience — you’re calm under pressure and can dissect and resolve the toughest infrastructure issues.
• Ability to create and maintain high quality network documentation
• Effective communicator (both verbal and written) who can clearly present information or ideas within a team
• Willingness to learn, be challenged and have fun in a dynamic and fast paced environment

Preferred Qualifications:

• Experience with DNSSEC and securing against common spoofing or poisoning attacks
• Knowledge of anycast, and DDoS mitigation strategies
• Capacity planning and experience handling large-scale queries
• Experience with BGP and open source routing daemons on linux (BIRD, FRR)
• Familiarity with openSUSE, Gentoo, Arch a plus

Desired Qualifications:

• Past experience with network monitoring tools
• Experience with network operating systems (Juniper, Arista, Cisco, etc.)
• Comfortable with using open source tools for solutions

Annual Compensation Range:

$150,000-$195,000 USD base + benefits + equity (If based in the United States)

$123,000-$142,000 CAD base + benefits + equity (If based in Canada)

Note: The salary range listed for this position is a good faith estimate based on experience, qualifications, and internal compensation structure. The actual salary offered varies depending on the candidate's skill level and experience. This posting refers to an active vacancy within the organization.

ABOUT CUBIST

Cubist Systematic Strategies, an affiliate of Point72, deploys systematic, computer-driven trading strategies across multiple liquid asset classes, including equities, futures and foreign exchange. The core of our effort is rigorous research into a wide range of market anomalies, fueled by our unparalleled access to a wide range of publicly available data sources.

JOB DESCRIPTION

Researchers are responsible for independently conducting quantitative finance research with a focus on statistical and predictive models. Successful researchers manage all aspects of the research process including methodology selection, data collection and analysis, testing, prototyping, backtesting, and performance monitoring.

Some successful researchers have joined us from similar backgrounds at other firms. Others have joined from related fields or directly from academia and have thrived with hands on guidance from our large team of experienced portfolio managers and researchers. Our most exceptional team members combine strong technical skills and a passion for problem solving with an intense curiosity about financial markets and human behavior.

DESIRABLE CANDIDATES

• MS or PhD candidates in finance, computer science, mathematics, physics, or other quantitative discipline
• 3-7 years of experience in alpha driven quantitative research for equities, futures, fixed income, credit, and/or FX
• Strong analytical and quantitative skills
• Demonstrated ability to conduct independent research utilizing large data sets
• Programming in any of the following: C++, Java, C#, MATLAB, R, Python, or Perl
• Detail-oriented
• Willing to take ownership of his/her work, working both independently and within a small team

We’re looking for exceptional colleagues with unparalleled passion. If you’d like your resume to stand out, tell us about your exceptional personal achievements, even if they have nothing to do with finance. Of course we love to hear more about specific engineering or data projects that you’ve worked outside of school, or as part of your curriculum. If you’re proud of the work you did we want to hear about it. In addition to exceptional statisticians and engineers, we work with talented musicians, writers, mathematicians, and founders of non-profits; we’d love to learn more about what excites you.

Senior ASIC (Front End) Design Engineer

Summary:

• As a Senior ASIC (Front End) Design Engineer, you will be responsible for all aspects of digital SoC design, from micro-architecture specification, RTL, verification, synthesis, lint, CDC, LEC, and static timing analysis to deliver a design meeting target power, performance, and area goals.
• Work with system architects, software, hardware, and verification engineers to plan, architect, design, implement, and deliver advanced automotive communication semiconductors and systems.
• You will be on the leading edge of the development and definition of advanced, high-performance custom silicon that embodies functions from a wide range of protocols, algorithms, and applications.
• Expected to flesh out product definitions with precise specifications of: an ASIC's internal and external interactions, data flow, processing algorithms across a number of disciplines, resource management, and software interfaces.
• You will be a trusted self-starter who can work with very little guidance or oversight.
• This position is located in: Toronto, Canada - Hybrid

Key Qualifications:

• BS and/or MS in Electrical Engineering, Computer Science, or related field
• Minimum 10+ years of ASIC RTL design and/or architecture experience
• Proven track record with the development of complex SoCs
• Strong understanding of digital design fundamentals and methodologies
• In-depth knowledge of Verilog/System Verilog and simulation tools.
• Self-motivated and able to work effectively both independently and in a team

Additional Success Factors:

Experience in any of the following areas:

• Networking (Ethernet MAC, PHY/PCS, Switching, TCP/IP, PCIe and other industry standard protocols)
• Digital signal processing filters
• Digital Mixed-Signal modeling, design, and integration
• IP integration (SerDes, controllers, processors, etc.)
• Video standards, protocols, processing
• Perl, TCL, C/C++, Make

Personal Skills:

• Excellent communication/documentation skills.
• Attention to details.
• Collaboration across multidisciplinary and international teams.

What You Can Expect from Ethernovia:

• Technology depth and breadth expansion that can’t be found in a large company
• Opportunity to grow your career as the company grows
• Pre IPO stock options
• Cutting edge technology
• World class team
• Competitive base salary
• Flexible hours
• Medical, dental and vision insurance for employees

#LI-Hybrid

We're seeking highly motivated students who possess strong technical skills and the ability to work in a fast-paced collaborative environment.

Internship opportunities are not limited to the summer and are available throughout the year.

Primary Responsibilities:

• Develop new software and enhance existing systems.
• Create tools to process, store and analyze quote, trade and financial data.
• Work closely with our traders, quantitative research analysts, implementation programmers and other groups to provide software solutions.

Requirements of the Candidate include:

• Pursuing an undergraduate or graduate level degree in Computer Science or Mathematics.
• C++ and/or Java programming knowledge or experience in a Linux environment preferred.
• Excellent academic record.
• Strong problem solving skills.
• Knowledge of shell scripts and other languages including Perl, Bash or CSH is a plus.
• Knowledge of relational databases including Sybase, SQL Server and Oracle is a plus.