Overview of Role

As a Physical Design Principal Engineer, you will be responsible for the entire SOC implementation and verification flow from RTL-to-GDS that includes floorplan, place and route, CTS, STA, PV/EMIR/Noise/SigEM cleanup and signoff on lower power SoC. You will be joining a team of engineers dedicated to pushing the envelope for a leading fabless wireless semiconductor platform company specializing in extreme low power wireless radio solutions.

Location

• San Diego or San Jose, CA

Responsibilities

• Complete entire physical implementation of the block and chip level
• Perform synthesis and physical implementation steps – synthesis, floor-planning, power delivery, place&route, timing noise, physical verification, IR/RV.
• Collaborate with the SOC design team to drive architectural feasibility studies, develop timing, power, and area design targets, and explore RTL/design tradeoffs
• Analyze the quality of the floorplan and Customized Clock tree structure and Place & Route
• Implement ECOs for timing closure
• Signal EM/Noise and Power IR/EM analysis and fix
• DRC/LVS/ERC/ANTENNA analysis and clean up
• Timing verification and signoff
• Physical verification and sign off

Minimum Qualifications

• Master’s degree or above in electrical/computer science engineering with 10+ years of industry experience, or bachelor’s degree in electrical/computer science engineering plus 15+ years of industry experience
• Strong experience in Power/Ground grids, Partitioning, Timing ECO implementation, and physical verification.
• The entire SOC implementation and verification flow from RTL-to-GDS that includes fullchip floorplan, place and route, CTS, and layout verification signoff on lower power SoC
• Netlist (or RTL)-GDS physical implementation experience
• In depth knowledge of major EDA tools/design flows
• Strong Cadence experience/background
• Experience with TSMC N22 or below technology
• Experience in chip integration and signoff
• Experience in Perl/TCL language programming

Preferred Qualifications

• Strong experience in Low-power implementation methodology
• Strong experience in Advanced timing signoff methodology
• Knowledge of DFT (BSCAN, MBIST, SCAN) and understanding of their impact on physical design flows
• Able to independently complete Netlist-GDS P&R, signoff task
• Proven record in multi-million gate design production tapeouts

As a Sr. Staff/ Principal Digital Design Engineer, you will be working with a team of design engineers to develop novel SoC products for connectivity and communications. You will also be a key contributor to product definition and resulting detailed device performance and functional requirements specifications. In addition to delivering high quality digital solutions in the context of the product architecture, the team supports other disciplines with work product such as Verilog stimulus files, test benches for device bring up/characterization, test vectors for product manufacturing, etc.

Key Responsibilities

• Contribute to/review SoC specifications and architectures
• Front to back digital design and verification – RTL through physical implementation
• Hands on technical leadership
• Support schedule and resource planning
• Help define and socialize digital/system design, implementation methodologies and test strategies and flows
• Debug designs and provide timely closure
• Work with System, Software, RF, Analog, and Test teams and provide necessary support

Job Requirements

• MS/PhD EE/CS preferred
• 10 or more years of experience digital SoC development required
• Experience bringing highly integrated mixed signal SoCs to commercial mass production
• Experience with embedded systems, wireless protocols, power management, signal processing and standard digital interfaces
• Deep RTL design knowledge (Verilog/VHDL) and SystemVerilog, checkers, and other design verification techniques
• Deep knowledge of front-end tools (Verilog simulators, linters, clock-domain crossing checkers)
• Proven knowledge of synthesis, static timing, DFT and (Front to Back) F2B digital SoC design flow
• Experience with ATPG, fault grading, scan, BIST, DFT/DFM
• Proven knowledge of SystemVerilog assertions,
• Knowledge of languages such as C/C++, Perl, Tcl and Python
• Strong communication and presentation skills
• Good skills and interest in mentorship
• Ability to foresee issues and design in flexibility and workarounds for both known and unknown unknowns
• Expert in RTL design and implementation (architecture and micro-architecture)
• Deep knowledge of front-end tools and flow - Verilog simulators, linters, synthesis, static timing, clock trees, power simulation, floor plan development, and power supply implementation
• Deep knowledge of system modeling and verification using System Verilog or System C
• Proven knowledge in acquiring and integrating 3rd party IP
• High speed logic design (GHz+) , and high speed clock distribution experience.
• Understanding of mixed signal concepts

 Desirable Skills

• Experience with Cadence F2B design tools
• Experience with formal verification tools
• Able to work effectively with incomplete or changing requirements
• Good mentorship skills
• Strong knowledge of mixed signal concepts
• Focused, goal driven finisher