About Us

Are you ready to build the future of the supply chain? At Gather AI, we’re not just creating software; we’re pioneering a new era of warehouse intelligence. We’ve developed a groundbreaking, vision-powered platform that uses autonomous drones and existing equipment to capture real-time data, completely digitizing workflows that have historically been manual and error-prone. This means facilities operate smarter, safer, and more efficiently, ultimately redefining “on-time, in full” delivery.

If you’re looking for an opportunity to contribute to truly transformative technology and make a significant impact in a vital industry, Gather AI is the place for you. We’re leading the charge in the rapidly evolving robotics industry, and we invite you to join us in reshaping the global supply chain, one intelligent warehouse at a time.

About the Team

This role sits at the intersection of our Autonomy, Machine Learning, Hardware, and Product teams. You will collaborate with engineers across drone, MHE Vision, and embedded systems, partner with Product on scanning accuracy requirements, and work with Hardware and Operations on camera mounting, lighting, and real-world warehouse deployment.

About the Role

We are seeking a Staff Robotics Engineer - Perception to take full technical ownership of one of Gather AI's two production platforms — our drone-based inventory scanning system or our MHE Vision product — deployed today in customer warehouses. You'll bring systems-level rigor to a platform that already works, with a mandate to make it faster to deploy, easier to operate, and more reliable at scale. 

This is a high-ownership, high-impact role, critical to the quality of every scan our system performs. You will drive technical direction and deliver measurable impact on production systems serving real customers.

What You’ll Do

• Own the camera and imaging subsystem audit across MHEV and Modal: characterize existing performance (barcode decode rates, read distances, motion blur impact) and identify top bottlenecks
• Evaluate and select camera and sensor hardware — specifying resolution, sensor size, lens selection, and exposure control for industrial warehouse environments
• Implement and tune auto-exposure, gain control, and lighting strategies for variable warehouse lighting conditions, including motion blur mitigation for moving platforms
• Develop image quality metrics and production monitoring to maintain system performance as deployments scale
• Collaborate with the ML team to ensure perception model inputs meet training and inference quality requirements; contribute to next-generation capabilities such as damage detection and label reading
• Work with the hardware team on camera mounting, vibration/damping, and lens placement to optimize system-level performance

What You’ll Need

• 5+ years of experience in machine vision, imaging systems, or perception engineering
• Deep expertise in camera systems: sensor selection, lens specification, resolution analysis, pixels-on-target calculations, and exposure control for industrial applications
• Hands-on experience with motion blur analysis and mitigation — rolling vs global shutter trade-offs, exposure budgeting relative to platform velocity
• Strong Python and C++ proficiency with OpenCV and camera SDK experience (FLIR, Lucid, Basler, or similar); familiarity with GigE Vision or USB3 Vision standards
• BS or MS in Electrical Engineering, Optics, Physics, Computer Science, or a related field

Nice to Have

• Experience with drone or robotics perception systems (gimbal stabilization, triggering, onboard compute constraints)
• Optical design or lens selection experience (MTF analysis, depth of field, distortion characterization)
• Edge compute and embedded vision experience (NVIDIA Jetson, FPGA-based image processing)
• Familiarity with classical and deep learning perception algorithms and how image quality affects model performance

Efficient is looking for a seasoned Design Verification & Emulation Manager to staff, lead and scale our verification and emulation organization which is part of our newly formed HW engineering organization. This is a high-impact leadership role responsible for ensuring silicon correctness and system-level readiness across multiple industry defining product lines. You will own the verification strategy from block-level to full-chip, drive emulation-based validation for early software enablement, and build a world-class team of verification and emulation engineers.

This role combines deep technical expertise with strong people leadership and program execution skills, and is ideal for someone who thrives at the intersection of architecture, verification methodology, hardware-software integration, and team building. This is a unique opportunity to have an influence on our products and processes as we move from the initial stages of product development to market release and scaled volume production.  Join our team and help us shape the future of computing at the edge and beyond! 

Key Responsibilities 

• Define end-to-end verification strategy from block-level through full-chip simulation to emulation and prototyping
• Own UVM-based methodology, including constrained-random, coverage-driven closure, assertions, and formal verification adoption
• Drive emulation platform strategy — platform selection, capacity planning, compilation flows, and multi-project scheduling
• Enable system-level validation on emulation — processor boot, OS bring-up, firmware execution, and IO exercising
• Deliver pre-silicon platforms for early software development in partnership with firmware and software teams
• Establish hybrid simulation-emulation methodologies using transactor-based interfaces to maximize both environments
• Own functional coverage models and sign-off criteria, driving closure across simulation and emulation combined
• Lead debug and root cause analysis across simulation and emulation, driving cross-functional bug resolution
• Manage verification dashboards, bug tracking, and regression health to provide clear visibility to program leadership
• Build, mentor, and scale a high-performing team of verification and emulation engineers
• Drive verification schedules and risk mitigation aligned with chip program milestones and tapeout readiness
• Represent verification and emulation in tapeout readiness reviews and program-level decision forums
• Collaborate cross-functionally with Compiler Team, RTL design, architecture, DFT, physical design, and post-silicon teams
• Manage emulation lab infrastructure, including hardware resources, licensing, and vendor relationships
• Evaluate and adopt new EDA tools and methodologies, including AI/ML-assisted verification techniques.
• Define right DV  mix for in-house  vs outsourcing to 3rd party vendors. Coordinate 3rd party vendor resources towards achieving project goals.

Required Qualifications & Experience 

• Education: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. PhD is a plus.
• Experience: 12+ years of progressive experience in ASIC/SoC design verification, with at least 3–5 years in a management or senior technical leadership role overseeing both verification and emulation functions.
• Verification Methodology: Deep expertise in UVM, constrained-random verification, functional coverage, assertions (SVA), and simulation-based debug. Strong understanding of formal verification techniques.
• Emulation Platforms: Hands-on experience with at least one major emulation platform (Palladium, ZeBu, or Veloce) and familiarity with FPGA prototyping flows.
• Languages & Tools: Strong proficiency in SystemVerilog, Verilog, and C/C++ for testbench and reference model development. Experience with Python, Tcl, and scripting for flow automation.
• SoC Architecture: Solid understanding of modern SoC architectures — processors (ARM, RISC-V), cache coherency, interconnects (AMBA AXI/ACE/CHI), memory subsystems, and common peripherals.
• Leadership: Demonstrated ability to build, mentor, and manage verification teams of 10+ engineers. Experience hiring, developing talent, and scaling teams.
• Execution: Strong track record of driving verification closure and tapeout sign-off on complex designs (multi-million gate, multi-clock domain, multi-power domain).

Preferred Qualification

• Experience with portable stimulus standard (PSS / Accellera) for verification reuse across simulation and emulation.
• Background in power-aware verification (UPF/CPF-based) and low-power design verification challenges.
• Experience with AI/ML-assisted verification techniques (e.g., intelligent coverage convergence, ML-driven regression optimization).

We offer a competitive salary for this role, generally ranging from $210,000 to $250,000, along with meaningful equity and comprehensive benefits. The final compensation package will be based on your experience and location, with some flexibility to ensure we align with the right candidate.

We are seeking a Senior Software Optimization Engineer to join our growing team. Efficient’s Senior Software Optimization Engineer will design, optimize, and deploy applications for the world’s most energy-efficient programmable processor (the “Fabric”). In this role, you will take ownership of complex, performance-critical applications, working closely with Efficient’s compiler team to implement customer requirements, validate software quality, and provide deep technical insight into compiler interactions. This position is a unique opportunity to work on cutting-edge hardware/software co-design, while making an immediate impact in building the next generation of embedded applications.

Key Responsibilities 

• Independently design and implement complex embedded applications based on customer requirements, specifications, and existing code.
• Drive application optimization using Efficient’s compiler and software stack targeting the Fabric.
• Deploy and validate applications on the Fabric across software simulation and FPGA emulation environments.
• Own performance and energy-efficiency analysis, developing benchmarks and methodologies to evaluate applications against customer requirements.
• Identify, reproduce, and distill issues into minimum-viable test cases, conveying precise feedback to the compiler team.
• Collaborate deeply with the compiler team to test, debug, and refine compiler features.
• Contribute advanced optimizations to frameworks and libraries in domains such as DSP and machine learning.
• Provide architectural feedback based on hands-on experience to influence both software and hardware evolution.

Required Qualifications & Experience Requirements 

• Must be an excellent embedded engineer with 8+ years of work experience
• 3+ years of C/C++ experience
• Deep knowledge of at least one embedded platform, such as MSP430, STM32, Ambiq Apollo, PIC32, or similar
• Experience developing and deploying applications under resource constraints
• Experience using non-standard build environments and compiler toolchains, especially for embedded systems
• Experience using industry standard development and debugging tools for embedded development
• Strong attention to detail, good work ethic, ability to work on multiple projects simultaneously, and good communication skills 
• Good problem solving skills

Desired Qualifications & Experience Requirements 

• Experience using LLVM, MLIR, GCC, or a similar compiler framework to develop compiler passes
• Experience building TinyML models and deploying models under severe resource constraints (e.g. limited memory)
• Experience writing optimized BLAS and DSP kernels
• Knowledge of computer architecture

We offer a competitive salary for this role, generally ranging from $160,000 to $210,000, along with meaningful equity and comprehensive benefits. The final compensation package will be based on your experience and location, with some flexibility to ensure we align with the right candidate.