Qube Research & Technologies (QRT) is a global quantitative and systematic investment manager, operating in all liquid asset classes across the world. We are a technology- and data-driven group implementing a scientific approach to investing. Combining data, research, technology, and trading expertise has shaped our collaborative mindset, which enables us to solve the most complex challenges. QRT’s culture of innovation continuously drives our ambition to deliver high-quality returns for our investors. 

Market Access is responsible for building and maintaining the cutting-edge technology systems that connect QRT to global financial markets, brokers, and third-party providers. These systems are critical for delivering real-time market data and executing orders with speed, reliability, and precision. By enabling our strategies and traders to operate seamlessly, the team plays a pivotal role in supporting QRT’s rapidly expanding business needs and ensuring we maintain our competitive edge through world-class trading technology.

Your future role within QRT 

• A key member of the development team building and enhancing low latency algorithmic trading strategies for QRT 

• Coverage of all aspects of the algorithmic trading strategy, including the exchange price feeds, financial indicators, market making algorithms, back-testing engine, tick data management, exchange simulators and trading gateways, as well as support of the production environment and the processes surrounding it 

• You will work closely with a range of investment management professionals including quantitative analysts/developers, traders and operations staff, in order to design and develop cutting edge systems to keep QRT’s business at the forefront of its field 
• Opportunity to contribute to quantitative research, although this is not the core focus of the role 

Your present skillset 

• Computer Science degree or equivalent 

• Essential you have a background in Linux / C+ low latency optimizations (5 years+ on low latency Linux development using C/C++, STL, Boost) 

• Experience designing and implementing multithreaded and distributed systems 

• Experience of front-office trading desk-aligned role is an advantage 

• Good knowledge of distributed network architecture 

• Good knowledge of Equities and Futures asset classes highly desirable 

• Familiar with low level optimization techniques on x86/64 platform 

• Familiar with Linux / GCC development toolchain and Linux Red Hat distribution 

• Knowledge of market data feed handlers and execution gateways highly desirable 

• A background in Linux kernel, FPGA and Network card offloading will also be advantageous 

 
Base salary range for this position is $180,000 to $300,000 per year. 

QRT Total Compensation includes discretionary performance-based bonuses and a competitive benefits package.

Qube Research & Technologies (QRT) is a global quantitative and systematic investment manager, operating in all liquid asset classes across the world. We are a technology and data driven group implementing a scientific approach to investing. Combining data, research, technology and trading expertise has shaped QRT’s collaborative mindset which enables us to solve the most complex challenges. QRT’s culture of innovation continuously drives our ambition to deliver high quality returns for our investors. 

Your future role within QRT:

QRT are a rapidly growing hedge fund trading globally in competitive financial markets across Europe, the Middle East and Asia. As part of the next phase of development we are rolling out hardware platforms to accelerate our trading systems. FPGA development will be at the heart of many of these systems with a focus on high frequency trading. 

We are looking for talented hardware engineers with a track record of achievement in any domain. You may have experience of finance and trading, but it is not essential. You probably enjoy solving complex system problems where hardware and software come together to provide high performance solutions. We are looking for a range of experience from graduates through to senior engineers, so your achievements may be in academia or industry.

You will have the opportunity to work with the latest technologies and have your voice heard in this fast paced firm. Working with trading teams you will take ownership of:

• Translating trading ideas into the most appropriate solutions
• Develop RTL on the latest FPGAs with modern design flows
• Following through into production, analysing results and optimising

Your present skillset:

• A deep understanding of FPGA architecture leading to efficient designs
• Full lifecycle RTL development including automated verification
• Python scripting
• A working knowledge of C/C++ development
• An ability to see through complexity to identify simple solutions
• A realisation that good teamwork is essential to modern development

 
Base salary range for this position is $180,000 to $280,000 per year. 

QRT Total Compensation includes discretionary performance-based bonuses and a competitive benefits package.

Qube Research & Technologies (QRT) is a global quantitative and systematic investment manager, operating in all liquid asset classes across the world. We are a technology and data driven group implementing a scientific approach to investing. Combining data, research, technology and trading expertise has shaped QRT’s collaborative mindset which enables us to solve the most complex challenges. QRT’s culture of innovation continuously drives our ambition to deliver high quality returns for our investors.  

The successful candidate will join the established DCO team at QRT, working closely with Network Engineering and infrastructure teams you will be responsible for the implementation and physical  deployment of electronic trading infrastructure in support of the firm’s trading activities.

Your Future Role within QRT

• Contribute to the design and planning of new equipment deployments in line with data centre best practices

• Deploy, maintain, and decommission trading infrastructure hardware, including FPGA platforms, ultra-low-latency servers, and high-performance network switches, across a global colocation footprint

• Ensure consistent build quality across structured cabling, rack layouts, power distribution, cooling infrastructure, and environmental monitoring

• Coordinate installations, upgrades, capacity expansions, and decommissions with exchanges, colocation providers, hardware vendors, and onsite engineers

• Support procurement, logistics, inventory management, and the movement of hardware and components between sites

• Maintain accurate and up-to-date infrastructure documentation (rack elevations, patching matrices, connectivity layouts) using CMDB tools such as NetBox

• Work closely with network engineering and trading teams to ensure physical infrastructure meets performance and operational requirements

• Use basic scripting (Python, Bash, Ansible) to support automation, monitoring, and operational tooling where required

• Ensure data centre operations meet high standards of security, cleanliness, documentation, and supply management

• Install, troubleshoot, and support servers, switches, timing devices, and cabling in live environments

• Provide break-fix support in a 24/7 global trading environment

Your Present Skillset:

• Experience working in low-latency or high-performance trading infrastructure environments (e.g. HFT, exchange colocation, market making)

• Strong understanding of hardware and systems used in low-latency trading, including FPGAs, optical taps, high-performance servers, networking, and timing equipment

• Solid understanding of hardware and network devices, including basic configuration

• Proven experience managing vendors and delivering on-site changes and large-scale deployments to exacting standards

• High standards of physical build quality, attention to detail, and operational discipline in infrastructure layout and cabling

• Strong documentation skills with a focus on process consistency and operational readiness

• Comfortable working in a fast-paced, globally distributed team environment

• Willingness to travel internationally and provide occasional evening or weekend support as part of a flexible operations schedule

• Ability to participate in an out-of-hours on-call rotation supporting global trading operations

Base salary range for this position is $150,000 to $180,000 per year. 

QRT Total Compensation includes discretionary performance-based bonuses and a competitive benefits package.

Senior Network Engineer  

About IEX: 

IEX (IEX Group, Inc.) is an exchange operator and technology company dedicated to innovating for performance in capital markets. Founded in 2012, IEX launched a new kind of securities exchange in 2016 that combines a transparent business model and unique architecture designed to protect investors. Today, IEX applies its proprietary technology and experience to drive performance across asset classes, serve investors, and advocate for transparent and competitive markets.   

Role Overview: 

IEX is seeking a Senior Network Engineer to join our growing Infrastructure team. In this role, you will contribute to the design, implementation, and operation of high-performance, low-latency networks, including IEX’s new Options Exchange. This role requires expertise in low-latency networking and high-performance infrastructure to support real-time trading operations. The ideal candidate thrives in a high-pressure, fast-changing, and demanding environment, where microseconds matter. You will also play a crucial role in ensuring the resilience, scalability, and security of our infrastructure. 

What You’ll Do: 

Network Design & Engineering: 

• Participate in the engineering process to design, build, and manage resilient, high-performance network platforms 

• Collaborate with teams to ensure our network supports high-availability and low-latency operations 

• Contribute to the capacity planning, performance engineering, and scalability of network infrastructure 

Network Automation & Operations: 

• Automate, deploy, maintain, monitor, and upgrade network systems and services 

• Design and implement tools to automate network tasks and improve network operations 

• Monitor network performance, troubleshoot issues, and optimize the network to ensure reliability 

• Configure and maintain high-performance switches, routers, and firewalls from vendors such as Arista, Cisco, Juniper, and Fortinet 

Collaboration & Support: 

• Work with cross-functional teams, including Data Center Engineers and SREs, to maintain seamless network operations 

• Provide troubleshooting support and collaborate with vendors and contractors to resolve network issues quickly and efficiently 

Your Background: 

Experience: 

• Minimum of 10 years of experience in networking, with a focus on high-performance, low-latency networks 

• Strong experience with multicast and network automation platforms, such as Ansible and Python 

• Proven experience in the financial services industry, ideally in a High-Frequency Trading firm, Proprietary Trading Firm, or Exchange environment 

• Solid experience with capacity planning, network performance tuning, and implementing network upgrades 

Technical Skills: 

• Advanced understanding of network protocols and technologies, including TCP/IP, BGP, OSPF, VRF, STP, IGMP, PIM 

• Hands-on experience with network automation and orchestration tools (e.g., Ansible, Python, or similar platforms) 

• Familiarity with network monitoring tools and performance tuning techniques 

• Experience with firewalls and load balancers 

• Experience with BGP traffic engineering 

• Ability to troubleshoot packet loss, jitter, microbursts, and network latency issues in real-time 

• Familiarity with FIX protocol, FPGA-based networking, and market data feed handlers 

• Solid understanding of exchange connectivity, colocation facilities, and direct market access (DMA) 

• Prior work with cloud-based trading environments and hybrid infrastructures (AWS, GCP, or Azure) 

 Certifications & Education: 

• Bachelor's degree in computer science, Information Technology, Engineering, or a related field. 

• Networking certifications (e.g., CCNP, CCIE, JNCIE, or Arista ACE) are preferred 

Personal Attributes: 

• Experience working in fast-changing, high-pressure environments where downtime directly impacts revenue 

• Self-starter with a passion for learning new technologies and solving complex networking problems 

• Strong critical thinking and problem-solving skills, with the ability to think both strategically and tactically 

• Motivated to take on challenges, with the ability to work independently and take ownership of projects 

• Detail-oriented and highly organized, capable of managing multiple projects and priorities in a fast-paced environment 

• Proven ability to collaborate effectively with cross-functional teams to achieve common goals 

Additional Information: Occasional travel to other data centers and disaster recovery sites, as required 

Our job titles may span more than one career level. The starting annual base pay is between $225,000 and $250,000 for this NY-based position. The actual base pay is dependent upon many factors, such as: training, transferable skills, work experience, business needs and market demands. The annual base pay range is subject to change and may be modified in the future. This role is eligible for bonus and equity. 

Here at IEX, we are dedicated to an inclusive workplace and culture. We are an Equal Opportunity Employer that does not discriminate on the basis of actual or perceived race, color, creed, religion, alienage or national origin, ancestry, citizenship status, age, disability or handicap, sex, marital status, veteran status, sexual orientation, genetic information or any other characteristic protected by applicable federal, state or local laws. This policy not only complies with all applicable laws and protects workers' rights but is vital to IEX’s overall mission and values. 

 NYC Applicants_Notice Regarding Use of Automated Employment Decision

The applications for our FPGA Verification and Developer internships and full-time roles have not yet opened. To express your interest and be alerted when these positions open, submit your information below!

The Hardware team at Hudson River Trading (HRT) creates high performance compute engines using FPGA and ASIC technology to drive low latency trading decisions on global markets. We build custom solutions across the spectrum of speed and smarts: from bespoke circuits to world-class machine learning accelerators.

These high performance designs require even higher performance verification. We are looking for experienced Design Verification (DV) engineers who are skilled at writing testbenches and building verification environments to exercise complex HDL. Our ideal candidate is not only an ace tester, but a practicing toolsmith. You know the EDA landscape and want to be part of a team actively working to rethink, redesign, and surpass the status quo. For example, members of our team are active maintainers of popular open source projects such as Slang, Verilator, and Cocotb.

FPGA and ASIC verification is part of an innovative, growing team at HRT which is integral to the success of our trading. You can expect to always be challenged by the ever-changing financial markets as you work to ensure correctness and robustness of our critical hardware in an extremely fast-paced, real-time environment. No financial experience is necessary.

Responsibilities

• Creating testbenches and tests for our hardware platform, leveraging a hybrid open-source/proprietary, highly flexible environment
• Writing detailed verification plans
• Quickly root-cause RTL bugs
• Collaborating directly with designers for rapid bringup of new projects and debugging of existing designs
• Managing test suites and continuous integration infrastructure
• Developing and improving open-source and internal tools

Qualifications 

• Superb debug and analytical skills 
• Professional experience (2+ years) in RTL functional verification for FPGA or ASIC
• Experience with code and functional coverage collection/analysis
• Experience with SystemVerilog and industry-standard frameworks such as UVM
• Experience with Python
• Comfortable in a Linux environment
• Familiarity with Verilator and/or Cocotb preferred
• C++ experience is a plus
• A bachelor’s degree in computer science, electrical engineering, or a related field

The estimated base salary range for this position is 175,000 to 250,000 USD per year (or local equivalent). The base pay offered may vary depending on multiple individualized factors, including location, job-related knowledge, skills, and experience. This role will also be eligible for discretionary performance-based bonuses and a competitive benefits package.

Hudson River Trading (HRT) is seeking a Physical Design Engineer with a broad, versatile skillset to join our growing Hardware team. In this role, you will help deliver performance-critical ASICs and advance our physical design methodologies on leading-edge process nodes.

The Hardware team at HRT builds high-performance compute engines using FPGA and ASIC technology to drive low-latency trading decisions on global markets. We create custom solutions across the full spectrum of speed and sophistication, from bespoke circuits to world-class machine learning accelerators.

Responsibilities

• Drive design-for-test (DFT) methodologies and implementation 
• Contribute to physical implementation, from RTL handoff through GDSII on advanced process nodes 
• Partner on floorplanning and physical optimization for high-performance, latency-critical designs
• Close timing across multiple modes and corners while optimizing power, performance, and area (PPA)
• Diagnose and resolve physical design issues such as timing bottlenecks, congestion, and IR/EM violations
• Build, maintain, and improve repeatable, automated physical design flows
• Develop scripts and tooling to improve productivity, robustness, and insight into design behavior
• Collaborate closely with RTL, architecture, and other hardware engineers to influence design decisions early

Qualifications

• Experience working in high-performance ASIC design environments
• Strong fundamentals in digital logic, circuit design, and process technology
• Familiarity with DFT concepts and testing methodologies
• Strong scripting and automation skills (Python, Tcl, shell), including parsing and analyzing tool outputs
• Ability to design robust methodologies, diagnose complex failures, and improve physical design flows
• Applied use of statistics in analyzing timing, power, or design data (preferred)
• Hands-on experience with static timing analysis and timing closure methodologies
• Expertise using industry-standard physical design and signoff tools (e.g., Innovus, PrimeTime)

This job is accepting ongoing applications and there is no application deadline.

The estimated base salary range for this position is 200,000 to 300,000 USD per year (or local equivalent). The base pay offered may vary depending on multiple individualized factors, including location, job-related knowledge, skills, and experience.

This role will also be eligible for discretionary performance-based bonuses and a competitive benefits package which includes medical, dental, vision, basic life insurance, and enrollment in our company’s retirement savings plans. Employees will receive sick and parental leave, as well as other paid time off (including 20 vacation days and 10 paid holidays in the US). Please note that benefits and time off policies will vary across non-US locations.

In any materials you submit, you may redact or remove age-identifying information such as age, date of birth, or dates of school attendance or graduation. You will not be penalized for redacting or removing this information.

The Hardware team at Hudson River Trading (HRT) creates high performance compute engines using FPGA and ASIC technology to drive low latency trading decisions on global markets. We build custom solutions across the spectrum of speed and smarts: from bespoke circuits to world-class machine learning accelerators.

FPGAs and ASICs are critical pieces of our technology stack. We are looking for talented hardware developers to architect and design complex systems on a highly collaborative global team. In this role, you'll identify efficient ways to perform on-the-fly transformations of market data and implement models with complex data structures in RTL. Deep knowledge of SystemVerilog, FPGA internals and/or ASIC primitives, computer architecture, and vendor tool suites are essential to succeeding in this role. Expertise in networking protocols, CPU design, and/or machine learning accelerators is a big plus. No financial experience is necessary.

Responsibilities

• Collaborate with a cross-functional team to develop and deploy custom FPGA and/or ASIC solutions for a wide range of trading applications
• Investigate new technologies and tools
• Contribute to a nimble hardware development tech stack

Qualifications

• Ability to describe hardware designs at a high level, low level, or anywhere in between
• Brilliant design, optimization, debugging and problem solving skills
• Professional experience (2+ years) in RTL design for FPGA or ASIC
• Expert SystemVerilog development skills with a thorough understanding of the language 
• Expert on low level FPGA or ASIC architectures, with a deep understanding of what makes them "tick"
• Skilled in network communications, processing pipelines, and/or machine learning
• Working knowledge of Python and/or C++
• Comfortable in a Linux environment
• Strong verification experience
• Familiarity with AMD Vivado is a plus
• A bachelor’s degree in computer science, electrical engineering, or a related field

This job is accepting ongoing applications and there is no application deadline.

The estimated base salary range for this position is 200,000 to 300,000 USD per year (or local equivalent). The base pay offered may vary depending on multiple individualized factors, including location, job-related knowledge, skills, and experience.

This role will also be eligible for discretionary performance-based bonuses and a competitive benefits package which includes medical, dental, vision, basic life insurance, and enrollment in our company’s retirement savings plans. Employees will receive sick and parental leave, as well as other paid time off (including 20 vacation days and 10 paid holidays in the US). Please note that benefits and time off policies will vary across non-US locations.

In any materials you submit, you may redact or remove age-identifying information such as age, date of birth, or dates of school attendance or graduation. You will not be penalized for redacting or removing this information.

Hudson River Trading (HRT) is hiring an AI Researcher to join the HAIL team. HAIL (HRT AI Labs) is the team at HRT responsible for developing and maintaining our most powerful models, which are used by our trading teams to drive a significant fraction of our trading. We are building and deploying "foundation models for markets", that ingest and train on vast amounts of market data, to make predictions about future market state. We are seeking experienced AI researchers to join our team to accelerate our efforts.

Researchers have great independence to pursue the research directions they think would be most impactful as part of a small focused team with minimal bureaucracy. They are enabled by state-of-the-art research clusters with very high GPU-to-researcher ratios, and supported by excellent engineering, hardware, and systems teams to realize their vision. Your work will be directly, clearly, highly impactful on the business, and it will be challenging: this is a field with no easy or obvious solutions. You'll be responsible for improving every part of our models: from featurization of data, to architecture design, to training dynamics, to how trading decisions are made.

Qualifications

• Must have two or more years work experience in deep learning research, for any domain: robotics, biology, chemistry, physics, audio, video, etc.
• Experience translating methods between areas of application is highly valued.
• LLM experience is valuable, but not necessary.
• Strong engineering skills valued, especially any of: GPU kernel development, lower-level Pytorch/JAX development, intermediate C++, FPGA/ASIC experience, HPC experience.

The estimated base salary range for this position is 200,000 to 300,000 USD per year (or local equivalent). The base pay offered may vary depending on multiple individualized factors, including location, job-related knowledge, skills, and experience. 

This role will also be eligible for discretionary performance-based bonuses and a competitive benefits package which includes medical, dental, vision, basic life insurance, and enrollment in our company’s retirement savings plans. Employees will receive sick and parental leave, as well as other paid time off (including 20 vacation days and 10 paid holidays in the US). Please note that benefits and time off policies will vary across non-US locations.

About the Position

We are looking to hire an experienced ASIC Engineer to help us design, test and deploy advanced hardware designs. As part of our Ultra Low Latency team, you’ll have the opportunity to collaborate with people in areas across the firm, including trading, networking and research infrastructure. We are looking for someone who can contribute to all of our projects and be happy to work on both FPGA-based and ASIC-based technologies.

We’re big believers in the ability of tools to improve the productivity, reliability and day-to-day joy of hardware engineering. That’s why we created Hardcaml, a hardware development toolchain embedded in OCaml. We don’t expect you to know OCaml (we’ll teach you here), but we are looking for hardware engineers who are excited about the advantages that better tools can bring, and are willing to try new things as a result.

About You

• Have 4+ years practical experience in RTL design and verification
• Experienced in ASIC design using either Synopsys or Cadence flows, including at least one of the following:
  • Front-end RTL design and synthesis
  • Back-end physical design
  • Verification (including formal)
• Interested in using software engineering techniques to improve the hardware design process, and experience programming in some high-level languages (Python, C++, Java, Haskell, etc.)

If you're a recruiting agency and want to partner with us, please reach out to agency-partnerships@janestreet.com.

At Optiver we pride ourselves on being real engineers, not just coders. Our engineers work closely with traders to identify the business problems we face and determine how they should be solved. We apply a disciplined and scientific approach. We engineer simple, well-architected solutions that meet the dynamic needs of our traders. Our passion is to solve problems which really matter to the business, and we take pride in the quality of our solutions.

Hardware Engineers at Optiver build hardware-based trading systems ranging from low latency algorithms to high bandwidth computation. They are responsible for owning all aspects of the development process from ideation to implementation creating bespoke solutions to our complex trading problems. Their systems have little room for failure which add to the stability of the market, not detract from it. Working in close collaboration with software engineers and traders, hardware engineers deeply understand our trading problems and create dynamic, well-architected systems that make an impact in a matter of days and weeks rather than months and years.

What you’ll do: 

• Accelerate network infrastructure and trading system components with high-speed hardware designs.
• Research new low-latency techniques and platforms and identify opportunities for integration with our trading system.
• Work in a multidisciplinary team of traders, software developers, and infrastructure engineers.
• Leverage the best hardware available or build in-house versions to ensure our FPGAs can interface with cutting edge server hardware.
• Manage relationships with 3rd party vendors.

What you’ll get:

You’ll join a culture of collaboration and excellence, surrounded by curious thinkers and creative problem-solvers. Motivated by a passion for continuous improvement, you’ll thrive in a supportive, high-performing environment alongside talented colleagues, collectively tackling some of the toughest challenges in the financial markets.

In addition, you’ll receive:

• The opportunity to work alongside best-in-class professionals from over 40 different countries
• A highly competitive compensation package
• Global profit-sharing pool and performance-based bonus structure
• 401(k) match up to 50%
• Comprehensive health, mental, dental, vision, disability, and life coverage
• 25 paid vacation days alongside market holidays
• Extensive office perks, including breakfast, lunch and snacks, regular social events, clubs, sporting leagues and more

Who you are:

• A Bachelor’s degree in CE, EE, CS, or related technical field.
• Experience designing, coding, testing, and verifying FPGAs and/or ASICs.
• Experience coding in VHDL, Verilog, SystemVerilog as well as C or C++.
• Experience with RTL synthesis, writing timing, area, and other relevant constraints.
• Experience with digital simulators and self-checking test benches.
• Experience supporting post-silicon bring-up and debugging a plus.
• Ability to work closely with software developers to rapidly deliver integrated systems.

Who we are:

At Optiver, our mission is to improve the market by injecting liquidity, providing accurate pricing, increasing transparency, and stabilising the market no matter the conditions. With a focus on continuous improvement, we prioritise safeguarding the health and efficiency of the markets for all participants. As one of the largest market making institutions, we are a respected partner on 100+ exchanges across the globe.

Our differences are our edge. Optiver does not discriminate on the basis of race, religion, color, sex, gender identity, sexual orientation, age, physical or mental disability, or other legally protected characteristics.

Optiver is seeking Software Engineers specializing in the US cash equities and US ETF markets to help lead our continued rapid growth across cash equities. Our Software Engineers lead large technical projects, help set the direction for our trading infrastructure, and leverage technology to enable business success.

Our cash equities engineering team is building out systems that must ingest and react to market data feeds from major US exchanges in microseconds or less, efficiently price and hedge positions of single stocks and ETFs and execute orders with extremely low error tolerance. We continually refine, store, and analyze terabytes of data produced by market activity and our trading systems. Our user interfaces must present coherent, responsive real-time visualizations of market activity and system performance while providing intuitive control of a highly complex system. Our core systems must provide a stable, performant, and trusted foundation on which our systems are built.

What you’ll do:

In this role you will be building out functionality across simulation, research, and production systems. Specifically, you will:

• Help establish the vision and technical direction for major cash equities trading initiatives
• Design, develop, support, and maintain large portions of our low-latency equities trading infrastructure, including order management systems (OMS) and execution management systems (EMS)
• Contribute to our pricing, research and trading models that power our market-making and proprietary trading strategies in US equities and US ETFs
• Develop a deep understanding of exchange-specific protocols, order book dynamics and exchanges connectivity
• Optimize data processing pipelines to handle market data from multiple exchanges at scale while continuously improving execution speed and system performance
• Work closely with FPGA engineers to leverage hardware acceleration for ultra-low-latency execution and explore novel ways to integrate FPGAs with software-driven trading infrastructure
• Collaborate deeply with traders, engineers, and researchers to help us evolve our execution logic and market impact models

Technology at Optiver:

At Optiver we pride ourselves on being real engineers, not just coders. Our engineers work closely with traders to identify the business problems we face and determine how they should be solved. We apply a disciplined and scientific approach. We engineer simple, well-architected solutions that meet the dynamic needs of our traders. Our passion is to solve problems which really matter to the business, and we take pride in the quality of our solutions.

What you’ll get:

You’ll join a culture of collaboration and excellence, where you’ll be surrounded by curious thinkers and creative problem solvers. Motivated by a passion for continuous improvement, you’ll thrive in a supportive, high-performing environment alongside talented colleagues, working collectively to tackle the toughest problems in the financial markets.

In addition, you’ll receive:

• The opportunity to work alongside best-in-class professionals from over 40 different countries
• Ownership over initiatives that directly solve business problems
• 401(k) match up to 50% and fully paid health insurance
• 25 paid vacation days alongside market holidays
• Extensive office perks, including breakfast, lunch and snacks, regular social events, clubs, sporting leagues and more

Who you are:

• Familiarity with the market microstructure of the US Equities and/or US ETF markets
• Strong engineering instincts and a deep understanding of computer science fundamentals
• Programming experience across C++ or C with other object-orientated languages also considered
• Experience building low-latency trading systems on a large scale including across market data ingestion, order routing and execution performance
• Experience with exchange connectivity, order matching, and execution logic for major venues
• Experience optimizing high-throughput systems that must process and react in real-time to streams of market data
• Familiarity with building and integrating FPGA-assisted trading systems
• Innovative, big-picture thinking grounded in real-world pragmatism
• Readiness to set technical direction, promote strong engineering principles and continuously seek ways to refine and optimize systems in a fast-moving, ever evolving environment
• You can spot opportunities to enhance performance, efficiency, and maintainability

Who we are:

At Optiver, our mission is to improve the market by injecting liquidity, providing accurate pricing, increasing transparency and stabilizing the market no matter the conditions. With a focus on continuous improvement, we prioritize safeguarding the health and efficiency of the markets for all participants. As one of the largest market making institutions, we are a respected partner on 100+ exchanges across the globe.

Our differences are our edge. Optiver does not discriminate on the basis of race, religion, color, sex, gender identity, sexual orientation, age, physical or mental disability, or other legally protected characteristics.

About the Position

We are looking to hire an Engineer with experience in both software and hardware design to help us build our FPGA-based applications. 

We're big believers in the ability of tools to make programming faster, more pleasant, and more reliable. We apply these same principles to our FPGA Engineering work, and we’re looking for people who are interested in using programming language technology to improve the process of designing, testing, and validating hardware designs. We use Hardcaml, an OCaml library for succinctly describing hardware in RTL. Hardcaml is tightly integrated into our development environment, so you’ll also gain lots of exposure to the libraries and tools that are foundational to our internal systems. No previous knowledge of Hardcaml is required.

In this role, you’ll work on the ground-up design and implementation of new FPGA applications, and help extend and refine the high-level design and testing tools that we use internally. Your day-to-day work will predominantly involve OCaml & Hardcaml, for both RTL design and testing/integration, but you can also expect to work with some Verilog and C. While you don’t need to have worked with OCaml specifically, a good background in typed programming languages is a plus.

If you’d like to learn more, you can read about our interview process, meet some of our newest hires, or check out our OCaml All The Way Down talk and Programmable Hardware podcast episode.

About You

We don’t expect you to have a background in OCaml, finance, or any other specific field—we’re looking for smart programmers who will approach hardware design with a software engineering mindset. We’re more interested in how you think and learn than what you currently know. You should be:

• A top-notch programmer with a love for technology
• Comfortable with a software programming language
• Intellectually curious, collaborative, and eager to learn
• Humble and unafraid to ask questions and admit mistakes
• Experienced with a Hardware Description (or Construction) language (VHDL, Verilog, Chisel, Pymtl, or other), for both writing and testing hardware designs
• Experienced working with FPGA vendor tools (Vivado or Quartus)
• Experienced with building a working FPGA project through an academic, professional, or personal project
• Interested in learning how to use FPGAs in the context of networking

If you're a recruiting agency and want to partner with us, please reach out to agency-partnerships@janestreet.com.

HFT Software Developer – Junior & Senior Levels

About DeepFin Research

DeepFin Research is a proprietary high-frequency trading (HFT) firm powered by cutting-edge Deep Learning (DL) and Deep Reinforcement Learning (DRL). We've brought on teammates from Nvidia, DeepMind, CitSec, Graviton, Tower, Jump, and others, and are aggressively working across cutting edge AI research and traditional quant research methods to monetise our AI generated signals across the global financial markets.

The Role

We are looking for exceptional HFT software engineers to build our HFT trading infrastructure across global finanacial markets, including different asset classes, end-to-end from the ground up. This will include working across connectivity, market data, execution, risk, and building high performance high throughput C++ systems.

Responsibilities

• Design, implement, and optimize ultra-low-latency, zero-allocation trading engines in modern C++.
• Develop and maintain market data handlers and execution gateways utilizing protocols like FIX, OUCH, ITCH, and raw UDP multicast.
• Optimize system critical paths through OS-level tuning, CPU pinning, cache-line optimization, and NUMA-aware programming.
• Interface with hardware-accelerated components, working alongside FPGA engineers to integrate PCIe/DMA data pipelines.
• Implement kernel-bypass networking solutions (e.g., Solarflare OpenOnload, DPDK) to minimize network stack latency.
• Collaborate directly with AI researchers and quantitative traders to deploy complex quantitative models into strict, latency-sensitive production environments.
• Work end-to-end on projects from the ground up – this is not a role to focus on specialised parts of the infrastructure stack, but rather to see projects through end-to-end.

Ideal Candidate Profile

• 1–3 years of experience in low-latency software engineering for Junior candidates; 3–10+ years for Senior candidates.
• Exceptional expertise in C++ with a deep understanding of lock-free data structures, custom memory allocators, and hardware architecture.
• Proven experience building systems in HFT or highly concurrent, real-time computing environments.
• Strong grasp of Linux internals, network programming (TCP/IP, UDP), and performance profiling tools (e.g., perf, VTune).
• Solid understanding of futures markets microstructure; exposure to FX and options markets is a strong plus.
• Entrepreneurial mindset with the communication skills required to thrive in a fast-paced, highly collaborative environment, preferring end-to-end ownership over extreme specialization.

HFT Quantitative Developer

About DeepFin Research

DeepFin Research is a proprietary high-frequency trading (HFT) firm powered by cutting-edge Deep Learning (DL) and Deep Reinforcement Learning (DRL). We've brought on teammates from Nvidia, DeepMind, CitSec, Graviton, Tower, Jump, and others, and are aggressively working across cutting edge AI research and traditional quant research methods to monetise our AI generated signals across the global financial markets.

The Role

We are looking for exceptional quantitative developer with outstanding expertise at the intersection of quantitative research and C++ development to focus both on simulation and productionisation. This will include designing and building simulation across various financial markets, and taking high-frequency and mid-frequency alpha turning it into scalable, production-grade PnL across global exchanges.

Key Responsibilities

• Productionise research models into high-performance C++ systems used for live trading across multiple futures exchanges.
• Integrate and process L3/order-book data at scale, building and maintaining parsers, normalised book structures, and data pipelines.
• Develop and optimise execution logic, order placement strategies, queue-positioning logic, microstructure-aware order types, and latency-sensitive workflows.
• Collaborate closely with quant researchers to understand signals, model assumptions, and expected behaviours, ensuring seamless transition from prototypes into production code.
• Work with infra/engineering teams to deploy, monitor, and refine strategies in live environments; diagnose latency bottlenecks, instability, and performance drift.
• Build and maintain simulation/backtesting tools for microstructure-accurate evaluation of execution behaviour.
• Optional (desirable): support vol surface modelling, options execution logic, and cross-asset HFT monetisation.

Required Experience & Skills

• Must have Experience in HFT market making. 
• Outstanding C++ and Python expertise.
• Experience working with L3 and order-book data, market-data adapters, and high-throughput feed handling.
• Experience productionising HFT or mid-frequency strategies in live environments.
• Understanding of market microstructure: queue dynamics, adverse selection, order types, latency paths, tick-rule details.
• Ability to operate across both research and engineering disciplines: reading model code, understanding signals, and implementing robust production systems.
• Options experience is desirable
• FPGA experience is desirable