ABOUT THE TEAM 

The Anduril Imaging team develops state-of-the-art imaging systems across both hardware and software, deployed to tackle the most significant security challenges of America and its allies.  The team is heavily involved in utilizing computer vision, perception, electro-optical, infrared, and sensor data to give our war fighters and allies an advantage.   

ABOUT THE JOB 

The Imaging team is seeking a Firmware Engineer to help design a new product lines. In this role, you will work closely with an interdisciplinary technical team to define, complete the design and analysis, build prototypes leading to ground and flight testing, and mature the prototypes into products. 

WHAT YOU’LL DO 

• FPGA architecture, standards, development and review processes 
• FPGA Development: Designing, architecting, simulating, and integrating VHDL designs into FPGAs or Systems on Chip (SoC) for optimized performance, resource utilization, and power efficiency. 
• Hardware/Software Integration: Collaborating with multidisciplinary teams (electrical engineers, software engineers, systems engineers) to ensure seamless integration of the firmware with the overall system, including processor bring-up and board support packages. 
• Testing and Validation: Developing robust test benches in VHDL/Verilog and utilizing lab tools such as oscilloscopes and logic analyzers for rigorous testing and validation of designs against functional specifications and performance requirements. 
• Optimization: Optimizing the algorithms for hardware acceleration, including MIPS optimization and efficient use of on-chip bus protocols like AXI or AXI-Stream.  

REQUIRED QUALIFICATIONS 

• Education: A Bachelor's in Electrical Engineering, Computer Engineering, or a related technical field is typically required. 
• Experience: 2+ years of experience developing HDL firmware for FPGA devices  
• Hardware Description Languages: Expertise in VHDL and/or Verilog/SystemVerilog is essential for RTL (Register Transfer Level) design. 
• FPGA Tools: Experience with industry-standard FPGA design tools such as Xilinx Vivado or Intel Quartus. 
• Debugging Skills: Strong hardware/software debugging skills using standard lab equipment. 
• Version Control: Proficiency with version control systems (e.g., Git) for collaborative development. 
• Eligible to obtain and maintain an active U.S. Secret security clearance 

PREFERRED QUALIFICATIONS  

• Demonstrated experience designing with multi-gigabit SERDES, DDR memory busses, Ethernet MAC and PHY interfaces, FPGAs, and common communication busses like SPI and I2C 
• Embedded software development experience with the use of timers, interrupts, hardware peripherals such as SPI controllers and ADCs 
• Knowledge of embedded Linux development, including device trees, hardware drivers, bootloaders, and basic Unix/Linux tools 
• Familiar with common programming languages like Python and MATLAB 
• Familiarity with infrared image sensor technology 

At Tenstorrent, we believe the future of computing must be open, which is why our interns don’t just watch from the sidelines – they help build the core of it. We provide a "code-to-career" pipeline where students collaborate with industry experts to solve high-stakes problems in RISC-V and AI hardware-software co-design. By joining us, you are taking an internship to democratize high-performance computers that are accessible to everyone.

As a Design Verification Engineer Intern on the SoC Digital Verification team, you will help ensure the functional correctness and robustness of Tenstorrent’s next-generation RISC‑V and AI accelerator SoCs. You will work on building and improving modern verification environments, developing tests and checkers, and analyzing coverage to sign off complex digital IP and subsystems. Your work directly contributes to the reliability of the chips that power our AI and high‑performance computing roadmap.

We are looking for a minimum of 3 months for this role with the potential for extension to 6 months.

This role is hybrid, based in our Boston, MA office.

Who you are

• Pursuing a B.S. , M.S. or PhD. in Electrical Engineering, Computer Engineering, Computer Science, or a related field with a focus on digital design and verification.
• Strong understanding of digital logic design and computer architecture (pipelines, caches, interconnects, memory systems).
• Familiar with HDLs such as Verilog/SystemVerilog, and interested in learning Formal verification, Cocotb, and UVM‑based verification methodologies.
• Comfortable working in Linux-based development environments and using scripting languages (e.g., Python, Shell, Perl) to automate tasks.
• Detail-oriented problem solver who enjoys debugging complex issues, reasoning about corner cases, and working from specifications.
• Collaborative team member with clear communication skills, able to document work and discuss trade‑offs with RTL, architecture, and validation teams.

What We Need

• Help develop and maintain SystemVerilog/UVM testbenches for SoC IP blocks and subsystems, including stimulus, checkers, and scoreboards.
• Write and refine verification test plans from architectural and micro‑architectural specifications, with a strong focus on corner cases and coverage.
• Develop constrained‑random and directed tests, run regressions, and triage failures by working closely with RTL designers to root-cause issues.
• Analyze functional and code coverage results, identify gaps, and propose additional tests or checks to drive coverage closure.
• Contribute to automation and infrastructure (scripts, Makefiles, CI hooks, dashboards) that improve verification productivity and debug turnaround time.
• Partner with cross‑functional teams (architecture, design, performance, validation) to align on expected behavior and sign‑off criteria for silicon.
• Have impact measured through coverage metrics achieved, quality and reproducibility of bugs found, and robustness of the verification environment you help build.

What You Will Learn

• End‑to‑end SoC design and verification flow for cutting‑edge RISC‑V and AI accelerator architectures.
• Industry‑standard verification methodologies (SystemVerilog/UVM), including testbench architecture, stimulus generation, and scoreboard/checker design.
• Hands-on experience with simulation, regression, and coverage tools used in large‑scale industrial verification environments.
• How to read and interpret hardware specifications, micro‑architecture documents, and timing diagrams, and translate them into actionable tests and assertions.
• Exposure to high‑performance interconnects, memory controllers, and accelerators, and how they are verified at IP, subsystem, and SoC levels.
• Best practices for collaborating in a silicon development team, including code review, documentation, and cross‑site communication.

USA Hiring Timelines

This internship opportunity is available throughout our 3 terms with the following corresponding recruitment cycles:

• Winter Term: Jan–Apr work term, Sept–Dec recruit.
• Summer Term: May–Aug work term, Oct–Apr recruit.
• Fall Term: Sept–Dec work term, Jan–Aug recruit.

Please note these timelines are for reference only. Actual timelines may vary.